DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on 27 February 2026, with respect to claims 6-7 and 12-14 have been fully considered and are persuasive. The 35 U.S.C. § 112 (b) rejection of claims 6-7 and 12-14 has been withdrawn.
Applicant’s arguments, see Remarks, filed on 27 February 2026, with respect to the rejections of claims 1-11, 16-17, and 19-23 under 35 U.S.C. § 102 and the rejections of claims 1-4, 6-12, 15, 17-19, and 21-13 under 35 U.S.C. § 103 have been fully considered and are persuasive. The examiner notes that neither Dogiamis nor Han does not teach the amended limitation of “a bottom surface of the fluidic cooling unit is entirely non-metal, wherein the bottom surface of the fluidic cooling unit is disposed on and directly bonded to a surface.” For example, Dogiamis relies on conductive bond pads (214, see Fig. 12) in when directly bonding the interposer (204) with the first semiconductor die (206). Furthermore, Dogiamis does not teach the amended limitation of “wherein the fluidic cooling unit is horizontally adjacent to the at least one second semiconductor element.” Therefore, the rejection has been withdrawn. However, upon further search and considerations, a new ground of rejection is made using Chainer in view of Kim and Enquist. See rejection below.
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-11, 15, 17-23 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chainer (US 2017/0186728 A1) and further in view of Kim US 2012/0211199 A1) and Enquist (US 9,564,414 B2).
Regarding claim 1, Chainer teaches a microelectronic device (1100, Fig. 11) comprising:
a first semiconductor element (1106-1; ¶ [0059]: 1106-1 is a cooling unit; ¶ [0026]: cooling units may be made of silicon; hence 1106-1 is a semiconductor element );
at least one second semiconductor element (108 or 1106-2 or 110 or 1106-3; see ¶ [0023],[0026]: these elements are semiconductor dies and/or cooling units) disposed on the first semiconductor element; and
a fluidic cooling unit (1122), wherein a bottom surface (bottom surfaces of 1122 that contact 1106-1) of the fluidic cooling unit is disposed on to a surface (top surfaces of 1106-1 that contact the bottom surfaces of 1122) of the first semiconductor element and wherein the fluidic cooling unit is horizontally adjacent to the at least one second semiconductor element (as shown in Fig. 11, portions of 1122 are horizontally adjacent to any one of the second semiconductor elements), the fluidic cooling unit comprising a cavity structure (1124 & 1126) to contain a fluid (see ¶ [0059] ), the fluidic cooling unit to transfer heat away from the first semiconductor element (¶ [0059]: 1122 used to provide cooling fluid to channels 1120 of the first semiconductor element 1106-1; hence 1122 is a fluidic cooling unit that is used to transfer heat away from the first semiconductor element ).
Chainer further teaches the fluidic cooling unit to be a manifold (see ¶ [0059] ). However, Chainer does not teach the fluidic cooling unit, wherein a bottom surface of the fluidic cooling unit is entirely non-metal.
Kim, in the same field of invention, teaches a manifold (110, see Fig. 1) wherein a bottom surface (bottom surface of lower portion 104 of the manifold) of the manifold is entirely non-metal (¶ [0052] : silicon).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Chainer to change the unknown composition of the manifold, i.e., fluidic cooling unit of Chainer, to that of silicon, such that the entire bottom surface of the manifold becomes non-metallic. The ordinary artisan would have been motivated to modify Chainer in the manner set forth above for at least the purpose of preventing corrosion of cooling manifolds that are primarily composed of metals, with the corrosion caused to due to water exposure, by changing the composition of the manifolds from metal to that of a silicon (Kim ¶ [0006] ).
Chainer in view of Kim further teaches the fluidic cooling unit (Kim ¶ [0072] ) and the first semiconductor element (Chainer ¶ [0027]: 106 made of two silicon die; dies are known in the art to have come from wafers ) to be made from silicon wafers. However, Chainer in view of Kim does not teach directly bonding the fluidic cooling unit to the top surface of the first semiconductor element.
Enquist, in the same field of invention, teaches direct bonding (Col. 7, Ln. 19) of two silicon wafers (16 and 10; see Fig. 3; also see Col. 6, Lns 64-67).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Enquist into the device of Chainer in view of Kim to directly bond the bottom surface of the fluidic cooling unit to the top surface of the first semiconductor element. The ordinary artisan would have been motivated to modify Chainer in view of Kim in the manner set forth above for at least the purpose of improving the device density and reducing the cost of manufacturing of semiconductor devices (Col. 1, Ln. 24 to Col. 2, Ln. 29).
Regarding claim 2, the microelectronic device of Claim 1, wherein fluid is transported through the cavity structure by a fluidic system (see Chainer ¶ [0059]).
Regarding claim 3, the microelectronic device of Claim 1, wherein the cavity structure is formed of one or more electrically non-conducting or semiconducting materials (see Kim (¶ [0052] : silicon).
Regarding claim 5, the microelectronic device of Claim 1, wherein the cavity structure comprises a cap structure without a bottom wall (Chainer Fig. 11 shows 112 to be a U-shaped structure), wherein the cap structure is directly bonded to the first semiconductor element without an intervening adhesive (Enquist teaches the use Van der Waal forces boding agent instead of adhesives; see Col. 7 Ln. 11-13).
Regarding claim 6, the microelectronic device of Claim 1, wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122; see Chainer Fig. 11) disposed on the first semiconductor element (Fig. 11 shows these vertical walls directly contact 1106-1), and wherein a coefficient of thermal expansion (CTE) of the bottom wall (Kim ¶ [0052]: fluidic cooling unit made of silicon) is similar to a CTE of the first semiconductor element (Chainer ¶ [0026]: first semiconductor element made of silicon).
Regarding claim 7, the microelectronic device of Claim 1, wherein the first semiconductor element comprises silicon (Chainer ¶ [0026]: first semiconductor element made of silicon), wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122; see Chainer Fig. 11) disposed on the first semiconductor element (Fig. 11 shows these vertical walls directly contact 1106-1), and wherein a coefficient of thermal expansion (CTE) of the bottom wall (Kim ¶ [0052]: fluidic cooling unit made of silicon) is similar to the CTE of silicon.
Regarding claim 8, the microelectronic device of Claim 1, wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122; see Chainer Fig. 11) disposed on the first semiconductor element (Fig. 11 shows these vertical walls directly contact 1106-1), and wherein a coefficient of thermal expansion (CTE) of the bottom wall (Kim ¶ [0052]: fluidic cooling unit made of silicon; CTE of silicon: 2.49 µm/m-°C; as evidenced by Matweb, see NPL mailed 21 February 2025) is lower than that of copper (CTE of copper: 16.4 µm/m-°C; as evidenced by Matweb, see NPL mailed 21 February 2025).
Regarding claim 9, the microelectronic device of Claim 1, wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122; see Chainer Fig. 11) disposed on the first semiconductor element (Fig. 11 shows these vertical walls directly contact 1106-1), and wherein a coefficient of thermal expansion (CTE) of the bottom wall (CTE of silicon: 2.49 µm/m-°C; as evidenced by Matweb, see NPL mailed 21 February 2025) is lower than 10 µm/m°C.
Regarding claim 10, the microelectronic device of Claim 1, wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122; see Chainer Fig. 11) disposed on the first semiconductor element (Fig. 11 shows these vertical walls directly contact 1106-1), and wherein the bottom wall comprises silicon (Kim ¶ [0052]: fluidic cooling unit made of silicon).
Regarding claim 11, the microelectronic device of Claim 1, wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122; see Chainer Fig. 11) disposed on the first semiconductor element (Fig. 11 shows these vertical walls directly contact 1106-1), and wherein the bottom wall is directly bonded to the first semiconductor element without an intervening adhesive (Enquist teaches the use Van der Waal forces boding agent instead of adhesives; see Col. 7 Ln. 11-13).
Regarding claim 15, Chainer et al. teach the microelectronic device of Claim 1 and further teach: the at least one second semiconductor element to be made of silicon wafers (see Chainer ¶ [0023], [0027]; it is commonly known in the art that dies are made from silicon wafers). However, Chainer et al. do not teach: wherein the at least one second semiconductor element is directly bonded to the first semiconductor element without an intervening adhesive.
Enquist, in the same field of invention, teaches direct bonding (Col. 7, Ln. 19) of two silicon wafers (16 and 10; see Fig. 3; also see Col. 6, Lns 64-67) without an intervening adhesive (Enquist teaches the use Van der Waal forces boding agent instead of adhesives).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Enquist into the device of Chainer et al. to directly bond at least one of the second semiconductor elements to the first semiconductor element without an intervening adhesive. The ordinary artisan would have been motivated to modify Chainer et al. in the manner set forth above for at least the purpose of improving the device density of semiconductor devices (Col. 1, Ln. 24 to Col. 2, Ln. 29).
Regarding claim 17, Chainer teaches a method of forming a microelectronic device (1100, Fig. 11), the method comprising:
providing a first semiconductor element (1106-1; ¶ [0059]: 1106-1 is a cooling unit; ¶ [0026]: cooling units may be made of silicon; hence 1106-1 is a semiconductor element ); and
bonding a second semiconductor element (108; see ¶ [0023]: 108 is a semiconductor die) and a fluidic cooling unit (1122) to the first semiconductor element, such that the second semiconductor element and a bottom surface of the fluidic cooling unit are disposed on a surface (top surface of 1106) of the first semiconductor element and the fluidic cooling unit is horizontally adjacent to the second semiconductor element (Fig. 11 shows vertical portions of 1122 being horizontally adjacent to 108),
wherein the bottom surface (bottom surfaces of the vertical portions of 1122) of the fluidic cooling unit is bonded to the surface of the first semiconductor element,
wherein the fluidic cooling unit comprises a cavity structure (1124 and 1126) to contain a fluid (¶ [0059], [0065]: coolant), the fluidic cooling unit to transfer heat away from the first semiconductor element (¶ [0059]: 1122 used to provide cooling fluid to channels 1120 of the first semiconductor element 1106-1; hence 1122 is a fluidic cooling unit that is used to transfer heat away from the first semiconductor element ).
Chainer further teaches the fluidic cooling unit to be a manifold (see ¶ [0059] ). However, Chainer does not teach the bottom surface of the manifold is entirely non-metal.
Kim, in the same field of invention, teaches a manifold (110, see Fig. 1) wherein a bottom surface (bottom surface of lower portion 104 of the manifold) of the manifold is entirely non-metal (¶ [0052] : silicon).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Chainer to change the unknown composition of the manifold, i.e., fluidic cooling unit, of Chainer to that of silicon, such that the entire bottom surface of the manifold becomes non-metallic. The ordinary artisan would have been motivated to modify Chainer in the manner set forth above for at least the purpose of preventing corrosion of cooling manifolds that are primarily composed of metals, with the corrosion caused to due to water exposure, by changing the composition of the manifolds from metal to that of a silicon (Kim ¶ [0006] ).
Chainer in view of Kim further teaches the fluidic cooling unit (Kim ¶ [0072] ) and the first semiconductor element (Chainer ¶ [0027] ) to be made from silicon wafers. However, Chainer in view of Kim does not teach the method further comprising of directly bonding the bottom surface of the fluidic cooling unit to the top surface of the first semiconductor element.
Enquist, in the same field of invention, teaches direct bonding (Col. 7, Ln. 19) of two silicon wafers (16 and 12; see Fig. 3; also see Col. 6, Lns 64-67).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Enquist into the device of Chainer in view of Kim to directly bond the bottom surface of the fluidic cooling unit to the top surface of the first semiconductor element. The ordinary artisan would have been motivated to modify Chainer in view of Kim in the manner set forth above for at least the purpose of improving the device density of semiconductor devices (Col. 1, Ln. 24 to Col. 2, Ln. 29).
Regarding claim 18, Chainer et al. teach the method of Claim 17, and further teach: the at least one second semiconductor element to be made of silicon wafers (see Chainer ¶ [0023], [0027]; it is commonly known in the art that dies are made from silicon wafers). However, Chainer et al. do not teach: wherein bonding the second semiconductor element comprises directly bonding the second semiconductor element to the first semiconductor element without an intervening adhesive.
Enquist, in the same field of invention, teaches direct bonding (Col. 7, Ln. 19) of two silicon wafers (16 and 10; see Fig. 3; also see Col. 6, Lns 64-67) without an intervening adhesive (Enquist teaches the use Van der Waal forces boding agent instead of adhesives).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Enquist into the device of Chainer et al. to directly bond at least one of the second semiconductor elements to the first semiconductor element without an intervening adhesive. The ordinary artisan would have been motivated to modify Chainer et al. in the manner set forth above for at least the purpose of improving the device density of semiconductor devices (Col. 1, Ln. 24 to Col. 2, Ln. 29).
Regarding claim 19, the method of Claim 17, wherein the fluidic cooling unit comprises a bottom wall (any of the vertical walls of 1122 that directly contacts 1106-1; see Chainer Fig. 11), and wherein bonding the fluidic cooling unit comprises directly bonding the bottom wall to the first semiconductor element without an intervening adhesive (Enquist teaches the use Van der Waal forces boding agent instead of adhesives; see Col. 7 Ln. 11-13).
Regarding claim 20, the method of Claim 17, further comprising forming the cavity structure by directly bonding a cap structure without a bottom wall (Chainer Fig. 11 shows 112 to be a U-shaped structure ) to the first semiconductor element.
Regarding claim 21, Chainer teaches a microelectronic device comprising:
a first semiconductor element (1106-1; ¶ [0059]: 1106-1 is a cooling unit; ¶ [0026]: cooling units may be made of silicon; hence 1106-1 is a semiconductor element ); and
a fluidic cooling unit (1122), wherein a bottom surface bottom surfaces of 1122 that contact 1106-1) of the fluidic cooling unit is bonded to a surface (top surfaces of 1106-1 that contact the bottom surfaces of 1122) of the first semiconductor element, wherein the fluidic cooling unit comprising a cavity structure (1124 & 1126) to contain a fluid (¶ [0059], [0065]: coolant).
Chainer further teaches the fluidic cooling unit to be a manifold (see ¶ [0059] ). However, Chainer does not teach the bottom surface of the fluidic cooling unit is entirely non-metal.
Kim, in the same field of invention, teaches a manifold (110, see Fig. 1) wherein a bottom surface (bottom surface of lower portion 104 of the manifold) of the manifold is entirely non-metal (¶ [0052] : silicon).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Chainer to change the unknown composition of the manifold, i.e., fluidic cooling unit of Chainer, to that of silicon, such that the entire bottom surface of the manifold becomes non-metallic. The ordinary artisan would have been motivated to modify Chainer in the manner set forth above for at least the purpose of preventing corrosion of cooling manifolds that are primarily composed of metals, with the corrosion caused to due to water exposure, by changing the composition of the manifolds from metal to that of a silicon (Kim ¶ [0006] ).
Chainer in view of Kim further teaches the fluidic cooling unit (Kim ¶ [0072] ) and the first semiconductor element (Chainer ¶ [0027] ) to be made from silicon wafers. However, Chainer in view of Kim does not teach directly bonding the fluidic cooling unit to the first semiconductor element without an adhesive to form a dielectric-to-dielectric direct bond.
Enquist, in the same field of invention, teaches direct bonding (Col. 7, Ln. 19) of two silicon wafers (16 and 12; see Fig. 3) without an adhesive (Enquist teaches the use Van der Waal forces boding agent instead of adhesives; see Col. 7 Ln. 11-13) to form a dielectric-to-dielectric direct bond (17 and 12 are dielectrics, i.e., SiO2; see Col. 6, Lns. 45-47 and Col. 7, Lns. 1-6).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Enquist into the device of Chainer in view of Kim to directly bond the bottom surface of the fluidic cooling unit to the top surface of the first semiconductor element, without the use of an adhesive and instead forming a dielectric-to-dielectric bond. The ordinary artisan would have been motivated to modify Chainer in view of Kim in the manner set forth above for at least the purpose of improving the device density of semiconductor devices (Col. 1, Ln. 24 to Col. 2, Ln. 29).
Regarding claim 22, the microelectronic device of Claim 21, further comprising at least one second semiconductor element (108 or 1106-2 or 110 or 1106-3; see Chainer Fig. 11 and ¶ [0023]: these elements are semiconductor dies) disposed on the first semiconductor element.
Regarding claim 23, the microelectronic device of Claim 22, wherein the fluidic cooling unit reduces a heat flow through the at least one second semiconductor element (see Chainer ¶ [0059] ).
Regarding claim 26, the microelectronic device of Claim 1, wherein the first semiconductor element comprises an integrated device die (Chainer ¶ [0059]: 1106-1 is a cooling unit; ¶ [0027]: cooling unit 106 constructed of two silicon die halves).
Claims 4 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chainer (US 2017/0186728 A1) in view of Kim US 2012/0211199 A1) and Enquist (US 9,564,414 B2) as applied to claim 1 above, and further in view of Dogiamis (US 2022/0399249 A1).
Regarding claim 4, Chainer et al. teach the microelectronic device of Claim 1, but do not teach: wherein an interior surface of the cavity structure comprises features configured to increase turbulence in the fluid.
Dogiamis, in the same field of invention, teaches a fluidic cooling unit (440, see Fig. 24A) wherein an interior surface (inner surface of 442) of the cavity structure (442) comprises features configured to increase turbulence in the fluid.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Dogiamis into device of Chainer et al. to make the interior surface of the cavity structure of the fluidic cooling unit be configured to increase the turbulence of the cooling fluid. The ordinary artisan would have been motivated to modify Chainer et al. in the manner set forth above for at least the purpose of improving the heat dissipation properties of the fluidic cooling unit (Dogiamis ¶ [0065] ).
Regarding claim 24, the microelectronic device of Claim 4, wherein the features comprise an array of pillars (Dogiamis ¶ [0065] ).
Claims 16 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chainer (US 2017/0186728 A1) in view of Kim US 2012/0211199 A1) and Enquist (US 9,564,414 B2) as applied to claim 1 above, and further in view of Chan (US 2021/0183723 A1).
Regarding claim 16, Chainer et al. teach the microelectronic device of Claim 1, but do not teach the device further comprising a heat sink disposed on the at least one second semiconductor element.
Chan, in the same field of invention, teaches a device further comprising a heat sink (28) disposed on the at least one second semiconductor element (25).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chan into the device of Chainer et al. to dispose a heat sink on the at least one second semiconductor element. The ordinary artisan would have been motivated to modify Chainer et al. in the manner set forth above for at least the purpose of improving the heat dissipation of the microelectronic device by transferring the internal heat of the device to external surroundings (Chan ¶ [0034]).
Regarding claim 25, the microelectronic device of Claim 16, wherein the fluidic cooling unit is configured to transfer heat from the first semiconductor element to the heat sink (Chainer ¶ [0059] teaches using fluidic cooling unit 1122 to remove heat from 1106-1; since the heat sink of Chan is mounted on top of 1122, then the heat sink is configured to transfer heat from the first semiconductor device).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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