DETAILED ACTION
This Office action is in response to the amendment filed 30 December 2025. By this amendment, claims 14, 17-18, 21, and 31-33 are amended. Claims 14-33 are currently pending; claims 21-33 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 14 as amended have been considered but are moot because the grounds of rejection have been modified in response to Applicant’s amendments to the claims. The amended limitations are addressed by the modified grounds of rejection below.
Claim Rejections - 35 USC § 112
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "a second material" in line 14. Since “a second material” is also recited in line 9, it is unclear whether the recitation of line 14 is intended to refer to the same “second material” of line 9 or a different material. For the purposes of examination, the latter is assumed.
Claim 17 recites the limitation "the first material" in line 14. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, it is assumed “the first material” refers to a material.
Claims 18-20 depend directly or indirectly from claim 17 and thus also contain the above indefinite language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over CN 110838471 A to Chen et al. (citations refer to the English machine translation provided with the Non-Final Office action mailed 7 October 2025; hereinafter “Chen”) in view of US 2015/0129894 A1 to Kinoshita et al. (hereinafter “Kinoshita”).
Regarding independent claim 14, Chen (Fig. 19) discloses a device, comprising:
a semiconductor body 22 (p. 7, para. 3) of silicon carbide including a surface (top; Fig. 19);
an insulating structure 24 (p. 7, para. 5) on the surface of the semiconductor body (Fig. 19);
an interface layer 302 (p. 9, para. 8) on the insulating structure 24, and the interface layer is a made of a silicon nitride (SiN) material;
a passivation layer 400 (p. 6, second to last para.) on the interface layer 302, the passivation layer having an anchoring element including: a protrusion (portion of 400 disposed in region 31) that extends, starting from the passivation layer, completely through the interface layer 302 and at least in part through the insulating structure 24 (Fig. 19), the protrusion terminates within the insulating structure 24 before reaching the surface of the semiconductor body 22 and has a monolithic body with the passivation layer (Fig. 19; p. 6, third to last para.), and the protrusion is spaced laterally outward from the protection ring and extends into the second portion of the insulating structure.
Chen discloses a doped region 23 (p. 6, last para.) within the semiconductor body and at the surface of the semiconductor body (Fig. 19), the insulating structure 24 having a first portion on the doped region 23 and a second portion extends laterally outward from the doped region (Fig. 19), however fails to expressly disclose said doped region is a protection ring. Chen also fails to expressly disclose: the insulating structure having a first portion on the protection ring and a second portion extends laterally outward from the protection ring; a junction-barrier (JB) element including one or more doped regions spaced inward from the protection ring. In the same field of endeavor, Kinoshita (Fig. 1) discloses a protection ring 3 (¶ 0048) within a semiconductor body 1/2 (¶ 0047) and at the surface of the semiconductor body (Fig. 1); and a JB element 4 (¶ 0048) including one or more doped regions 4 paced inward from the protection ring (Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a protection ring and JB element as disclosed in Kinoshita in the device of Chen, the combination thus also disclosing the insulating structure 24 having a first portion on the protection ring and a second portion extends laterally outward from the protection ring, for the purpose of providing a JBS diode with decreased leak current and low on-resistance (¶ 0030).
Regarding claim 15, Chen and Kinoshita discloses discloses the anchoring element according to claim 14, Chen (Fig. 19) discloses further comprising: a first portion (portion of 400 extending into 302) extending in the interface layer 302 at a first distance from the surface and having, in a direction parallel to a first axis parallel to the surface, a maximum dimension having a first value (Fig. 19, first value = width of portion of 400 disposed in the opening of 302); and a second portion (portion of 400 extending from bottom of 302 into 24) extending in the insulating structure 24 in structural continuation of the first portion and having, in a direction parallel to the first axis, a respective maximum dimension having a second value greater than the first value (Fig. 19, second value = width of portion of 400 at the interface of 301 and 24).
Regarding claim 16, Chen and Kinoshita disclose the anchoring element according to claim 15, Chen (Fig. 19) further discloses wherein said second portion (portion of 400 extending from bottom of 302 into 24) of the anchoring element extends in part inside or completely through the insulating structure 24 (Fig. 19 - extends in part inside).
Regarding independent claim 17, as best understood, Chen (Fig. 19) discloses a device, comprising:
a semiconductor body 22 (p. 7, para. 3) of silicon carbide including a surface (top);
a first insulating layer 24 (p. 7, para. 5) on the surface of the semiconductor body;
a stacked insulating structure 24/301 comprising:
a second insulating layer 301 (p. 10, para. 6 - TEOS), of a second material, on the first insulating layer 24 (Fig. 19); and
a layer of metal material 25 (p. 7, third to last para.) extending in part on the surface of the semiconductor body 22 and in part on the first insulating layer 24 (Fig. 19);
an interface layer 302 (p. 9, para. 8) on the second insulating layer 301 and on the layer of metal material 25, the interface layer 302 is made of a second material (p. 9, paras. 5, 8 - polyimide) different from the first material (silane or TEOS-based oxide);
a passivation layer 400 (p. 6, second to last para.) on the interface layer 302 (Fig. 19); and
an anchoring element (portion of 400 disposed in region 31) of the passivation layer 400 that protrudes towards the first insulating layer 24 and extends completely through an opening of the interface layer 302 and terminates within the stacked insulating structure 24/301, the anchoring element having at least one dimension, in a direction parallel to said surface, greater than a corresponding dimension of the opening (Fig. 19 - portion of 400 below opening in 302 has width greater than opening 302).
Chen discloses a doped region 23 (p. 6, last para.) within the semiconductor body and at the surface of the semiconductor body (Fig. 19), the first insulating layer 24 including a first portion on the doped region 23 and a second portion extends laterally outward from the doped region (Fig. 19), the anchoring element (portion of 400 disposed in region 31) is spaced laterally from the doped region 23 (Fig. 19); however fails to expressly disclose said doped region is a protection ring. Chen also fails to expressly disclose: the first insulating layer having a first portion on the protection ring and a second portion extends laterally outward from the protection ring; a junction-barrier (JB) element including one or more doped regions spaced inward from the protection ring. In the same field of endeavor, Kinoshita (Fig. 1) discloses a protection ring 3 (¶ 0048) within a semiconductor body 1/2 (¶ 0047) and at the surface of the semiconductor body (Fig. 1); and a JB element 4 (¶ 0048) including one or more doped regions 4 paced inward from the protection ring (Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a protection ring and JB element as disclosed in Kinoshita in the device of Chen, the combination thus also disclosing the insulating structure 24 having a first portion on the protection ring and a second portion extends laterally outward from the protection ring, for the purpose of providing a JBS diode with decreased leak current and low on-resistance (¶ 0030).
Regarding claim 18, Chen and Kinoshita disclose the electronic device according to claim 17, Chen (Fig. 19) discloses further wherein the interface layer 302 couples the passivation layer 400 to the stacked insulating structure 24/301 (Fig. 19), and the interface layer 302 is configured to favor adhesion of the passivation layer 400 with the stacked insulating structure 24/301 (Fig. 19 - opening in 302 facilitates contact between 400 and 24).
Regarding claim 19, Chen and Kinoshita disclose the electronic device according to claim 17, Chen (Fig. 19) further discloses: wherein the anchoring element (portion of 400 disposed in region 31) extends throughout a first thickness of the interface layer 302 and a second thickness of the first insulating layer 24 (Fig. 19).
Regarding claim 20, Chen and Kinoshita disclose the device according to claim 17, Chen (Fig. 19) (Fig. 19) further discloses: wherein the anchoring element (portion of 400 disposed in region 31) extends throughout a first thickness of the interface layer 302 and part of a second thickness of the first insulating layer 24, and the anchoring element terminates within the first insulating layer 24 before reaching the surface of the semiconductor body 22 (Fig. 19).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
8 May 2026
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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