DETAILED ACTION
This Office action is in response to the amendment filed 30 December 2025. By this amendment, claims 1, 6-8 are amended; claims 2 and 4 are cancelled; claim 9 is new. Claims 1, 3, and 5-9 are currently pending; claims 6-7 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 30 December 2025 have been fully considered but they are not persuasive.
Regarding the drawing objection, Applicant argues “that one skilled in the art would clearly understand these features in view of the existing drawings and their related description in the present application.” (Remarks, p. 5.) Applicant’s argument notwithstanding, 37 CFR 1.83(a) requires drawings show every feature of the invention specified in the claims. Thus, the drawing objection is maintained and repeated below.
Regarding claim 1 as amended, Applicant argues that there is no motivation to combine Terai with Arai because Terai is concerned with peeling caused by thermal stress and Arai does not disclose a “technology regarding ‘thermal stress brought about by a temperature cycle during an operation of the semiconductor device.’” (Remarks, pp. 6-7.) Examiner respectfully disagrees; one of ordinary skill in the art would recognize that considerations of thermal stress and damage occurring during the manufacturing process (e.g., dicing), among other concerns, are not mutually exclusive. Rather, the consideration of multiple factors, including the effect of thermal stress and reduction of damage occurring during the manufacturing process, is necessary in order to form a functional semiconductor device. Thus, the prior art reads on the claims as currently drafted.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “trench gate [] provided in the cell region” (as in claim 1) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0162219 A1 to Terai et al. (hereinafter “Terai”) in view of JP 2020-4881 to Asai et al. (citations refer to the English machine translation filed with the 14 November 2024 IDS; hereinafter “Asai”).
Regarding independent claim 1, Terai (Figs. 11-12) discloses a semiconductor device comprising:
a semiconductor element PD (not labeled in Fig. 12; see ¶ 0022) diced into a square shape in top view from a semiconductor wafer (Figs. 11-12; ¶ 0054); and
a sealing resin sealing the semiconductor element (¶ 0059), wherein
the semiconductor element includes a cell region 1 (¶ 0022) through which a main current flows, a terminal region (Fig. 12 - dotted line border region around 1) provided on an outer peripheral side of the cell region, and a protective film 2/7 (¶ 0053) covering an upper surface of an outer peripheral portion of the terminal region (¶ 0053),
the protective film 2/7 includes spread portions spreading to outermost ends at four corners of the semiconductor element (Fig. 12 - 7 at corners; ¶ 0054), and
the spread portions have a cut section 6 (¶ 0037) continuous with a cut section 6 of the terminal region (Figs. 11-12), and the protective film does not spread to the outermost ends of the terminal region in four sides (Figs. 11-12 - substrate surface 3 is uncovered; ¶ 0033) excluding the four corners of the semiconductor element (Fig. 12 - four corners are covered by 7; ¶ 0054),
the protective film 2/7 contains polyimide (¶ 0022).
Terai fails to expressly disclose: a trench gate is provided in the cell region, a step portion having a depth equal to that of the trench gate is provided in a portion of the terminal region covered with the spread portion, and the spread portions are provided on the step portion. In the same field of endeavor, Asai (Figs. 1-3) discloses a semiconductor device 1 having a trench gate (¶ 0014) in a trench 34 (¶ 0014; Fig. 2) formed together with step portion 12 (¶ 0023; Fig. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Terai to include the semiconductor device as in Asai, thus providing spread portions on the step portion, for the purpose of providing a functional device (IGBT) in an art recognized way, and to provide the step portion having a depth equal to that of the trench gate provided as recited to reduce the number of steps required to manufacture the device and to suppress chipping during the dicing process (Asai, ¶ 0007).
Regarding claim 3, Terai and Asai disclose the semiconductor device according to claim 1, however fail to expressly disclose wherein the spread portions spread at least 200 μm in the four corners of the semiconductor element to the outermost ends. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a spread of at least 200 µm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the size of the protective film, and thus the spread portions, is considered a result effective variable because it affects the ability of the protective film to prevent peeling and cracking (Terai, ¶¶ 0065-66). Thus the ordinary artisan would have been motivated to modify the size of the protective film and the spread of its spread portions according to the application and to minimize peeling and cracking.
Regarding claim 5, Terai and Asai disclose the semiconductor device according to claim 1, wherein a semiconductor material of the semiconductor element is SiC (Terai, ¶ 0058).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Terai and Asai as applied to claim 1 above, and further in view of US 2018/0241391 A1 to Chandrasekaran et al. (hereinafter “Chandrasekaran”).
Regarding claim 8, Terai and Asai disclose a semiconductor device according to claim 1, including a switching element such as an IGBT or MOSFET (¶ 0058), however fails to expressly disclose: a power conversion apparatus comprising: a conversion circuit including a semiconductor device according to claim 1, and configured to convert and output input power; a drive circuit configured to output a drive signal for driving the semiconductor device; and a control circuit configured to output a control signal for controlling the drive circuit.
In the same field of endeavor, Chandrasekaran discloses a power conversion apparatus comprising: a conversion circuit including IGBTs and MOSFETs, and configured to convert and output input power; a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit (¶ 0002). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the semiconductor device of Terai and Asai in the power conversion apparatus of Chandrasekaran for the purpose of providing necessary components, IGBTs and MOSFETs, in an art-recognized, conventional manner (as exemplified by Terai, ¶ 0058).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Terai and Asai as applied to claim 1 above, and further in view of US 2020/0020604 A1 to Kim et al. (hereainfter “Kim”).
Regarding claim 9, Terai and Asai disclose the semiconductor device according to claim 1, however fails to expressly disclose: wherein the step portion has a chamfered shape including a polygonal shape or a curved surface.
In the same field of endeavor, Kim (Fig. 5B) discloses a semiconductor device including an edge portion having a chamfered shape 134GR (¶ 0084) including a polygonal shape or a curved surface (Fig. 5B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the shape of Kim in the step portion of the semiconductor device of Terai and Asai for the purpose of reducing chipping and cracking of the semiconductor device during the dicing process.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
13 May 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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