DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/20/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/20/2026was filed after the mailing date of the final rejection on 1/20/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: 26, 27, 33-36, 42, 43, 44, 46, and 56-59 rejected, 37 and 39 objected
Present action: 26, 27, 33-36, 42, 43, 44, 46, and 56-59 rejected, 37 and 39 objected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 26, 33, 34, 36, 56, and 57 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen (US 2022/0037268) in view of Lee (US 2023/0187294)
Regarding claim 26.
Shen teaches:
A method comprising: providing a first assembly (fig 26,27:690; [para 0066]) comprising a substrate (fig 26,27:622; [para 0069]) and one or more layers (fig 26,27:642,638; [para 0066]) comprising a front surface bonding dielectric (fig 26,27:638; [para 0066]) and a conductor (fig 26,27:642; [para 0066]) embedded in the front surface bonding dielectric (fig 26,27:638; [para 0066]), the front surface bonding dielectric (fig 26,27:638; [para 0066]) and the conductor (fig 26,27:642; [para 0066]) embedded therein forming at least part of a hybrid bonding surface (fig 27; [para 0066]), the one or more layers (fig 26,27:642,638; [para 0066]) disposed on a top surface of the substrate (fig 26,27:622; [para 0069]), the one or more layers (fig 26,27:642,638; [para 0066]) and the substrate (fig 26,27:622; [para 0069]) comprising a plurality of devices (fig 26,27:608,618; [para 0066])to be singulated into dies (fig 27:612; [para 0071]) and a scribe region (fig 27,28:516; [para 0066]) separating the devices (fig 27,30:608,618; [para 0066]);
forming at least one trench (fig 27:655; [para 0066]) in the one or more layers (fig 26,27:642,638; [para 0066])hybrid bonding ([para 0066]) the first assembly (fig 26,27:690; [para 0066]) to a second assembly (fig 26,27:500; [para 0066]), the at least one trench (fig 27:655; [para 0066]) separating the devices (fig 27,30:608,618; [para 0066]) and at least partially overlapping with the scribe region (fig 27,28:516; [para 0066]);
and depositing a fill dielectric material (fig 28:660; [para 0072]) in the at least one trench (fig 27:655; [para 0066]) to completely fill the at least one trench (fig 28:655; [para 0066]).
Shen does not teach forming the trench before hybrid bonding the first and second assemblies.
Lee teaches:
A method comprising: providing a first assembly (fig 19:1900; [para 0065]) comprising a substrate (fig 19:102; [para 0065]) and one or more layers (fig 19,23:110,2302; [para 0070])
forming at least one trench (fig 19:122; [para 0065]) in the one or more layers (fig 19,23:110,2302; [para 0070]) before hybrid bonding ([para 0071]) the first assembly (fig 23:101a; [para 0071]) to a second assembly (fig 24:101b; [para 0071]);
and depositing a fill dielectric material (fig 20:120; [para 0070]) in the at least one trench (fig 19:122; [para 0065]) to completely fill the at least one trench (fig 20:122; [para 0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the trench before the hybrid bonding the assemblies in order to that the dielectric stack may be protected from damage that may be caused by subsequent wafer processing (paragraph 20)
Regarding claim 33.
Shen in view of Lee teaches the method of claim 26.
Shen teaches:
bonding the hybrid bonding surface to a carrier wafer (fig 26:500; [para 0066]); and removing a portion of the substrate (fig 26,27:622; [para 0069]), wherein the removing begins at a bottom surface of the substrate (fig 27:622; [para 0069]) and extends a distance toward the hybrid bonding surface (fig 27; [para 0069]).
Regarding claim 34.
Shen in view of Lee teaches the method of claim 33.
Lee teaches:
removing the portion of the substrate (fig 24,25:102; [para 0072]) exposes the fill dielectric material (fig 25:120; [para 0072]) in the at least one trench (fig 25:122; [para 0072]).
Regarding claim 36.
Shen in view of Lee teaches the method of claim 26
Shen teaches:
The at least one trench (fig 27:655; [para 0071])comprises two sub trenches (fig 27:655; [para 0071]) formed in the scribe region (fig 27:516; [para 0071]), wherein a center portion of the scribe region (fig 27:516; [para 0071]) is substantially unchanged (fig 27).
Regarding claim 56.
Shen in view of Lee teaches the method of claim 26
Lee teaches:
a bottom surface of the at least one trench (fig 19:122; [para 0065]) is at or below the top surface of the substrate (fig 19:102; [para 0065]).
Regarding claim 57.
Shen in view of Lee teaches the method of claim 56
Lee teaches:
the at least one trench (fig 19:122; [para 0065]) extends through a thickness of the substrate (fig 19:102; [para 0065]).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen (US 2022/0037268) in view of Lee (US 2023/0187294) as applied to claim 26 and further in view of Montgomery (US 2017/0069578).
Regarding claim 27.
Shen in view of Lee teaches elements of the claimed invention in claim 26 above.
Shen in view of Lee does not teach a buffer layer in the trench.
Montgomery teaches:
before depositing the fill dielectric material (fig 2c:244; [para 0031]) in the at least one trench (fig 2b:230; [para 0031]), forming a trench buffer layer (fig 2c:242; [para 0031]) in the at least one trench (fig 2b:230; [para 0031]).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to provide a buffer layer in the trench in order to avoid chipping and cracking during singulation (Montgomery paragraph 17)
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen (US 2022/0037268) in view of Lee (US 2023/0187294) as applied to claim 34 and further in view of Hedler (US 2003/0143819).
Regarding claim 35.
Shen in view of Lee teaches the method of claim 34 above.
Shen teaches:
dicing (fig 30:292; [para 0074]) the first assembly (fig 30:690; [para 0074]), the dicing (fig 30:292; [para 0074]) comprising separating the plurality of devices into the dies (fig 30:695; [para 0075]) by cutting (fig 30,31; [para 0074])
Shen in view of Lee does not teach cutting through the fill dielectric in the trench.
Hedler teaches:
dicing (fig 3c:270; [para 0055]) comprises cutting through the fill dielectric (fig 3b:21’; [para 0055]) in the trench (fig 1b:21; [para 0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cut through the fill dielectric in the trench in order to reduce edge chipping (Hedler paragraph 7)
Claim(s) 42, 43, 44, 46, and 58 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0187294) in view of Shen (US 2022/0037268)
Regarding claim 42
Lee teaches:
A method comprising: providing a first wafer (fig 23:101a; [para 0070]) comprising a first front surface (fig 23), a first plurality of devices (fig 23:104; [para 0060])to be singulated into first dies ([para 0076]) and at least one first trench (fig 23:122; [para 0065]) formed in the first front surface (fig 19; [para 0065]), the at least one first trench (fig 23:122; [para 0065]) , the at least one first trench (fig 23:122; [para 0065]) filled with a first dielectric material (fig 20: 120; [para 0031]) that is different from a second dielectric material (fig 23:110; [para 0030]) in adjacent first metallization layers (fig 23:116; [para 0061]) of the first plurality of devices (fig 23:104; [para 0064]), wherein the first wafer (fig 23:101a; [para 0071]) comprises a first hybrid bonding surface ([para 0071]) at the first front surface (fig 23), the first hybrid bonding surface ([para 0071]) comprising a first bonding dielectric (fig 23:2304; [para 0070]) and a first conductor (fig 23:2306; [para 0070]) in electrical communication with the first metallization layers (fig 23:116; [para 0070]);
providing a second wafer (fig 24:101b; [para 0071]) comprising a second front surface (fig 24), a second plurality of devices (fig 24:104; [para 0060]) to be singulated into second dies ([para 0076]) and at least one second trench (fig 24:122; [para 0066]) formed in the second front surface (fig 24), the at least one second trench (fig 24:122; [para 0066]) , the at least one second trench (fig 24:122; [para 0066]) filled with a third dielectric material (fig 24:120; [para 0031]) that is different from a fourth dielectric material (fig 24:110; [para 0030]) in adjacent second metallization layers (fig 24:116; [para 0061]) of the second plurality of devices (fig 24:104; [para 0060]), wherein the second wafer (fig 24:101b; [para 0071]) comprises a second hybrid bonding surface ([para 0071]) at the second front surface (fig 24; [para 0071]), the second hybrid bonding surface ([para 0071]) comprising a second bonding dielectric (fig 24:2304; [para 0070]) and a second conductor (fig 24:2306; [para 0070]) in electrical communication with the second metallization layers (fig 24:116; [para 0061]);
and directly bonding the first hybrid bonding surface of the first wafer (fig 24:101a; [para 0071]) to the second hybrid bonding surface of the second wafer (fig 24:101b; [para 0071]) by directly bonding the first bonding dielectric (fig 24:2304; [para 0071])to the second bonding dielectric (fig 24:2304; [para 0071]) and directly bonding the first conductor (fig 24:2306; [para 0070]) to the second conductor (fig 24:2306; [para 0070]), wherein the at least one first trench (fig 24:122; [para 0066]) and the at least one second trench (fig 24:122; [para 0066]) are formed (fig 19,20; [para 0065]) before directly bonding the first hybrid bonding surface to the second hybrid bonding surface (fig 24; [para 0071]).
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Lee does not teach the trenches separate at least two devices.
Shen teaches:
A method comprising: providing a first wafer (fig 2:122; [para 0023]) comprising a first front surface, a first plurality of devices (fig 2:118; [para 0024]) to be singulated into first dies (fig 30,31:695; [para 00744,0075]) and at least one first trench (fig 27:655; [para 0070]) formed in the first front surface, the at least one first trench (fig 27:655; [para 0070]) separating at least two of the first plurality of devices (fig 2,27:118,518; [para 0024]), the at least one first trench (fig 27:655; [para 0070]) filled with a first dielectric material (fig 28:660; [para 0072]);
providing a second wafer (fig 26:600; [para 0069]) comprising a second front surface, a second plurality of devices (fig 26:608; [para 0066]) to be singulated into second dies (fig 30,31:612; [para 0071]) and at least one second trench (fig 27:655; [para 0070]) formed in the second front surface, the at least one second trench (fig 27:655; [para 0070]) separating at least two of the second plurality of devices (fig 26:608; [para 0066]), the at least one second trench filled with a third dielectric material (fig 28:660; [para 0072])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide trenches between at least two of a plurality of device in order to extend the sealing ring structure to between individual die, thereby providing each die with provide mechanical stress support and to provide a seal against humidity penetration (paragraph 19)
Regarding claim 43.
Lee in view of Shen teaches the method of claim 42
Lee teaches:
the first dielectric material (fig 24:120; [para 0067]) has a higher dielectric constant (silicon nitride k= 7 to 9 ; [para 0031]) than the second dielectric material (fig 24:110, silicon dioxide k = 3.9 to 4.1 ; [para 0030]), wherein the third dielectric material (fig 24:120; [para 0067]) has a higher dielectric constant (silicon nitride k= 7 to 9 ; [para 00311]) than the fourth dielectric material (fig 24:110, silicon dioxide k = 3.9 to 4.1 ; [para 0030]).
Regarding claim 44
Lee in view of Shen teaches the method of claim 42
Lee teaches:
thinning the second wafer (fig 25:101b; [para 0072]) after directly bonding (fig 24,25; [para 0072]).
Regarding claim 46.
Lee in view of Shen teaches the method of claim 44
Lee teaches:
the first dielectric material (fig 24:120; [para 0031]) and the second dielectric material (fig 24:110; [para 0030]) are inorganic (silicon oxide, silicon nitride).
Regarding claim 58.
Lee in view of Shen teaches the method of claim 42
Lee teaches:
the first metallization layers (fig 17:116; [para 0061]) are disposed over a first bulk semiconductor layer (fig 17:102; [para 0061]) and the second metallization layers (fig 17,24:116; [para 0061]) are disposed over a second bulk semiconductor layer (fig 17,24:102; [para 0061]), wherein the at least one first trench (fig 19,24:122; [para 0065]) extends to or into the first bulk semiconductor layer (fig 20:102; [para 0066]) and the at least one second trench (fig 19,24:122; [para 0066]) extends to or into the second bulk semiconductor layer (fig 19,24:102; [para 0066]).
Claim(s) 59 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0187294) in view of Shen (US 2022/0037268) as applied to claim 58 and further in view of Yu (US 2018/0158749)
Regarding claim 59.
Lee in view of Shen teaches the method of claim 58 above.
Lee teaches:
the at least one first trench (fig 25:122; [para 0065])and the at least one second trench (fig 25:122; [para 0065])extends completely through the second wafer (fig 25:101b,102; [para 0065]).
Lee in view of Shen does not teach that the at least one first trench extends completely through the first wafer.
Yu teaches
at least one first trench (fig 15:217; [para 0060]) extends completely through the first wafer (fig 15:221; [para 0060]) and the at least one second trench (fig 15:227; [para 0060]) extends completely through the second wafer (fig 15:231; [para 0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first trench to extend completely through the first substrate and the second trench to extend completely through the second substrate in order to facilitate the stacking of a plurality of substrates into a stack (Lee fig 49, paragraph 103) by provide multiple level of substrates that comprises the seal structure completely through the substrate.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied rejections over Shen (US 2022/0037268) in combination with Lee (US 2023/0187294) teaches all elements of the amended claims.
Allowable Subject Matter
Claims 37 and 39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 37, the prior art does not teach removing a portion of the substrate that aligns with the at least one trench while not removing a portion of the substrate that aligns with the plurality of devices, wherein the removing exposes the fill dielectric material; removing the fill dielectric material; and forming a second dielectric material in the at least one trench in combination with the other elements of the claim.
Regarding claim 39, the prior art does not teach forming a second trench in the substrate by removing a portion of the substrate that aligns with the at least one trench while not removing a portion of the substrate that aligns with the plurality of devices, wherein the removing exposes the fill dielectric material; and forming a second dielectric material in the second trench in combination with the other elements of the claims.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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