DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to Fig. 2 in the Applicant’s response dated 12 November 2025. The objection to the drawings as described in the previous office action has been withdrawn.
The Examiner acknowledges the arguments presented by the Applicant in the remarks filed 12 November 2025 and has withdrawn the rejections to claims 1-7 and 11 based upon the previously presented non-final office action filed on 18 August 2025. The new grounds of rejection are outlined in the non-final office action below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Katsuji Iguchi (US 2018/0254226 A1; hereinafter “Iguchi”) in further view of Hideaki Nezu (JP 2014072330 A; hereinafter “Nezu”).
Regarding Claim 1, Iguchi teaches an LED circuit board structure, comprising:
a plurality of first color LEDs, each of the first color LEDs comprising a first P-type electrode and a first N-type electrode (202 and 13, Fig. 2 and Fig. 8, para [0115] and para [0077] describes a red LED 202 wherein the red LED corresponds to red LED chip 13 which comprises a cathode and an anode wherein there exists a plurality of red LEDs on the pixel array 2 of Fig. 4);
a plurality of second color LEDs, each of the second color LEDs comprising a second P-type electrode and a second N-type electrode (203 and 14, Fig. 2 and Fig. 8, para [0115] and para [0078] describes a green LED 203 wherein the green LED corresponds to green LED chip 14 which comprises a cathode and an anode wherein there exists a plurality of green LEDs on the pixel array 2 of Fig. 4);
a plurality of third color LEDs, each of the third color LEDs comprising a third P-type electrode and a third N-type electrode (204 and 15, Fig. 2 and Fig. 8, para [0115] and para [0079] describes a blue LED 204 wherein the blue LED corresponds to blue LED chip 15 which comprises a cathode and an anode wherein there exists a plurality of blue LEDs on the pixel array 2 of Fig. 4);
a plurality of integrated circuit chips, each of the integrated circuit chips electrically connecting each of the first color LEDs, each of the second color LEDs and each of the third color LEDs (205, Fig. 8, para [0116] describes wherein the driver ICs 205 are electrically connected to the first color LEDs 202, second color LEDs 203, and third color LEDs 204 on their respective pixel package);
a carrier board (100, Fig. 4, para [0091] describes a base substrate wherein pixel substrates are arranged) comprising a carrying surface (201a, Fig. 9, para [0116] describes the third principal surface 201a wherein the LED chips are disposed) and a bottom surface opposite (201b, Fig. 9, para [00172] describes a fourth principal surface 201b on the bottom of the substrate) to each other, the carrying surface comprising a plurality of pixel-front-side-pattern regions disposed in intervals (200, Fig. 4, para [0091] describes wherein the base substrate is comprised of a plurality of pixel substrates 200 which comprise pixel front-side patterns), the bottom surface comprising a plurality of pixel-back-side-pattern regions respectively corresponding to the pixel-front-side-pattern regions (Fig. 9, para [0113] describes wherein every third principal surface (carrying surface) has a corresponding fourth principal surface (bottom surface) on an opposite side), wherein one of the first color LEDs, one of the second color LEDs, one of the third color LEDs and one of the integrated circuit chips are disposed in one of the pixel-front-side-pattern regions (201a, Fig. 9, para [0116] describes wherein the first color, second color, and third color LED chips are disposed on the third principal surface (carrying surface));
a plurality of first P-type pads located at the carrying surface of the carrier board, wherein one of the first P-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the first P-type electrodes (Fig. 9, para [0117] describes a surface electrode pad of an LED chip facing the pixel-front-side-pattern wherein the electrode pad effectively mounts the first P-type electrode to the carrying surface 201a);
a plurality of second P-type pads located at the carrying surface of the carrier board, wherein one of the second P-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the second P-type electrodes (Fig. 9, para [0117] describes a surface electrode pad of an LED chip facing the pixel-front-side-pattern wherein the electrode pad effectively mounts the second P-type electrode to the carrying surface 201a);
a plurality of third P-type pads located at the carrying surface of the carrier board, wherein one of the third P-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the third P-type electrodes (Fig. 9, para [0117] describes a surface electrode pad of an LED chip facing the pixel-front-side-pattern wherein the electrode pad effectively mounts the third P-type electrode to the carrying surface 201a);
a plurality of first color pads located at the carrying surface of the carrier board (217, Fig. 8 and Fig. 9, para [0131] describes connection pads which can be seen as being located at the carrying surface 201a), wherein one of the first color pads is disposed at one of the pixel-front-side-pattern regions for mounting a first pin of the integrated circuit chip that is disposed at the same pixel-front-side-pattern region (217, Fig. 8 and Fig. 9, para [0131] describes wherein connection pads connect the IC chip 205 at a pixel-front-side-pattern), and for electrically connecting the first P-type pad that is disposed at the same pixel-front-side-pattern region (217, Fig. 8 and Fig. 9, para [0131] describes wherein the IC chip is connected to the LED chips, comprising the P-type pads, through the connection pads 217);
a plurality of second color pads located at the carrying surface of the carrier board (217, Fig. 8 and Fig. 9, para [0131] describes connection pads which can be seen as being located at the carrying surface 201a), wherein one of the second color pads is disposed at one of the pixel-front-side-pattern regions for mounting a second pin of the integrated circuit chip that is disposed at the same pixel-front-side-pattern region (217, Fig. 8 and Fig. 9, para [0131] describes wherein connection pads connect the IC chip 205 at a pixel-front-side-pattern), and for electrically connecting the second P-type pad that is disposed at the same pixel-front-side-pattern region (217, Fig. 8 and Fig. 9, para [0131] describes wherein the IC chip is connected to the LED chips, comprising the P-type pads, through the connection pads 217);
a plurality of third color pads located at the carrying surface of the carrier board (217, Fig. 8 and Fig. 9, para [0131] describes connection pads which can be seen as being located at the carrying surface 201a), wherein one of the third color pads is disposed at one of the pixel-front-side-pattern regions for mounting a third pin of the integrated circuit chip that is disposed at the same pixel-front-side-pattern region (217, Fig. 8 and Fig. 9, para [0131] describes wherein connection pads connect the IC chip 205 at a pixel-front-side-pattern), and for electrically connecting the third P-type pad that is disposed at the same pixel-front-side-pattern region (217, Fig. 8 and Fig. 9, para [0131] describes wherein the IC chip is connected to the LED chips, comprising the P-type pads, through the connection pads 217);
a plurality of first testing wires located at the carrying surface of the carrier board (206, Fig. 8, para [0114] describes a testing wiring pattern 206); and
a plurality of first connecting wires (112, Fig. 11, para [0097] describes a connecting wiring layer),
Iguchi fails to explicitly teach a plurality of first testing wires located at the carrying surface of the carrier board, wherein one of the first testing wires is disposed at one of the pixel-front-side-pattern regions and extends from the first P-type pad or the first color pad that is disposed at the same pixel-front-side-pattern region; and a plurality of first connecting wires, each of the first connecting wires electrically connecting two of the first testing wires of adjacent two of the pixel-front-side-pattern regions in parallel.
However, Nezu teaches a similar LED circuit board structure a plurality of first testing wires located at the carrying surface of the carrier board (TS, annotated Fig. 1 depicts testing wires TS) , wherein one of the first testing wires is disposed at one of the pixel-front-side-pattern regions and extends from the first P-type pad or the first color pad that is disposed at the same pixel-front-side-pattern region (13, 14 and TS, annotated Fig. 1, PE2E English Machine Translation page 2 describes a pair of conductive lands from which testing wires TS extend wherein testing wires TS are disposed at one of a pixel front side pattern region of circuit board 1); and
a plurality of first connecting wires (CS, annotated Fig. 1 depicts connecting wires CS), each of the first connecting wires electrically connecting two of the first testing wires of adjacent two of the pixel-front-side-pattern regions in parallel (CS, annotated Fig. 1, PE2E English Machine translation page 2 describes wherein connecting wire CS portions of the testing wires TS outside of separation regions 15 connect testing wires of the light emitting diodes in parallel).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Iguchi with Nezu to further disclose an LED circuit board structure comprising testing wires disposed at pixel front-side-pattern regions and extending from a first pad wherein said testing are connected by a connecting wire in parallel for adjacent pixel patterns in order to provide the advantage of being able to test adjacent light emitting diodes at a same time so that a defective light emitting diode can be easily identified (Nezu, PE2E English Machine Translation page 3).
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Regarding Claim 2, the combination of Iguchi and Nezu teach the LED circuit board structure of claim 1, further comprising:
a plurality of second testing wires located at the bottom surface of the carrier board, wherein one of the second testing wires is disposed at one of the pixel-back-side-pattern regions and electrically connects the second P-type pads or the second color pads that is disposed at the pixel-front-side-pattern region where the one of the pixel-back-side-pattern corresponds (Iguchi, TG, 211, 206, and 111, Fig. 8 and Fig. 11, para [0172] describes wherein the external connection pad 211 corresponding to and electrically connected to the second P-type pad for sending a test signal TG, is electrically connected to a second testing wire 111 of the wiring pattern on the fourth principal 201b (pixel-back-side)).
a plurality of second connecting wires, each of the second connecting wires electrically connecting two of the second testing wires of adjacent two of the pixel-back-side-pattern regions in parallel (Iguchi, 112, Fig. 11, para [0097] and para [0108] describes wherein the base substrate comprises a second wiring layer 112 wherein the second wiring layer is electrically connected to first wiring layer 111 thus electrically connecting adjacent pixel-back-side pattern regions in parallel);
a plurality of third testing wires located at the bottom surface of the carrier board, wherein one of the third testing wires is disposed at one of the pixel-back-side-pattern regions and electrically connects the third P-type pads or the third color pads that is disposed at the pixel-front-side-pattern region where the one of the pixel-back-side-pattern corresponds (Iguchi, TB, 211, 206, and 111, Fig. 8 and Fig. 11, para [0172] describes wherein the external connection pad 212 corresponding to and electrically connected to the third P-type pad for sending a test signal TB, is electrically connected to a second testing wire 111 of the wiring pattern on the fourth principal 201b (pixel-back-side)).; and
a plurality of third connecting wires, each of the third connecting wires electrically connecting two of the third testing wires of adjacent two of the pixel-back-side-pattern regions in parallel (Iguchi, 112, Fig. 11, para [0097] and para [0108] describes wherein the base substrate comprises a second wiring layer 112 wherein the second wiring layer is electrically connected to first wiring layer 111 thus electrically connecting adjacent pixel-back-side pattern regions in parallel).
Regarding Claim 3, the combination of Iguchi and Nezu teach the LED circuit board structure of claim 2, wherein each of the first testing wires extends from each of the first color pads in each of the pixel-front-side-pattern regions (Nezu, 13, 14 and TS, annotated Fig. 1, PE2E English Machine Translation page 2 describes a pair of conductive lands from which testing wires TS extend wherein testing wires TS are disposed at one of a pixel front side pattern region of circuit board 1), each of the second testing wires of each of the pixel-back-side-pattern regions electrically connects each of the second color pads via a conducting hole (Iguchi, TG, 211, 206, and 111, Fig. 8 and Fig. 11, para [0172] describes wherein the external connection pad 211 corresponding to and electrically connected to the second P-type pad for sending a test signal TG, is electrically connected to a second testing wire 111 of the wiring pattern on the fourth principal 201b (pixel-back-side)), and each of the third testing wires of each of the pixel-back-side-pattern regions electrically connects each of the third color pads via another conducting hole (Iguchi, 112, Fig. 11, para [0097] and para [0108] describes wherein the base substrate comprises a second wiring layer 112 wherein the second wiring layer is electrically connected to first wiring layer 111 thus electrically connecting adjacent pixel-back-side pattern regions in parallel).
Regarding Claim 4, the combination of Iguchi and Nezu teach the LED circuit board structure of claim 3, further comprising:
a plurality of first N-type pads located at the carrying surface of the carrier board (Iguchi, 217, Fig. 9, para [0117] describes a surface electrode pad of an LED chip facing the pixel-front-side-pattern wherein the N-type electrode pad is the right most connection pad 217), one of the first N-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the first N-type electrodes (Iguchi, 217 and 236, Fig. 9 and Fig. 10, para [0117] and para [0018] describes wherein the first N-type pad 217 is disposed at one the carrying surface 201a comprising the pixel-front-side pattern region wherein the first N-type pad mounts the N-type electrode 236 of the LED chip 202 to the pixel-front-side-pattern);
a plurality of second N-type pads located at the carrying surface of the carrier board (Iguchi, 217, Fig. 9, para [0117] describes a surface electrode pad of an LED chip facing the pixel-front-side-pattern wherein the N-type electrode pad is the right most connection pad 217), one of the second N-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the second N-type electrodes (Iguchi, 217 and 236, Fig. 9 and Fig. 10, para [0117] and para [0018] describes wherein the second N-type pad 217 is disposed at one the carrying surface 201a comprising the pixel-front-side pattern region wherein the second N-type pad mounts the N-type electrode 236 of the LED chip 202 to the pixel-front-side-pattern);
a plurality of third N-type pads located at the carrying surface of the carrier board (Iguchi, 217, Fig. 9, para [0117] describes a surface electrode pad of an LED chip facing the pixel-front-side-pattern wherein the N-type electrode pad is the right most connection pad 217), one of the third N-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the third N-type electrodes, wherein each of the first N-type pads, each of the second N-type pads and each of the third N-type pads are electrically connected (Iguchi, 217 and 236, Fig. 9 and Fig. 10, para [0117] and para [0018] describes wherein the first N-type pad 217 is disposed at one the carrying surface 201a comprising the pixel-front-side pattern region wherein the third N-type pad mounts the N-type electrode 236 of the LED chip 202 to the pixel-front-side-pattern); and
a plurality of fourth connecting wires located at the carrying surface of the carrier board (Iguchi, FCW, annotated Fig. 8, displays a fourth connecting wire at the carrying surface 201a of the carrier board), each of the fourth connecting wires electrically connecting two of the first N-type pads, two of the second N-type pads and two of the third N-type pads of adjacent two of the pixel-front-side-pattern regions in parallel (Iguchi, FCW, TGND, 214, annotated Fig. 8, para [0114] describes wherein the fourth connecting wire is electrically connected to the external connection pad 214 which receives a common test ground voltage through the connection wiring wherein the fourth connecting wire FCW of annotated Fig. 8 can be seen connecting the LED chips through the N-type pad on the right side of the chip).
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Regarding Claim 5, the combination of Iguchi and Nezu teach the LED circuit board structure of claim 4, further comprising a plurality of cutting lanes located at the carrier board (Nezu, 5, Fig. 1(a), PE2E machine translation page 2, describes a collective mounting board 3 is separated along the dividing line 5 into individual pieces to further comprise multiple individual mounting boards 4), wherein the first connecting wires, the second connecting wires, the third connecting wires and the fourth connecting wires are located at the cutting lanes (Nezu, annotated Fig. 1, PE2E machine translation page 2, describes test wiring TS and connecting wiring CS of a wire set 6 connecting the four light emitting diodes wherein the test wiring can be seen running along the dotted lines of the cutting lanes 5 and further wherein upon combining Iguchi with Nezu, the resulting second, third and fourth connecting wires would also be located at the cutting lanes 5).
Regarding Claim 11, Iguchi teaches an LED pixel package, comprising:
a carrier board (100, Fig. 4, para [0091] describes a base substrate wherein pixel substrates are arranged) comprising a carrying surface (201a, Fig. 9, para [0116] describes the third principal surface 201a wherein the LED chips are disposed);
a first color LED disposed on the carrying surface (202, Fig. 8, para [0115] and para [0116] describes a red LED 202 wherein the red LED is disposed on the carrying surface 201a);
a second color LED disposed on the carrying surface (203, Fig. 8, para [0115] and para [0116] describes a green LED 203 wherein the green LED is disposed on the carrying surface 201a);
a third color LED disposed on the carrying surface (204, Fig. 8, para [0115] and para [0116] describes a blue LED 204 wherein the blue LED is disposed on the carrying surface 201a);
an integrated circuit chip disposed on the carrying surface and electrically connecting the first color LED, the second color LED and the third color LED (205, Fig. 8, para [0116] describes wherein a driver IC 205 is electrically connected to the first color LEDs 202, second color LEDs 203, and third color LEDs 204);
a sealing layer covering the first color LED, the second color LED, the third color LED and the integrated circuit chip (para [0137 describes wherein an insulating resin may be used to cover the LED chips 202 to 204 and the driver IC 205); and
a first wire set disposed at the carrying surface and electrically connecting the first color LED and the integrated circuit chip (206, Fig. 8, para [0116] describes wherein the wiring pattern 206 electrically connects the driver IC and the LED chips mounted on the carrying surface 201a).
Iguchi fails to explicitly disclose wherein a part of the first wire set extends from the first color LED or the integrated circuit chip to an edge of the carrier board, wherein a top surface of the part is higher than the carrying surface of the carrier board to form a metal break surface at the edge.
However, Nezu teaches a similar LED circuit board structure wherein a part of the first wire set extends from the first color LED or the integrated circuit chip to an edge of the carrier board (6, TS and CS, annotated Fig. 1 and Fig. 2, PE2E English Machine Translation page 2 describes wherein a wire set 6 comprising test wires TS and connecting wires CS can be printed on a top surface of a carrier board 1 wherein Fig. 2 shows wiring set 6 at an edge of carrier board 1 and annotated Fig. 1 shows wherein wiring set 6 extends to an edge of separation regions 15 and extends from a first color LED D), wherein a top surface of the part is higher than the carrying surface of the carrier board to form a metal break surface at the edge (6, Fig. 2 depicts wherein a top surface of the part of the wire set 6 at an edge of the carrier board is higher than the carrying surface of the carrier board 1 wherein wire set 6 would result in a metal break surface).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Iguchi with Nezu to further disclose an LED circuit board structure comprising a wire set that extends from the first color LED to an edge of a carrier board and is higher than a carrying surface of a carrier board in order to provide the advantage of providing a break line across which the wire set extends so as to prevent an inconvenience such as a short circuit wherein portions of the wire set remain (Nezu, PE2E English Machine Translation page 4).
Claim 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Katsuji Iguchi (US 2018/0254226 A1; hereinafter “Iguchi”) in view of Hideaki Nezu (JP 2014072330 A; hereinafter “Nezu”) and in further view of Christopher Andrew Bower et al. (US 2022/0165918 A1; hereinafter “Bower”).
Regarding Claim 6, the combination of Iguchi and Nezu discloses all the limitations of claim 5.
The combination of Iguchi and Nezu fails to explicitly disclose the LED circuit board structure of claim 5, further comprising a plurality of first data wires, a plurality of second data wires, a plurality of third data wires and a plurality of fourth data wires, wherein each of the first data wires and each of the fourth data wires extend along a first direction and respectively electrically connect the first connecting wires and the fourth connecting wires, and each of the second data wires and each of the third data wires extend along a second direction and respectively electrically connect the second connecting wires and the third connecting wires.
However, Bower teaches a similar LED circuit board structure, further comprising a plurality of first data wires (14, Fig. 1, para [0031] describes row-select lines 14 that are configured to be control lines to provide data to controllers), a plurality of second data wires (16, Fig. 1, para [0031] describes column-data lines 16 that are configured to be control lines to provide data to controllers), a plurality of third data wires (16, Fig. 1, para [0031] describes column-data lines 16 that are configured to be control lines to provide data to controllers) and a plurality of fourth data wires (14, Fig. 1, para [0031] describes row-select lines 14 that are configured to be control lines to provide data to controllers), wherein each of the first data wires and each of the fourth data wires extend along a first direction and respectively electrically connect the first connecting wires and the fourth connecting wires (14 and 26, Fig. 1, para [0031] describes wherein the row-select lines run in a first horizontal direction and electrically connect the connecting pixel wires 26 in a first direction to send data signals along the pixel wires 26), and each of the second data wires and each of the third data wires extend along a second direction and respectively electrically connect the second connecting wires and the third connecting wires (16 and 26, Fig. 1, para [0031] describes wherein the column-data lines run in a second vertical direction and electrically connect the connecting pixel wires 26 in a second direction to send data signals along the pixel wires 26).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Iguchi and Nezu with the teachings of Bower to further disclose an LED circuit board structure comprising data wires that electrically connect the connecting wires along a first and second direction in order to provide the advantage of reducing pixel data rates (Bower, para [0019]).
Regarding Claim 7, the combination of Iguchi, Nezu, and Bower teaches the LED circuit board structure of claim 6, wherein line widths of each of the first data wires, each of the second data wires, each of the third data wires and each of the fourth data wires are in a range of 25 μm to 40 μm (Bower, 14 and 16, Fig. 1, para [0055] describes wherein the conductive wires (14 and 16) can have a line width in a range of less than one micron to less than 50 microns).
The combination of Iguchi, Nezu, and Bower fails to explicitly disclose the LED circuit board structure of claim 6, wherein a line distance between one of the first data wires and one of the fourth data wires adjacent thereto, and a line distance of one of the second data wires and one of the third data wires adjacent thereto are in a range of 40 μm to 50 μm.
However, Bower teaches in the disclosure of their invention, wherein a size of a light-diode of a pixel 20 can have a length and width in a range of less than 10 microns to less than 100 microns (para [0013]) and further wherein an interconnection wire, such as the data wires 14 and 16, can have a width in a range of 1 micron to 50 microns (para [0055]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size diodes and data wires resulting in line distances between the first and fourth data wires, and second and third data wires, in a range of 40 μm to 50 μm as each of the adjacent data wires from Bouche are found on either side of six diodes, wherein diodes with a width of less than 10 microns with data wires on either side could result in line distances in a range of 40 μm to 50 μm in order to provide the advantage of decreasing light emitter size leaving additional area on display substrates for more wiring to enable additional functionalities such as touch sensing circuits (Bower, para [0039]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Response to Arguments
Applicant’s arguments, see page 15, lines 1-15 and page 16, lines 1-13, filed 12 November 2025, with respect to the rejection of claims 1 and 11 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejections is made in view of prior art of record Hideaki Nezu (JP 2014072330 A) covering the limitations pointed out by the applicant that the prior art of record, Iguchi, does not appear to disclose. Applicant states that Iguchi, with respect to claim 1, does not appear to disclose or reasonably suggest “one of the first testing wires is disposed at one of the pixel-front-side pattern regions and extends from the first P-type pad or the first color pad that is disposed at the same pixel-front-side-pattern region” and “each of the first connecting wires electrically connecting two of the first testing wires of adjacent two of the pixel-front-side-pattern regions in parallel”. Examiner finds this argument persuasive; however prior art of record Hideaki Nezu (JP 2014072330 A) teaches a plurality of first testing wires located at the carrying surface of the carrier board (TS, annotated Fig. 1 depicts testing wires TS) , wherein one of the first testing wires is disposed at one of the pixel-front-side-pattern regions and extends from the first P-type pad or the first color pad that is disposed at the same pixel-front-side-pattern region (13, 14 and TS, annotated Fig. 1, PE2E English Machine Translation page 2 describes a pair of conductive lands from which testing wires TS extend wherein testing wires TS are disposed at one of a pixel front side pattern region of circuit board 1); and a plurality of first connecting wires (CS, annotated Fig. 1 depicts connecting wires CS), each of the first connecting wires electrically connecting two of the first testing wires of adjacent two of the pixel-front-side-pattern regions in parallel (CS, annotated Fig. 1, PE2E English Machine translation page 2 describes wherein connecting wire CS portions of the testing wires TS outside of separation regions 15 connect testing wires of the light emitting diodes in parallel) as outlined in the USC 103 rejection above.
Furthermore, Applicant states that Iguchi, with respect to claim 11, does not appear to disclose or reasonably suggest “a part of the first wire set extends from the first color LED or the integrated circuit chip to an edge of the carrier board, wherein a top surface of the part is higher than the carrying surface of the carrier board to form a metal break surface at the edge”. Examiner finds this argument persuasive; however prior art of record Hideaki Nezu (JP 2014072330 A) teaches wherein a part of the first wire set extends from the first color LED or the integrated circuit chip to an edge of the carrier board (6, TS and CS, annotated Fig. 1 and Fig. 2, PE2E English Machine Translation page 2 describes wherein a wire set 6 comprising test wires TS and connecting wires CS can be printed on a top surface of a carrier board 1 wherein Fig. 2 shows wiring set 6 at an edge of carrier board 1 and annotated Fig. 1 shows wherein wiring set 6 extends to an edge of separation regions 15 and extends from a first color LED D), wherein a top surface of the part is higher than the carrying surface of the carrier board to form a metal break surface at the edge (6, Fig. 2 depicts wherein a top surface of the part of the wire set 6 at an edge of the carrier board is higher than the carrying surface of the carrier board 1 wherein wire set 6 would result in a metal break surface) as outlined in the USC 103 rejection above..
Applicant's arguments filed 12 November 2025 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the signal is transmitted to the first P-type pad without passing into the integrated circuit chip”) are not recited in the rejected claim (1). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). However, as indicated above, the additional arguments presented regarding the limitations with respect to claim 1 are found persuasive. Therefore, the limitations presented in the argument found to be not persuasive have been withdrawn and a new ground of rejection has been made in view of the prior art of record Hideaki Nezu (JP 2014072330 A) in light of the persuasive arguments.
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898