DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Species I (claims 1-13) in the reply filed on 01/26/2026 is acknowledged.
The present invention includes the foreign document (Republic of Korea 10-2022-0064172) which was not translated into English, thus the filing date (05/25/2022) of the priority document is not perfected, and is not considered as a priority filing date.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7-8, 10, and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al. (U.S 2022/0310515 A1).
As to claim 1, LEE et al. disclose in Fig. 2A a three-dimensional semiconductor memory device, comprising:
a first substrate (4) comprising a cell array region (see “cell array region” as annotated in Fig. 2A below) and a contact region (see “contact region” as annotated in Fig. 2A below) (see annotated Fig. 2A below, para. [0039]);
a peripheral circuit structure (see “peripheral circuit structure” as annotated in Fig. 2A below) on the first substrate (4) (Fig. 2A, para. [0223]);
a cell array structure (see “cell array structure” as annotated in Fig. 2A below) on the peripheral circuit structure (see “peripheral circuit structure” as annotated in Fig. 2A below), wherein the cell array structure (see “cell array structure” as annotated in Fig. 2A below) comprises a stack structure (comprising 25, 38, 27g, 40g) comprising interlayer dielectric layers (25, 38) (Fig. 2A, para. [0044], [0048], [0052], [0055], [0057]-[0058], [0060]-[0062]) and gate electrodes (“gate layers” 27g, 40g) that are alternately stacked on the peripheral circuit structure (see “peripheral circuit structure” as annotated in Fig. 2A below) (Fig. 2A, para. [0048], [0052]-[0053], [0247]-[0249]),
a dielectric layer (comprising “intermediate insulating layers” 32, 44) on the stack structure (comprising 25, 38, 27g, 40g) (Fig. 2A, para. [0057]), and a second substrate (comprising layers 58, 63, 73, and 91) on the stack structure (comprising 25, 38, 27g, 40g) (Fig. 2A, para. [0083]-[0084]), wherein the gate electrodes (gate layers” 27g, 40g) comprise pad portions (“first gate pads” 27P) having a stepwise structure on the contact region (see “contact region” as annotated in Fig. 2A below) (see Fig. 2A, para. [0046], [0048], [0050], [0057]);
a vertical separation dam structure (“dam structure” 71) that penetrates the dielectric layer (comprising “intermediate insulating layers” 32, 44) and at least a portion of the stack structure (comprising 25, 38, 27g, 40g), wherein the vertical separation dam structure (“dam structure” 71) penetrates at least one of the pad portions (“first gate pads” 27P) (Fig. 2A, para. [0070], [0104], [0241]-[0243]);
a mold structure (comprising “external insulating layers” 19a, 19b, and “second insulating horizontal layers” 27i) that is adjacent to the vertical separation dam structure (“dam structure” 71), wherein the mold structure (comprising “external insulating layers” 19a, 19b, and “second insulating horizontal layers” 27i) comprises a dielectric material (Fig. 2A, para. [0053]-[0055], [0080] [0223], [0225], [0243]); and
through structures (87b,87c, 89) that penetrate the dielectric layer (comprising “intermediate insulating layers” 32, 44) and the mold structure (comprising “external insulating layers” 19a, 19b, and “second insulating horizontal layers” 27i) (Fig. 2A, para. [0223], [0225], [0254]-[0257]).
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As to claim 2, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein the mold structure (comprising “external insulating layers” 19a, 19b, and “second insulating horizontal layers” 27i) comprises residual interlayer dielectric layers (“external insulating layers” 19a, 19b) and residual sacrificial layers (“second insulating horizontal layers” 27i) that are alternately stacked, wherein the residual interlayer dielectric layers (“external insulating layers” 19a, 19b) are adjacent to respective ones of the interlayer dielectric layers (25, 38) opposite the vertical separation dam structure (“dam structure” 71), and wherein the residual sacrificial layers (“second insulating horizontal layers” 27i) are adjacent respective ones of the gate electrodes (gate layers” 27g, 40g) opposite the vertical separation dam structure (“dam structure” 71) (Fig. 2A, para.[0043], [0053]-[0056], [0080], [0223], [0225]).
As to claim 4, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein the through structures (87b,87c, 89) penetrate a portion of the second substrate (comprising layers 58, 63, 73, and 91), and wherein a top surface of each of the through structures (87b,87c, 89) is in contact with the second substrate (comprising layers 58, 63, 73, and 91) (Fig. 2A, para. [0083], [0088]).
As to claim 5, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the semiconductor memory device further comprising: a residual lower sacrificial layer (25) between the mold structure (comprising “external insulating layers” 19a, 19b, and “second insulating horizontal layers” 27i) and the second substrate (comprising layers 58, 63, 73, and 91) (Fig. 2A), wherein the residual lower sacrificial layer (25) is in contact with the vertical separation dam structure (“dam structure” 71), and wherein the through structures (87b,87c, 89) penetrate the residual lower sacrificial layer (25) (Fig. 2A).
As to claim 7, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the semiconductor memory device further comprising: vertical channel structures (“channel layer” 51) that penetrate the stack structure (comprising 25, 38, 27g, 40g) and have top surfaces in contact with the second substrate (comprising layers 58, 63, 73, and 91), wherein bottom surfaces of the through structures (87b,87c, 89) are coplanar with bottom surfaces of the vertical channel structures (“channel layer” 51) (Fig. 2A-3A, para. [0105]-[0107]).
As to claim 8, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein the cell array structure (see “cell array structure” as annotated in Fig. 2A below) further comprises conductive lines (see “conductive lines” as annotated in Fig. 2A below), connection contact plugs (see “connection contact plugs” as annotated in Fig. 2A below), and connection circuit lines (see “connection circuit lines” as annotated in Fig. 2A below) between the peripheral circuit structure (see “peripheral circuit structure” as annotated in Fig. 2A below) and the stack structure (comprising 25, 38, 27g, 40g), (Fig. 2A) (see annotated Fig. 2A below, para. [0039], [0041], [0079]-[0080]) and
wherein the through structures (87b,87c, 89) are electrically connected to the peripheral circuit structure (see “peripheral circuit structure” as annotated in Fig. 2A below) through the conductive lines (see “conductive lines” as annotated in Fig. 2A below), the connection contact plugs (see “connection contact plugs” as annotated in Fig. 2A below), and/or the connection circuit lines (see “connection circuit lines” as annotated in Fig. 2A below) (see annotated Fig. 2A below, para. [0039], [0041], [0079]-[0080]).
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As to claim 10, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein a top surface of the vertical separation dam structure (“dam structure” 71) is in contact with the second substrate (comprising layers 58, 63, 73, and 91) (Fig. 2A).
As to claim 12, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein the vertical separation dam structure (“dam structure” 71) has a polygonal or circular annular shape (“dam structure” 71 corresponding to a circular hole in layers 32, 44, Fig. 2A) when viewed in plan.
As to claim 13, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein an outer sidewall of the mold structure (comprising “external insulating layers” 19a, 19b, and “second insulating horizontal layers” 27i) is in contact with an inner sidewall of the vertical separation dam structure (“dam structure” 71) (Fig. 2A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 6, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (U.S 2022/0310515 A1) in view of LIM et al. (U.S 2022/0139456 A1).
As to claim 3, as applied to claims 1 and 2 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein the residual sacrificial layers (“second insulating horizontal layers” 27i) comprise silicon nitride (Fig. 2A, para. [0055]).
LEE et al. do not disclose the residual interlayer dielectric layers comprise silicon oxide.
LIM et al. disclose in Fig. 10A a three-dimensional semiconductor memory device, comprising: a vertical separation dam structure (DM) that penetrates the residual interlayer dielectric layers (112A, 112C), wherein the residual interlayer dielectric layers (112A, 112C) comprise silicon oxide (Fig. 10A, para. [0077]). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of LEE at el. by having the residual interlayer dielectric layers comprise silicon oxide, as taught by LIM et al., in order to improve performance, reliability and manufacturability.
As to claim 6, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations including the limitation: wherein each of the through structures (87b,87c, 89) is in a respective through structure hole (Fig. 2A), wherein ones of the through structures (87b,87c, 89) comprise: a barrier layer (“spacer layer” 65b) that conformally overlaps an inner sidewall and a bottom surface of the respective through structure hole (Fig. 2A, para. [0082]); and a conductive pattern (87a/87c) in an inner space of the respective through structure hole, the inner space being surrounded by the barrier layer in a plan view (Fig. 2A, para. [0078]-[0079], [0081]), and wherein the conductive pattern comprises at least one of a doped semiconductor, a metal (“peripheral contact plug”, para. [0078]-[0081]), or a transition metal.
LEE et al. do not disclose the barrier layer comprises at least one of titanium nitride or tantalum nitride.
LIM et al. disclose in Fig. 10A a three-dimensional semiconductor memory device, comprising: through structures (comprising ML & D180) comprises a barrier layer (THV), wherein the barrier layer (THV) comprises at least one of titanium nitride or tantalum nitride (Fig. 10A, para. [0101]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of LEE at el. by having a barrier layer comprises at least one of titanium nitride or tantalum nitride, as taught by LIM et al., in order to improve electrical performance and help to maintain stable memory states over time.
As to claim 11, as applied to claim 1 above, LEE et al. disclose in Fig. 2A all claimed limitations except for the limitation: wherein a bottom surface of each of the through structures and a bottom surface of the vertical separation dam structure are coplanar with each other.
LIM et al. disclose in Fig. 10A a three-dimensional semiconductor memory device, comprising: a bottom surface of each of the through structures (D180) and a bottom surface of the vertical separation dam structure (DM) are coplanar with each other (Fig. 10A, para. [0081]-[0083]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of LEE at el. by having a bottom surface of each of the through structures and a bottom surface of the vertical separation dam structure are coplanar with each other, as taught by LIM et al., in order to improve performance, safety, and efficiency.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached on M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 2, 2026
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