DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US PGpub: 2023/0074585 A1), hereinafter Huang, in view of BEN SHALOM (USPGpub: 2023/0357009 A1), hereinafter BEN.
Regarding claim 1, Huang teaches a semiconductor device comprising: a substrate comprising a channel region (706, FIG. 7, 8A); a ferroelectric structure disposed (102) over the channel region, the ferroelectric structure comprising a plurality of two-dimensional material layers of the same material; and a gate electrode layer (402) disposed on the ferroelectric structure.
Huang does not explicitly teach ferroelectric structure comprising a plurality of two-dimensional material layers which is disposed to have a moiré pattern and wherein a thickness of the ferroelectric structure is controlled through the number of stacked two-dimensional material layers.
However, ferroelectric structure comprising a plurality of two-dimensional material layers disposed to have a moiré pattern is disclosed in in BEN in Paragraph [0010]-[0014], [0040]-[0055], FIG. 2B). as stated in Partograph [0098], number of layers in the multilayered material (the diatomic hexagonal multilayered material is selected from hexagonal-boron-nitride (h-BN) as in Paragraph [0102]) is two or three or more. h-BN flakes of various thicknesses (1-5 nm) as stated in Paragraph [0135]. So, the thickness can be controlled using number of hBN layers chosen by people skilled in the art as stated in Paragraph [0098], [0123] and Claim 61. So, the thickness is controlled based on number of stacked hBN selected.
Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use Huang’s semiconductor device to modify with teachings from BEN in order to provide an array of permanent and switchable polarization domains in the crystal. In other words, the magnitude of polarization, as known in the art, of a multilayered stack structure of the invention is thus dependent on the number of layer interfaces present in the structure such that the value of the magnitude may be calculated or determined by determining the magnitude of polarization of a single interface and multiplying said value by the number of interfaces in the structure. In some embodiments, the polarization magnitude of a structure of the invention is the polarization magnitude of a single layer interface multiplied by the number of interfaces in the structure. Depolarization effects in a structure of the invention are minimized to the extent that the linear enhancement of the polarization may be predicted based on a measurable polarization for a single interface (Paragraph [0045].
Regarding claim 2, Huang teaches (in view of BEN) the semiconductor device of claim 1, wherein anyone of the plurality of two-dimensional material layers forms , (Paragraph [0044]-[0054], [0070], [0076], in BEN.) van der Waals bond with another adjacent two-dimensional material layer of the plurality of the two-dimensional material layers so that The structural texture of h-BN is a layered structure, wherein the boron atoms and atoms of nitrogen are bound strongly due to covalent bonds present in-plane and van der Waals forces that hold the layer together.
Regarding claim 3, Huang teaches (in view of BEN) the semiconductor device of claim 1, wherein the ferroelectric structure has ferroelectric polarization generated between the plurality of two-dimensional material layers (Paragraph [0044]-[0054], [0070], [0076] in BEN) in order to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties..
Regarding claim 5, Huang teaches (in view of BEN) the semiconductor device of claim 1, wherein the ferroelectric structure has a superlattice structure comprising the plurality of two-dimensional material layers (Paragraph [0044]-[0054], [0070], [0076], [0089]-[0109] in BEN) in order to provide an array of permanent and switchable polarization domains in the crystal. The process comprising forming or obtaining a diatomic hexagonal multilayered material having a layered stacking configuration, wherein the material layers are stacked in a parallel lattice orientation to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties.
Regarding claim 6, Huang teaches (in view of BEN) the semiconductor device of claim 1, wherein each of the at least two of the two-dimensional material layers includes a lower layer with lower layer lattices and an upper layer with upper layer lattices, the upper layer is disposed on the lower layer, and at least some of the upper layer lattices of the upper layer are twisted at a predetermined angle with respect to the lower layer lattices of the lower layer (Paragraph [0009], [0013], [0079], [0082] in BEN) in order to provide an array of permanent and switchable polarization domains in the crystal. The process comprising forming or obtaining a diatomic hexagonal multilayered material having a layered stacking configuration, wherein the material layers are stacked in a parallel lattice orientation to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties.
Regarding claim 7, Huang teaches (in view of BEN) the semiconductor device of claim 6, wherein the predetermined angle is 0.5° to 1.5° (Paragraph [0079], [0082] in BEN) in order to provide an array of permanent and switchable polarization domains in the crystal. The process comprising forming or obtaining a diatomic hexagonal multilayered material having a layered stacking configuration, wherein the material layers are stacked in a parallel lattice orientation to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties.
Regarding claim 8, Huang teaches (in view of BEN) the semiconductor device of claim 1, wherein each of the plurality of two-dimensional material layers includes a lower layer with lower layer lattices, and an upper layer with upper layer lattices stacked on the lower layer, and at least some of the upper layer lattices of the upper layer are alternately disposed with the lower layer lattices of the lower layer in a lateral direction substantially parallel to a plane formed by the lower layer (Paragraph [0003]-[0006], [0011]-[0025], [0085]-[0093], [0154] FIG. 1A-1D, 7A, 7B, Claim 51 in BEN) in order to provide an array of permanent and switchable polarization domains in the crystal. The process comprising forming or obtaining a diatomic hexagonal multilayered material having a layered stacking configuration, wherein the material layers are stacked in a parallel lattice orientation to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties.
Regarding claim 9, Huang teaches (in view of BEN) the semiconductor device of claim 8, wherein at least some of the upper layer lattices are arranged by sliding in the lateral direction with respect to the corresponding lower layer lattices (Paragraph [0003]-[0006], [0011]-[0025], [0085]-[0093], [0154] FIG. 1A-1D, 7A, 7B, Claim 51 in BEN) in order to provide an array of permanent and switchable polarization domains in the crystal. The process comprising forming or obtaining a diatomic hexagonal multilayered material having a layered stacking configuration, wherein the material layers are stacked in a parallel lattice orientation to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties.
Regarding claim 10, Huang teaches (in view of BEN) the semiconductor device of claim 1, wherein the ferroelectric structure implements a negative capacitance (FIG. 6A-6D, Paragraph [0010]-[0012] in BEN) in order to provide an array of permanent and switchable polarization domains in the crystal. The process comprising forming or obtaining a diatomic hexagonal multilayered material having a layered stacking configuration, wherein the material layers are stacked in a parallel lattice orientation to exhibit internal interfacial electric field normal to the layer plane of the crystal and applying electric field to said layered material to induce room temperature stable ferroelectric properties. The ferroelectric materials having polarization states that can be selected or switched by application of an electric field, and these polarization states remain after the electric field is removed can be used as capacitors possibility for simple, low cost, high density, non-volatile memories.
Regarding claim 11, Huang teaches the semiconductor device of claim 1, further comprising a base dielectric layer that is disposed between the channel region and the ferroelectric structure and that has non-ferroelectric properties (304, FIG. 3B)
Regarding claim 12, Huang teaches the semiconductor device of claim 1, further comprising a source region and a drain region disposed at opposite sides of the channel region (FIG.7, 704/704 is the source drain region, 706 is the channel region).
Conclusion
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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