DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/13/2026 has been entered.
Response to Amendment
The Amendment filed on 07/13/2026 has been entered. Claims 1-3, 5-13 and 15-20 remain pending in the application. Claims 4 and 14 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro et al., (United States Patent Application Publication Number, US 2021/0296427 A1) hereinafter referenced as Ishiguro, in view of Menath et al., (United States Patent Number, US 2013/0277797 A1) hereinafter referenced as Menath.
Regarding claim 1, Ishiguro teaches a semiconductor device comprising: a first chip (Fig.22, left side chip corresponds to the chip in Fig.20) including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip (Fig.22, elements #11-1 and #12-1, separated by insulator #21-1, numbered in Fig.20).
Ishiguro does not teach wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Menath teaches wherein a width of the first coil (Fig.1a, wire width of element #140) is greater than a width of the second coil (Fig.1a, wire of element #130 is circular, see also Fig.2i, and therefore a wire width of element #130 at the bottom of the wire smaller than the wire width of element #140 exists), a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, the horizontal spacing between wires of element #140 is less than the horizontal spacing between wires of element #130 which corresponds to the same height as the width of the second coil) and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (Fig.1a and 1b, the wires of the two coils are aligned, paragraph [0006], rows 4-6, therefore they have the same pitch equal to each of the two sums). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Menath and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. As disclosed by Menath, making the wires of the second coil circular, which results in the claimed relation between the width and spacing of the wires of the two coils, reduces excessive electrical fields, which decrease the strength of the device (paragraph [0024], [0026]).
Ishiguro further teaches a second chip (Fig.22, left side chip corresponds to the chip in Fig.21) including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip (Fig.22, elements #11-2 and #12-2, separated by insulator #21-2, numbered in Fig.21).
Ishiguro does not teach wherein a width of the third coil is greater than a width of the fourth coil, a spacing between wires of the third coil is less than a spacing between wires of the fourth coil, and a sum of the width of the third coil and spacing between wires of the third coil is same as a sum of the width of the fourth coil and spacing between wires of the fourth coil. Menath teaches wherein a width of the first coil (Fig.1a, wire width of element #140) is greater than a width of the second coil (Fig.1a, wire of element #130 is circular, see also Fig.2i, and therefore a wire width of element #130 at the bottom of the wire smaller than the wire width of element #140 exists), a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, the horizontal spacing between wires of element #140 is less than the horizontal spacing between wires of element #130 which corresponds to the same height as the width of the second coil) and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (Fig.1a and 1b, the wires of the two coils are aligned, paragraph [0006], rows 4-6, therefore they have the same pitch equal to each of the two sums). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Menath and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. As disclosed by Menath, making the wires of the second coil circular, which results in the claimed relation between the width and spacing of the wires of the two coils, reduces excessive electrical fields, which decrease the strength of the device (paragraph [0024], [0026]).
Ishiguro further teaches a first bonding wire that connects a first pad at a center of the second coil to a second pad at a center of the fourth coil (Fig.19, element #63); and a second bonding wire that connects a third pad at a terminal of the second coil to a fourth pad a terminal of the fourth coil (Fig.19, element #65).
Regarding claim 2, the combination of Ishiguro and Menath teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 1, wherein: the first coil is fabricated on a bottom layer of the first insulator; the second coil is fabricated on a top layer of the first insulator using top metal layer process (Fig.20, element #11-1 is fabricated on bottom insulator layer, element #20a, elements #12-1 is fabricated on top insulator layer, element #22-1, top metal layer, element #12); the third coil is fabricated on a bottom layer of the second insulator; and the fourth coil is fabricated on a top layer of the second insulator using top metal layer process (Fig.21, element #11-2 is fabricated on bottom insulator layer, element #20b, elements #12-2 is fabricated on top insulator layer, element #22-2, top metal layer, element #12).
Regarding claim 5, the combination of Ishiguro and Menath teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 1, wherein the first chip and the second chip form a transformer that implements an isolator (Fig.22, paragraph [0139] and [121]).
Regarding claim 10, Ishiguro teaches a semiconductor device comprising: a transmitter configured to output a transmission signal (Fig.22, element #1, paragraph [0044], rows 1-5); a receiver (Fig.22, element #2, paragraph [0044], rows 1-5) and an isolator (Fig.22, element #310) including a first chip (Fig.22, left side chip corresponds to the chip in Fig.20) including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip (Fig.22, elements #11-1 and #12-1, separated by insulator #21-1, numbered in Fig.20).
Ishiguro does not teach wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Menath teaches wherein a width of the first coil (Fig.1a, wire width of element #140) is greater than a width of the second coil (Fig.1a, wire of element #130 is circular, see also Fig.2i, and therefore a wire width of element #130 at the bottom of the wire smaller than the wire width of element #140 exists), a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, the horizontal spacing between wires of element #140 is less than the horizontal spacing between wires of element #130 which corresponds to the same height as the width of the second coil) and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (Fig.1a and 1b, the wires of the two coils are aligned, paragraph [0006], rows 4-6, therefore they have the same pitch equal to each of the two sums). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Menath and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. As disclosed by Menath, making the wires of the second coil circular, which results in the claimed relation between the width and spacing of the wires of the two coils, reduces excessive electrical fields, which decrease the strength of the device (paragraph [0024], [0026]).
Ishiguro further teaches a second chip (Fig.22, left side chip corresponds to the chip in Fig.21) including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip (Fig.22, elements #11-2 and #12-2, separated by insulator #21-2, numbered in Fig.21).
Ishiguro does not teach wherein a width of the third coil is greater than a width of the fourth coil, a spacing between wires of the third coil is less than a spacing between wires of the fourth coil, and a sum of the width of the third coil and spacing between wires of the third coil is same as a sum of the width of the fourth coil and spacing between wires of the fourth coil. Menath teaches wherein a width of the first coil (Fig.1a, wire width of element #140) is greater than a width of the second coil (Fig.1a, wire of element #130 is circular, see also Fig.2i, and therefore a wire width of element #130 at the bottom of the wire smaller than the wire width of element #140 exists), a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, the horizontal spacing between wires of element #140 is less than the horizontal spacing between wires of element #130 which corresponds to the same height as the width of the second coil) and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (Fig.1a and 1b, the wires of the two coils are aligned, paragraph [0006], rows 4-6, therefore they have the same pitch equal to each of the two sums). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Menath and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. As disclosed by Menath, making the wires of the second coil circular, which results in the claimed relation between the width and spacing of the wires of the two coils, reduces excessive electrical fields, which decrease the strength of the device (paragraph [0024], [0026]).
Ishiguro further teaches a first bonding wire that connects a first pad at a center of the second coil to a second pad at a center of the fourth coil (Fig.19, element #63); and a second bonding wire that connects a third pad at a terminal of the second coil to a fourth pad a terminal of the fourth coil (Fig.19, element #65).
Ishiguro further teaches wherein the isolator is configured to: receive the transmission signal from the transmitter; and output the transmission signal to the receiver (Fig.22, the coils of the isolator are connected to the transmitter, element #1 and the receiver, element #2, and therefore is configured to receive and transmit signals).
Regarding claim 12, the combination of Ishiguro and Menath teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 10, wherein: the first coil is fabricated on a bottom layer of the first insulator; the second coil is fabricated on a top layer of the first insulator using top metal layer process (Fig.20, element #11-1 is fabricated on bottom insulator layer, element #20a, element #12-1 is fabricated on top insulator layer, element #22-1, top metal layer, element #12); the third coil is fabricated on a bottom layer of the second insulator; and the fourth coil is fabricated on a top layer of the second insulator using top metal layer process (Fig.21, element #11-2 is fabricated on bottom insulator layer, element #20b, elements #12-2 is fabricated on top insulator layer, element #22-2, top metal layer, element #12).
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro in view of Menath and in view of Richardson, (United States Patent Application Publication Number, US 2018/0233264 A1) hereinafter referenced as Richardson.
Regarding claim 3, the combination of Ishiguro and Menath teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 1, wherein: each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape (paragraph [0034], rows 1-4, and Fig.19); and the first coil, the second coil, the third coil, and the fourth coil have a same coil turn number (Fig.19, 20 and 21 show the same turn number) and, the second coil, the third coil, have a same winding direction (Fig.19). The combination of Ishiguro and Menath does not teach wherein the first coil, the second coil, the third coil, and the fourth coil have a same diameter, and a same winding direction.
Richardson teaches wherein: each one of the first coil (Fig.1A, first coil formed by elements #106 and #108), the second coil (Fig.1A, second coil formed by elements #102 and #104), has a spiral shape (Fig.2A, both have a spiral shape) and the first coil and the second coil have a same diameter, a same coil turn number, and a same winding direction (Fig.1A, both have the same diameter, coil turn number and winding direction). Since Ishiguro teaches the first and the second chip have the same configuration (paragraph [0133] and [0135]), the combination of Ishiguro and Richardson also teaches each one of the third coil and the fourth coil has a spiral shape, and the third coil and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Richardson and disclose each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; and the first coil, the second coil, the third coil, and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. Using coils with the same number of turns, same winding and diameter results in the coils having the same self-inductance, which increases the coupling coefficient. Furthermore, using identical components in a circuit simplifies the design process and helps reduce costs.
Regarding claim 13, the combination of Ishiguro and Menath teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 10, wherein: each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape (paragraph [0034], rows 1-4, and Fig.19); and the first coil, the second coil, the third coil, and the fourth coil have a same coil turn number (Fig.19, 20 and 21 show the same turn number) and, the second coil, the third coil, have a same winding direction (Fig.19). The combination of Ishiguro and Menath does not teach wherein the first coil, the second coil, the third coil, and the fourth coil have a same diameter, and a same winding direction.
Richardson teaches wherein: each one of the first coil (Fig.1A, first coil formed by elements #106 and #108), the second coil (Fig.1A, second coil formed by elements #102 and #104), has a spiral shape (Fig.2A, both have a spiral shape) and the first coil and the second coil have a same diameter, a same coil turn number, and a same winding direction (Fig.1A, both have the same diameter, coil turn number and winding direction). Since Ishiguro teaches the first and the second chip have the same configuration (paragraph [0133] and [0135]), the combination of Ishiguro and Richardson also teaches each one of the third coil and the fourth coil has a spiral shape, and the third coil and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Richardson and disclose each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; and the first coil, the second coil, the third coil, and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. Using coils with the same number of turns, same winding and diameter results in the coils having the same self-inductance, which increases the coupling coefficient. Furthermore, using identical components in a circuit simplifies the design process and helps reduce costs.
Claim 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro in view of Menath and in view of Lee et al., (United States Patent Number, US 7,470,927 B2) hereinafter referenced as Lee.
Regarding claim 6, the combination of Ishiguro and Menath teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Ishiguro and Menath does not teach the semiconductor of claim 1, wherein: a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Lee teaches wherein a thickness of the second coil is greater than a thickness of the first coil (Fig.1a, a thickness t1 of the first coil is in the range 0.3 microns to 5 microns, column 7, rows 19-20 and a thickness of the second coil, t2 is in the range 3 microns to 10 microns, column 8, rows 36-38, also second coil is made in a thick metal layer). Ishiguro teaches the first and the second chip have the same configuration (paragraph [0133] and [0135]), and therefore, the combination of Ishiguro and Lee also teaches a thickness of the fourth coil is greater than a thickness of the third coil. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Making the second and fourth coils thicker than the first and third coils results in a lower electrical resistance which allows higher current to flow through the coils and transferring more power.
Regarding claim 15, the combination of Ishiguro and Menath teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. The combination of Ishiguro and Menath does not teach the semiconductor of claim 10, wherein: a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Lee teaches wherein a thickness of the second coil is greater than a thickness of the first coil (Fig.1a, a thickness t1 of the first coil is in the range 0.3 microns to 5 microns, column 7, rows 19-20 and a thickness of the second coil, t2 is in the range 3 microns to 10 microns, column 8, rows 36-38, also second coil is made in a thick metal layer). Ishiguro teaches the first and the second chip have the same configuration (paragraph [0133] and [0135]), and therefore, the combination of Ishiguro and Lee also teaches a thickness of the fourth coil is greater than a thickness of the third coil. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Making the second and fourth coils thicker than the first and third coils results in a lower electrical resistance which allows higher current to flow through the coils transferring more power.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro in view of Menath, in view of Fouquet et al., (United States Patent Application Publication Number, US 2008/0179963 A1) hereinafter referenced as Fouquet, in view of Mizuide, (United States Patent Number, US 4,806,791) hereinafter referenced as Mizuide.
Regarding claim 7, the combination of Ishiguro and Menath teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Ishiguro and Menath does not teach the semiconductor device of claim 1, wherein an output terminal of the third coil is connected to a differential comparator. Fouquet teaches wherein the output terminal of a bottom coil is connected to a differential comparator (paragraph [0015], rows 5-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fouquet and disclose wherein an output terminal of the third coil is connected to a differential comparator. As disclosed by Fouquet, the differential comparator can be configured to sense changes from both positive to negative output pulses (paragraph [0015], rows 11-17).
The combination of Ishiguro, Menath and Fouquet does not disclose the differential comparator is an NPN comparator. Mizuide teaches a differential comparator is an NPN comparator. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mizuide and disclose the differential comparator is an NPN comparator. As disclosed by Mizuide, an NPN differential comparator can be responsive to high input difference voltage without degrading hysteresis characteristics (column 1, rows 26-30).
Regarding claim 16, the combination of Ishiguro and Menath teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. The combination of Ishiguro and Menath does not teach the semiconductor device of claim 10, wherein an output terminal of the third coil is connected to a differential comparator. Fouquet teaches wherein the output terminal of a bottom coil is connected to a differential comparator (paragraph [0015], rows 5-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fouquet and disclose wherein an output terminal of the third coil is connected to a differential comparator. As disclosed by Fouquet, the differential comparator can be configured to sense changes from both positive to negative output pulses (paragraph [0015], rows 11-17).
The combination of Ishiguro, Menath and Fouquet does not disclose the differential comparator is an NPN comparator. Mizuide teaches a differential comparator is an NPN comparator. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mizuide and disclose the differential comparator is an NPN comparator. As disclosed by Mizuide, an NPN differential comparator can be responsive to high input difference voltage without degrading hysteresis characteristics (column 1, rows 26-30).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ishiguro in view of Menath and in view of Sugahara (United States Patent Number, US 9899146 B2) hereinafter referenced as Sugahara.
Regarding claim 11, the combination of Ishiguro and Menath teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Ishiguro teaches a transmitter and a receiver circuit (paragraph [0044]). The combination of Ishiguro and Menath does not teach the semiconductor device of claim 10, wherein the transmitter is a controller of a voltage regulator, and the receiver is a driver of the voltage regulator. Sugahara teaches a voltage regulator (Fig.11, and abstract, rows 1-4) where the isolator (Fig.11 caption, signal transfer device uses an insulator transformer) receives a signal from transmitter that controls the isolator (Fig.11, logical circuit) and outputs a signal to a driver of a voltage regulator (Fig.11 driver H). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sugahara and disclose wherein the transmitter is a controller of a voltage regulator and the receiver is a driver of the voltage regulator. Using the semiconductor device disclosed by Ishiguro and Menath in the regulator circuit disclosed by Sugahara provides an improved withstand voltage of the output transistors of the regulator.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sugahara, in view of Ishiguro and Menath.
Regarding claim 18, Sugahara teaches a voltage regulator comprising: a controller configured to output a transmission signal (Fig.11, logical circuit) a power stage including a driver configured to drive a transistor (Fig.11, driver H) and an isolator (Fig.11 caption, signal transfer device uses an insulator). Sugahara does not teach the isolator including: a first chip including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip; a second chip including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip; and at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip. Ishiguro teaches a semiconductor device comprising: a first chip (Fig.22, left side chip corresponds to the chip in Fig.20) including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip (Fig.22, elements #11-1 and #12-1, separated by insulator #21-1, numbered in Fig.20) and a second chip (Fig.22, left side chip corresponds to the chip in Fig.21) including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip (Fig.22, elements #11-2 and #12-2, separated by insulator #21-2, numbered in Fig.21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ishiguro and disclose an isolator including: a first chip including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip; a second chip including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip; and at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip. Using the isolator disclosed by Ishiguro in the regulator circuit disclosed by Sugahara allows the integration of the isolator with other circuits on the same chips (like circuits 1 and 2 of Fig.22) which offers reduced cost and manufacturing efficiency.
The combination of Sugahara and Ishiguro does not teach wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Menath teaches wherein a width of the first coil (Fig.1a, wire width of element #140) is greater than a width of the second coil (Fig.1a, wire of element #130 is circular, see also Fig.2i, and therefore a wire width of element #130 at the bottom of the wire smaller than the wire width of element #140 exists), a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, the horizontal spacing between wires of element #140 is less than the horizontal spacing between wires of element #130 which corresponds to the same height as the width of the second coil) and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (Fig.1a and 1b, the wires of the two coils are aligned, paragraph [0006], rows 4-6, therefore they have the same pitch equal to each of the two sums). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Menath and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. As disclosed by Menath, making the wires of the second coil circular, which results in the claimed relation between the width and spacing of the wires of the two coils, reduces excessive electrical fields, which decrease the strength of the device (paragraph [0024], [0026]).
Since Ishiguro teaches both chips having the same configuration (paragraph [0133] and [0135]) and Menath teaches the claimed differences in the width of the coils and spacing between wires of the coils, the combination of Ishiguro and Menath also teaches a width of the third coil is greater than a width of the fourth coil, a spacing between wires of the third coil is less than a spacing between wires of the fourth coil, and a sum of the width of the third coil and spacing between wires of the third coil is same as a sum of the width of the fourth coil and spacing between wires of the fourth coil.
Ishiguro further teaches a first bonding wire that connects a first pad at a center of the second coil to a second pad at a center of the fourth coil (Fig.19, element #63); and a second bonding wire that connects a third pad at a terminal of the second coil to a fourth pad a terminal of the fourth coil (Fig.19, element #65). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ishiguro and disclose a first bonding wire that connects a first pad at a center of the second coil to a second pad at a center of the fourth coil (Fig.19, element #63); and a second bonding wire that connects a third pad at a terminal of the second coil to a fourth pad a terminal of the fourth coil. As disclosed by Ishiguro, this allows one to isolate the circuits of the device from each other with improved reliability as compared with a structure with a single pair of coils (paragraph [0139], rows 11-16).
Sugahara further teaches wherein the isolator is configured to: receive the transmission signal from the controller (Fig.11, the signal transfer device which comprises the insulator receives a signal from the logical circuit) and output the transmission signal to the driver (Fig.11, the signal transfer device which comprises the insulator outputs the signal to driver H).
Regarding claim 19, the combination of Sugahara, Ishiguro and Menath teaches the semiconductor device of claim 18 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 1, wherein: the first coil is fabricated on a bottom layer of the first insulator; the second coil is fabricated on a top layer of the first insulator using top metal layer process (Fig.20, element #11-1 is fabricated on bottom insulator layer, element #20a, elements #12-1 is fabricated on top insulator layer, element #22-1, top metal layer, element #12); the third coil is fabricated on a bottom layer of the second insulator; and the fourth coil is fabricated on a top layer of the second insulator using top metal layer process (Fig.21, element #11-2 is fabricated on bottom insulator layer, element #20b, elements #12-2 is fabricated on top insulator layer, element #22-2, top metal layer, element #12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ishiguro and disclose the first coil is fabricated on a bottom layer of the first insulator; the second coil is fabricated on a top layer of the first insulator using top metal layer process; the third coil is fabricated on a bottom layer of the second insulator; and the fourth coil is fabricated on a top layer of the second insulator using top metal layer process. Fabricating the coils on bottom and top layers of insulators of semiconductor chips is compatible with semiconductor fabrication processes and, as disclosed by Ishiguro, allows integration of the coils with other circuits on the same chip, which reduces manufacturing costs.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sugahara in view of Ishiguro, Menath and in view of Richardson and Lee.
Regarding claim 20, the combination of Sugahara, Ishiguro and Menath teaches the voltage regulator of claim 18 as set forth in the obviousness rejection. Ishiguro further teaches the semiconductor device of claim 1, wherein: each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape (paragraph [0034], rows 1-4, and Fig.19); and the first coil, the second coil, the third coil, and the fourth coil have a same coil turn number (Fig.19, 20 and 21 show the same turn number) and, the second coil, the third coil, have a same winding direction (Fig.19). Richardson also teaches wherein: each one of the first coil (Fig.1A, first coil formed by elements #106 and #108), the second coil (Fig.1A, second coil formed by elements #102 and #104), has a spiral shape (Fig.2A, both have a spiral shape) and the first coil and the second coil have a same diameter, a same coil turn number, and a same winding direction (Fig.1A, both have the same diameter, coil turn number and winding direction). Since Ishiguro teaches the first and the second chip have the same configuration (paragraph [0133] and [0135]), the combination of Ishiguro and Richardson also teaches each one of the third coil and the fourth coil has a spiral shape, and the third coil and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ishiguro and Richardson and disclose each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; and the first coil, the second coil, the third coil, and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. The spiral shape allows for a compact footprint and a more uniform magnetic field as compared to other shapes. Using coils with the same number of turns, same winding and diameter results in the coils having the same self-inductance, which increases the coupling coefficient. Furthermore, using identical components in a circuit simplifies the design process and helps reduce costs.
The combination of Sugahara, Ishiguro, Menath and Richardson does not teach a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Lee teaches wherein a thickness of the second coil is greater than a thickness of the first coil (Fig.1a, a thickness t1 of the first coil is in the range 0.3 microns to 5 microns, column 7, rows 19-20 and a thickness of the second coil, t2 is in the range 3 microns to 10 microns, column 8, rows 36-38, also second coil is made in a thick metal layer). Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), and therefore, the combination of Osada and Lee also teaches a thickness of the fourth coil is greater than a thickness of the third coil. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Making the second and fourth coils thicker than the first and third coils results in a lower electrical resistance which allows higher current to flow through the coils transferring more power.
Allowable Subject Matter
Claim 8 and 17 are allowed if written in independent form. Claim 9 is allowed as being dependent on claim 8, if claim 8 is written in independent form.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claims 8 and 17 the cited prior art does not teach or fairly suggests, along with other claimed features: “further comprising a third chip, wherein: the second chip includes a fifth coil and a sixth coil magnetically coupled in a vertical alignment and isolated by the second insulator in the second chip; the third coil is electrically connected to the fifth coil; the third chip includes a seventh coil and an eighth coil magnetically coupled in a vertical alignment and isolated by a third insulator in the third chip; and a bonding wire connects the sixth coil in the second chip to the eighth coil in the third chip”.
Osada, (Worldwide Application Publication Number, JPWO-2022168675 A1, JaUS version US 20230361773 A1 is used) teaches wherein: the isolator further includes a third chip (Fig.9, element #80A); the second chip (Fig.9, element #80C) includes a fifth coil and a sixth coil magnetically coupled in a vertical alignment and isolated by the second insulator in the second chip (Fig.4, each chip contains multiple coils pairs aligned in vertical direction, coils A and B; Fig.10, the fifth coil is top coil element #49A, sixth coil is bottom coil element #48A, the third coil is bottom coil element #48B, and fourth coil is top coil element #49B, where coils B are not shown, the chips have the same configuration and therefore a second insulator similar to the first insulator exists); the second coil (Fig.10, first chip is element #80B, second coil is top coil element #45B, not shown but equivalent to top coil element #45A) is electrically connected to the fourth coil (Fig.10, top coil elements #45B and #49B are connected through wire equivalent to element #15A, see Fig.9 for top view); the third coil is electrically connected to the fifth coil (both coils are in the same chip separated by dielectric layers, therefore capacitive coupling exists); the third chip includes a seventh coil and an eighth coil magnetically coupled in a vertical alignment (Fig.10, seventh coil is element #43A and eighth coil is element #44A and isolated by a third insulator in the third chip; and a bonding wire connects the sixth coil in the second chip to the eighth coil in the third chip (Fig.10, wire element #13A connects element #48A to element #44A). However, the electrical connections between the coils as disclosed by Osada are not compatible with the electrical connections of the coils as disclosed by the other references, and the inventions disclosed by other references do not require a third chip.
Response to Arguments
Applicant’s arguments filed on 07/13/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
