DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/28/2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments have overcome each and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 10/16/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/28/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 6, 8, 9, 10, 12, 14, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Osada (Worldwide Application Publication Number, JPWO-2022168675 A1, Japanese application translation was used), hereinafter referenced as Osada, in view of Lee et al., (United States Patent Number, US 7,470,927 B2) hereinafter referenced as Lee.
Regarding claim 1, Osada teaches a semiconductor device comprising: a first chip (Fig.3, element #80A) including at least a first coil (Fig.3, element #43A) and a second coil (Fig.3, element #44A) magnetically coupled in a vertical alignment (Fig.3, paragraph [0030], rows 1-3) and isolated by a first insulator in the first chip Fig.5, portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between). Osada does not teach wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Lee teaches wherein a width of the first coil is greater than a width of the second coil (Fig.1a, a width w1 of the first coil, element #200, is in the range 1um to 20um, column 7 rows 20-23, and a width w2 of the second coil, element #300, is in the range 2um to 20um, column 8 rows 38-40) a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, a spacing s1 of the first coil, element #200, is in the range 1um to 20um, column 7 rows 23-25, and a spacing s2 of the second coil, element #300, is in the range 2um to 20um, column 8 rows 40-43), and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (based on the ranges above the sum of w1 and s1 can be the same as the sum of w2 and s2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Wider wires increase current capacity and reduce voltage drop across the coil, while smaller spacing can lead to increase leakage inductance. Furthermore, since the coils are manufactured using different metal levels and possibly different metals, they required different metal filling factors to ensure uniform layer densities during the manufacturing process. Considering the above, and since the two coils have to be designed to handle different voltages and loads, each coil can be independently optimized by adjusting the wires width and spacing, while maintaining the same planar size for both to reduce the device footprint. Also, having the sum of the width of the first coil and spacing between wires of the first coil the same as a sum of the width of the second coil and spacing between wires of the second coil, results in the possibility of using the same number of turns for both, which simplifies the design process and results in increase efficiency.
Osada further teaches a second chip (Fig.3, element #80B) including at least a third coil (Fig.3, element #46A) and a fourth coil (Fig.3, element #45A) magnetically coupled in a vertical alignment (Fig.3, paragraph [0030], rows 3-5) and isolated by a second insulator in the second chip (both chips have the same configuration, paragraph [0094], rows 1-2, therefore a second insulator similar to the first insulator exists). Since Osada teaches both chips having the same configuration (paragraph [0094], rows 1-2) and Lee teaches the claimed differences in the width of the coils and spacing between wires of the coils, the combination of Osada and Lee teaches
wherein a width of the third coil is greater than a width of the fourth coil, a spacing between wires of the third coil is less than a spacing between wires of the fourth coil, and a sum of the width of the third coil and spacing between wires of the third coil is same as a sum of the width of the fourth coil and spacing between wires of the fourth coil.
Osada further teaches at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip (Fig.3, wire element #11A connects second coil, element #44A, with the fourth coil, element #45A).
Regarding claim 2, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 1, wherein: the first coil (Fig.3, element #43A) is fabricated on a bottom layer of the first insulator (element #43A is located on the bottom layer of the first insulator, where the first insulator is the portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); the second coil (Fig.3, element #44A) is fabricated on a top layer of the first insulator (element #44A is located on the top layer of the first insulator, where the first insulator is the portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); using top metal layer process (Fig.5, the coils are fabricated on metal layers on top of substrate, element #84); the third coil is fabricated on a bottom layer of the second insulator; and the fourth coil is fabricated on a top layer of the second insulator using top metal layer process (second chip has same configuration as the first chip, paragraph [0094], rows 1-2).
Regarding claim 4, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 1, wherein: the second coil includes a first pad at a center of the second coil (Fig.5, element #44A includes pad element #82A at a center in the horizontal direction); the second coil includes a second pad at a terminal of the second coil (paragraph [0093], rows 1-5); the fourth coil includes a third pad at a center of the fourth coil (Fig.3, element #45A includes pad element #81B at a center in the horizontal direction); the fourth coil includes a fourth pad at a terminal of the fourth coil (paragraph [0093], rows 1-5); the at least one bonding wire include a first bonding wire that connects the first pad to the third pad (Fig.1, wire element #11A connects first and fourth pads, paragraph [0093], rows 1-5); and the at least one bonding wire include a second bonding wire that connects the second pad to the fourth pad (Fig.1, wire element #12A connects the second and fourth pad, paragraph [0093], rows 1-5).
Regarding claim 5, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 1, the semiconductor device of claim 1, wherein the first chip and the second chip form a transformer that implements an isolator (Fig.3, the two chips #80A and #80B form a transformer that implements an isolator, and transport a signal from low voltage circuit, element #20 to high voltage circuit, element #30).
Regarding claim 6, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Osada does not teach the semiconductor of claim 1, wherein: a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Lee teaches wherein a thickness of the second coil is greater than a thickness of the first coil (Fig.1a, a thickness t1 of the first coil is in the range 0.3 microns to 5 microns, column 7, rows 19-20 and a thickness of the second coil, t2 is in the range 3 microns to 10 microns, column 8, rows 36-38, also second coil is made in a thick metal layer). Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), and therefore, the combination of Osada and Lee also teaches a thickness of the fourth coil is greater than a thickness of the third coil. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Making the second and fourth coils thicker that the first and third coils results in a lower electrical resistance which allows for higher current to flow through the coils and therefore transfer more power.
Regarding claim 8, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 1, further comprising a third chip (Fig.9, third chip is element #80B; note that element #80C in Fig.9 is equivalent to element #80B in Fig.3), wherein: the second chip (Fig.9, element #80C) includes a fifth coil and a sixth coil magnetically coupled in a vertical alignment and isolated by the second insulator in the second chip (Fig.4, each chip contains multiple coils pairs aligned in vertical direction, labeled A and B; Fig.10, the fifth coil is element #48A, sixth coil is element #49A, the third coil is element #48B and fourth coil is element #49B, where B labeled coils are not shown, the chips have the same configuration and therefore a second insulator similar to the first insulator exists); the third coil is electrically connected to the fifth coil (both coils are in the same chip separated by dielectric layers therefore capacitive coupling exists); the third chip includes a seventh coil and an eighth coil magnetically coupled in a vertical alignment (Fig.10, seventh coil is element #46A and eighth coil is element #45A) and isolated by a third insulator in the third chip (chips have the same configuration, paragraph [0151], rows 1-2) therefore, a third insulator similar to the first and second insulators exists); and a bonding wire connects the sixth coil in the second chip to the eighth coil in the third chip (Fig.10, wire element #15A connects the sixth coil, element #49A, with the eight coil, element #45A).
Regarding claim 9, the combination of Osada and Lee teaches the semiconductor device of claims 1 and 8 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 8, wherein the first chip, the second chip, and the third chip form a transformer that implements an isolator (Fig.10, the three chips, elements #80A, #80B and #80C form a transformer that implements an isolator, and transport a signal from low voltage circuit, element #20 to high voltage circuit, element #30).
Regarding claim 10, Osada teaches a semiconductor device comprising: a transmitter configured to output a transmission signal (Fig.3, element #20, paragraph [0018], row 4-5); a receiver (Fig.3, element #30, paragraph [0018], rows 1-4); and an isolator (formed by elements #80A and #80B) including: a first chip (Fig.3, element #80A) including at least a first coil (Fig.3, element #43A) and a second coil (Fig.3, element #44A) magnetically coupled in a vertical alignment (Fig.3, paragraph [0030], rows 1-3) and isolated by a first insulator in the first chip (Fig.5, portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between).
Osada does not teach wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Lee teaches wherein a width of the first coil is greater than a width of the second coil (Fig.1a, a width w1 of the first coil, element #200, is in the range 1 to 20um, column 7 rows 20-23, and a width w2 of the second coil, element #300, is in the range 2 to 20um, column 8 rows 38-40) a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, a spacing s1 of the first coil, element #200, is in the range 1 to 20um, column 7 rows 23-25, and a spacing s2 of the second coil, element #300, is in the range 2 to 20um, column 8 rows 40-43), and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (based on the ranges above the sum of w1 and s1 can be the same as the sum of w2 and s2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Wider wires increase current capacity and reduce voltage drop across the coil, while smaller spacing can lead to increase leakage inductance. Furthermore, since the coils are manufactured using different metal levels and possibly different metals, they required different metal filling factors to ensure uniform layer density during the manufacturing process. Considering the above, and since the two coils have to be designed to handle different voltages and loads, each one can be independently optimized by adjusting the wires width and spacing, while maintaining the same planar size for both to reduce the device footprint. Also, having the sum of the width of the first coil and spacing between wires of the first coil the same as a sum of the width of the second coil and spacing between wires of the second coil, results in the possibility of using the same number of turns for both, which simplifies the design process and results in increase efficiency.
Osada further teaches a second chip (Fig.3, element #80B) including at least a third coil (Fig.3, element #46A) and a fourth coil (Fig.3, element #45A) magnetically coupled in a vertical alignment (Fig.3, paragraph [0030], rows 3-5) and isolated by a second insulator in the second chip (both chips have the same configuration, paragraph [0094], rows 1-2, therefore a second insulator similar to the first insulator exists). Since Osada teaches both chips having the same configuration (paragraph [0094], rows 1-2) and Lee teaches the claimed differences in the width of the coils and spacing between wires of the coils, the combination of Osada and Lee teaches
wherein a width of the third coil is greater than a width of the fourth coil, a spacing between wires of the third coil is less than a spacing between wires of the fourth coil, and a sum of the width of the third coil and spacing between wires of the third coil is same as a sum of the width of the fourth coil and spacing between wires of the fourth coil.
Osada further teaches at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip (Fig.3, wire element #11A connects second coil, element #44A, with the fourth coil, element #45A); wherein the isolator is configured to: receive the transmission signal from the transmitter (Fig.3, first chip, element #80A receive a signal from transmitter, element #20); and output the transmission signal to the receiver (Fig.3, and second chip, element #80B outputs a transmission signal to the receiver, element #30).
Regarding claim 12, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 10, wherein: the first coil (Fig.3, element #43A) is fabricated on a bottom layer of the first insulator (element #43A is located on the bottom layer of the first insulator, where the first insulator is the portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); the second coil (Fig.3, element #44A) is fabricated on a top layer of the first insulator (element #44A is located on the top layer of the first insulator, where the first insulator is the portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); using top metal layer process (Fig.5, the coils are fabricated on metal layers on top of substrate, element #84); the third coil is fabricated on a bottom layer of the second insulator; and the fourth coil is fabricated on a top layer of the second insulator using top metal layer process(second chip has same configuration as the first chip, paragraph [0094], rows 1-2).
Regarding claim 14, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 10, wherein: the second coil includes a first pad at a center of the second coil (Fig.5, element #44A includes pad element #82A at a center in the horizontal direction); the second coil includes a second pad at a terminal of the second coil (paragraph [0093], rows 1-5); the fourth coil includes a third pad at a center of the fourth coil (Fig.3, element #45A includes pad element #81B at a center in the horizontal direction); the fourth coil includes a fourth pad at a terminal of the fourth coil (paragraph [0093], rows 1-5); the at least one bonding wire include a first bonding wire that connects the first pad to the third pad (Fig.1, wire element #11A connects first and fourth pads, paragraph [0093], rows 1-5); and the at least one bonding wire include a second bonding wire that connects the second pad to the fourth pad (Fig.1, wire element #12A connects the second and fourth pad, paragraph [0093], rows 1-5).
Regarding claim 15, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the anticipation rejection. Osada does not teach the semiconductor of claim 10, wherein: a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. . Lee teaches wherein a thickness of the second coil is greater than a thickness of the first coil (Fig.1a, a thickness t1 of the first coil is in the range 0.3 microns to 5 microns, column 7, rows 19-20 and a thickness of the second coil, t2 is in the range 3 microns to 10 microns, column 8, rows 36-38, also second coil is made in a thick metal layer). Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), and therefore, the combination of Osada and Lee also teaches a thickness of the fourth coil is greater than a thickness of the third coil. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Making the second and fourth coils thicker that the first and third coils results in a lower electrical resistance which allows for higher current to flow through the coils and therefore transfer more power.
Regarding claim 17, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Osada further teaches the semiconductor device of claim 10, wherein: the isolator further includes a third chip (Fig.9, third chip is element #80A; note that element #80B in Fig.9 is equivalent to first chip element #80A in Fig.3); the second chip (Fig.9, second chip is element #80C, note that element #80C in Fig.9 is equivalent to second chip element #80B in Fig.3) includes a fifth coil and a sixth coil magnetically coupled in a vertical alignment and isolated by the second insulator in the second chip (Fig.4, each chip contains multiple coils pairs aligned in vertical direction, coils A and B; Fig.10, the fifth coil is top coil element #49A, sixth coil is bottom coil element #48A, the third coil is bottom coil element #48B, and fourth coil is top coil element #49B, where coils B are not shown, the chips have the same configuration and therefore a second insulator similar to the first insulator exists); the second coil (Fig.10, first chip is element #80B, second coil is top coil element #45B, not shown but equivalent to top coil element #45A) is electrically connected to the fourth coil (Fig.10, top coil elements #45B and #49B are connected through wire equivalent to element #15A, see Fig.9 for top view); the third coil is electrically connected to the fifth coil (both coils are in the same chip separated by dielectric layers, therefore capacitive coupling exists); the third chip includes a seventh coil and an eighth coil magnetically coupled in a vertical alignment (Fig.10, seventh coil is element #43A and eighth coil is element #44A and isolated by a third insulator in the third chip; and a bonding wire connects the sixth coil in the second chip to the eighth coil in the third chip (Fig.10, wire element #13A connects element #48A to element #44A).
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Osada in view of Lee and in view of Richardson, (United States Patent Application Publication Number, US 2018/0233264 A1) hereinafter referenced as Richardson.
Regarding claim 3, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Osada does not teach the semiconductor device of claim 1, wherein: each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; and the first coil, the second coil, the third coil, and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. Lee teaches wherein each one of the first coil and the second coil have a spiral shape (Fig.1b and Fig.1c).The spiral shape allows for a compact footprint and a more uniform magnetic field as compared to other shapes.
Richardson teaches wherein: each one of the first coil (Fig.1A, first coil formed by elements #106 and #108), the second coil (Fig.1A, first coil formed by elements #102 and #104), has a spiral shape (Fig.2A, both have a spiral shape) and the first coil and the second coil have a same diameter, a same coil turn number, and a same winding direction (Fig.1A, both have the same diameter, coil turn number and winding direction). Since Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), the combination of Osada and Richardson also teaches each one of the third coil and the fourth coil has a spiral shape, and the third coil and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Richardson and disclose each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; and the first coil, the second coil, the third coil, and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. The spiral shape allows for a compact footprint and a more uniform magnetic field as compared to other shapes. Using coils with the same number of turns, same winding and diameter results in the coils having the same self-inductance, which increases the coupling coefficient. Furthermore, using identical components in a circuit simplifies the design process and helps reduce costs.
Regarding claim 13, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Osada does not teach the semiconductor device of claim 10, wherein: each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; the first coil, the second coil, the third coil, and the fourth coil have a same diameter; the first coil, the second coil, the third coil, and the fourth coil have a same coil turn number; and the first coil, the second coil, the third coil, and the fourth coil have a same winding direction. Lee teaches wherein each one of the first coil and the second coil have a spiral shape (Fig.1b and Fig.1c). The spiral shape allows for a compact footprint and a more uniform magnetic field as compared to other shapes.
Richardson teaches wherein: each one of the first coil (Fig.1A, first coil formed by elements #106 and #108), the second coil (Fig.1A, first coil formed by elements #102 and #104), has a spiral shape (Fig.2A, both have a spiral shape) and the first coil and the second coil have a same diameter, a same coil turn number, and a same winding direction (Fig.1A, both have the same diameter, coil turn number and winding direction). Since Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), the combination of Osada and Richardson also teaches each one of the third coil and the fourth coil has a spiral shape, and the third coil and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Richardson and disclose each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; and the first coil, the second coil, the third coil, and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. The spiral shape allows for a compact footprint and a more uniform magnetic field as compared to other shapes. Using coils with the same number of turns, same winding and diameter results in the coils having the same self-inductance, which helps achieve maximum coupling coefficient. Furthermore, using identical components in a circuit simplifies the design process and helps reduce costs.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Osada in view of Lee, in view of Fouquet et al., (United States Patent Application Publication Number, US 2008/0179963 A1) hereinafter referenced as Fouquet, in view of Mizuide, (United States Patent Number, US 4,806,791) hereinafter referenced as Mizuide.
Regarding claim 7, the combination of Osada and Lee teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Osada and Lee does not teach the semiconductor device of claim 1, wherein an output terminal of the third coil is connected to a differential comparator. Fouquet teaches wherein the output terminal of a bottom coil is connected to a differential comparator (paragraph [0015], rows 5-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fouquet and disclose wherein an output terminal of the third coil is connected to a differential comparator. As disclosed by Fouquet, the differential comparator can be configured to sense changes from both positive to negative output pulses (paragraph [0015], rows 11-17).
Fouquet does not disclose the differential comparator is an NPN comparator. Mizuide teaches a differential comparator is an NPN comparator. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mizuide and disclose the differential comparator is an NPN comparator. As disclosed by Mizuide, an NPN differential comparator can be responsive to high input difference voltage without degrading hysteresis characteristics (column 1, rows 26-30).
Regarding claim 16, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. The combination of Osada and Lee does not teach the semiconductor device of claim 10, wherein an output terminal of the third coil is connected to a NPN differential comparator. Fouquet teaches wherein the output terminal of a bottom coil is connected to a differential comparator (paragraph [0015], rows 5-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fouquet and disclose wherein an output terminal of the third coil is connected to a differential comparator. As disclosed by Fouquet, the differential comparator can be configured to sense changes from both positive to negative output pulses (paragraph [0015], rows 11-17).
Fouquet does not disclose the differential comparator is an NPN comparator. Mizuide teaches a differential comparator is an NPN comparator. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mizuide and disclose the differential comparator is an NPN comparator. As disclosed by Mizuide, an NPN differential comparator can be responsive to high input difference voltage without degrading hysteresis characteristics (column 1, rows 26-30).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Osada in view of Lee and in view of Sugahara (United States Patent Number, US 9899146 B2) hereinafter referenced as Sugahara.
Regarding claim 11, the combination of Osada and Lee teaches the semiconductor device of claim 10 as set forth in the obviousness rejection. Osada teaches the semiconductor device of claim 10, wherein the transmitter is a controller of a gate driver (Fig.1, element #20) and the receiver is a driver of the gate driver (Fig.1, element #30). The combination of Osada and Lee does not teach the semiconductor device of claim 10, wherein the transmitter is a controller of a voltage regulator and the receiver is a driver of the voltage regulator. Sugahara teaches a voltage regulator (Fig.11, and abstract, rows 1-4) where the isolator (Fig.11 caption, signal transfer device uses an insulator) receives a signal from transmitter that controls the isolator (Fig.11, logical circuit) and outputs a signal to a driver of the regulator (Fig.11 driver H). Therefore, the combination of Sugahara and Osada teaches wherein the transmitter is a controller of a voltage regulator and the receiver is a driver of the voltage regulator. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sugahara and disclose wherein the transmitter is a controller of a voltage regulator and the receiver is a driver of the voltage regulator. Using the semiconductor device disclosed by Osada in the regulator circuit disclosed by Sugahara provides an improved withstand voltage (Osada, paragraph [0080], rows 1-3) of the output transistors of the regulator.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sugahara, in view of Osada and Lee.
Regarding claim 18, Sugahara teaches a voltage regulator comprising: a controller configured to output a transmission signal (Fig.11, logical circuit) a power stage including a driver configured to drive a transistor (Fig.11, driver H) and an isolator (Fig.11 caption, signal transfer device uses an insulator). Sugahara does not teach the isolator including: a first chip including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip; a second chip including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip; and at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip. Osada teaches an insulator including a first chip (Fig.3, element #80A) including at least a first coil (Fig.3, element #43A) and a second coil (Fig.3, element #44A) magnetically coupled in a vertical alignment (Fig.3, paragraph [0030], rows 1-3) and isolated by a first insulator in the first chip (Fig.5, portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); a second chip (Fig.3, element #80B) including at least a third coil (Fig.3, element #46A) and a fourth coil (Fig.3, element #45A) magnetically coupled in a vertical alignment (Fig.3, paragraph [0030], rows 3-5) and isolated by a second insulator in the second chip (both chips have the same configuration, paragraph [0094], rows 1-2, therefore a second insulator similar to the first insulator exists); and at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip (Fig.3, wire element #11A connects second coil, element #44A, with the fourth coil, element #45A). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Osada and disclose an isolator including: a first chip including at least a first coil and a second coil magnetically coupled in a vertical alignment and isolated by a first insulator in the first chip; a second chip including at least a third coil and a fourth coil magnetically coupled in a vertical alignment and isolated by a second insulator in the second chip; and at least one bonding wire that connects the second coil in the first chip to the fourth coil in the second chip. Using the semiconductor device disclosed by Osada in the regulator circuit disclosed by Sugahara provides an improved withstand voltage (Osada, paragraph [0080], rows 1-3) of the output transistors of the regulator.
The combination of Sugahara and Osada does not teach wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Lee teaches wherein a width of the first coil is greater than a width of the second coil (Fig.1a, a width w1 of the first coil, element #200, is in the range 1 to 20um, column 7 rows 20-23, and a width w2 of the second coil, element #300, is in the range 2 to 20um, column 8 rows 38-40) a spacing between wires of the first coil is less than a spacing between wires of the second coil (Fig.1a, a spacing s1 of the first coil, element #200, is in the range 1 to 20um, column 7 rows 23-25, and a spacing s2 of the second coil, element #300, is in the range 2 to 20um, column 8 rows 40-43), and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil (based on the ranges above the sum of w1 and s1 can be the same as the sum of w2 and s2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose wherein a width of the first coil is greater than a width of the second coil, a spacing between wires of the first coil is less than a spacing between wires of the second coil, and a sum of the width of the first coil and spacing between wires of the first coil is same as a sum of the width of the second coil and spacing between wires of the second coil. Wider wires increase current capacity and reduce voltage drop across the coil, while smaller spacing can lead to increase leakage inductance. Furthermore, since the coils are manufactured using different metal levels and possibly different metals, they required different metal filling factors to ensure uniform layer densities during the manufacturing process. Considering the above, and since the two coils have to be designed to handle different voltages and loads, each one can be independently optimized by adjusting the wires width and spacing, while maintaining the same planar size for both to reduce the device footprint. Also, having the sum of the width of the first coil and spacing between wires of the first coil the same as a sum of the width of the second coil and spacing between wires of the second coil, results in the possibility of using the same number of turns for both, which simplifies the design process and results in increase efficiency.
Since Osada teaches both chips having the same configuration (paragraph [0094], rows 1-2) and Lee teaches the claimed differences in the width of the coils and spacing between wires of the coils, the combination of Osada and Lee also teaches wherein a width of the third coil is greater than a width of the fourth coil, a spacing between wires of the third coil is less than a spacing between wires of the fourth coil, and a sum of the width of the third coil and spacing between wires of the third coil is same as a sum of the width of the fourth coil and spacing between wires of the fourth coil.
Sugahara further teaches wherein the isolator is configured to: receive the transmission signal from the controller (Fig.11, the signal transfer device which comprises the insulator receives a signal from the logical circuit) and output the transmission signal to the driver (Fig.11, the signal transfer device which comprises the insulator outputs the signal to driver H).
Regarding claim 19, the combination of Sugahara, Osada and Lee teaches the semiconductor device of claim 18 as set forth in the obviousness rejection. Osada further teaches the voltage regulator of claim 18, wherein: the first coil (Fig.3, element #43A) is fabricated on a bottom layer of the first insulator (element #43A is located on the bottom layer of the first insulator, where the first insulator is the portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); the second coil (Fig.3, element #44A) is fabricated on a top layer of the first insulator (element #44A is located on the top layer of the first insulator, where the first insulator is the portion of element #85 including the layers in which elements #44A and 43A are located and all the layers in between); using top metal layer process (Fig.5, the coils are fabricated on metal layers on top of substrate, element #84); the third coil is fabricated on a bottom layer of the second insulator; the fourth coil is fabricated on a top layer of the second insulator using top metal layer process (second chip has same configuration as the first chip, paragraph [0094], rows 1-2); the second coil includes a first pad at a center of the second coil (Fig.5, element #44A includes pad element #82A at a center in the horizontal direction); the second coil includes a second pad at a terminal of the second coil (paragraph [0093], rows 1-5); the fourth coil includes a third pad at a center of the fourth coil (Fig.3, element #45A includes pad element #81B at a center in the horizontal direction); the fourth coil includes a fourth pad at a terminal of the fourth coil (paragraph [0093], rows 1-5); the at least one bonding wire include a first bonding wire that connects the first pad to the third pad (Fig.1, wire element #11A connects first and fourth pads, paragraph [0093], rows 1-5); and the at least one bonding wire include a second bonding wire that connects the second pad to the fourth pad (Fig.1, wire element #12A connects the second and fourth pad, paragraph [0093], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Osada and disclose an isolator configuration as claimed. As disclosed by Osada, this configuration provides an improved withstand voltage at the output of a gate driver (Osada, paragraph [0080], rows 1-3).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sugahara, in view of Osada, Lee and Richardson
Regarding claim 20, the combination of Sugahara, Osada and Lee teaches the semiconductor device of claim 18 as set forth in the obviousness rejection. The combination of Sugahara, Osada and Lee does not teach the voltage regulator of claim 18, wherein: each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; the first coil, the second coil, the third coil, and the fourth coil have a same diameter; the first coil, the second coil, the third coil, and the fourth coil have a same coil turn number; the first coil, the second coil, the third coil, and the fourth coil have a same winding direction.
Richardson teaches wherein: each one of the first coil (Fig.1A, first coil formed by elements #106 and #108), and the second coil (Fig.1A, first coil formed by elements #102 and #104), has a spiral shape (Fig.2A, both have a spiral shape), the first coil and the second coil have a same diameter, a same coil turn number, and a same winding direction (Fig.1A, both have the same diameter, coil turn number and winding direction). Since Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), the combination of Osada and Richardson also teaches each one of the third coil and the fourth coil has a spiral shape, and the first coil, the second coil, the third coil and the fourth coil have a same diameter, a same coil turn number, and a same winding direction. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Richardson and disclose each one of the first coil, the second coil, the third coil, and the fourth coil has a spiral shape; the first coil, the second coil, the third coil, and the fourth coil have a same diameter; the first coil, the second coil, the third coil, and the fourth coil have a same coil turn number; the first coil, the second coil, the third coil, and the fourth coil have a same winding direction. The spiral shape allows for a compact footprint and a more uniform magnetic field as compared to other shapes. Using coils with the same number of turns, same winding and diameter results in the coils having the same self-inductance, which helps achieve maximum coupling coefficient. Furthermore, using identical components in a circuit simplifies the design process and helps reduce costs.
The combination of Sugahara and Osada does not teach a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Lee teaches wherein a thickness of the second coil is greater than a thickness of the first coil (Fig.1a, a thickness t1 of the first coil is in the range 0.3 microns to 5 microns, column 7, rows 19-20 and a thickness of the second coil, t2 is in the range 3 microns to 10 microns, column 8, rows 36-38, also second coil is made in a thick metal layer). Osada teaches the first and the second chip have the same configuration (paragraph [0094], rows 1-2), and therefore, the combination of Osada and Lee also teaches a thickness of the fourth coil is greater than a thickness of the third coil. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose a thickness of the second coil is greater than a thickness of the first coil; a thickness of the fourth coil is greater than a thickness of the third coil. Making the second and fourth coils thicker that the first and third coils results in a lower electrical resistance which allows for higher current to flow through the coils and therefore transfer more power.
Response to Arguments
Applicant’s arguments filed on 01/28/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899