DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 11/04/2025 have been entered and considered. The amendments to claim 1, 20, and 24, the amendments to FIGS. 9A and 9B, and the cancelation of claims 1-4, 10-14, and 19 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim(s) 5 and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments and amendments to FIGS. 9A and 9B overcome the drawing objections presented in the office action filed 7/14/2025. The drawing objections are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 5-6, 15-16, 22 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lau et al US 20220336333 A1 (hereinafter referred to as Lau).
Regarding claim 5, Lau teaches,
A composite contact bump structure (“package structure 100b” para. 0067 FIG. 1Z) comprising:
a metal wiring layer (“first redistribution circuit 125” para. 0041);
a first seed layer (“seed material S22”, para. 0046) on the metal wiring layer;
a first metal stud (The portion of the “metal layer M22” in the “third opening 132” can be considered the metal stud, para. 0043, 0046.) and a first routing line protruding from the first seed layer, wherein the first routing line is integrally formed with the first metal stud (leftward extending portion of “metal layer M22” on “dielectric layer 130” is considered a routing line);
a first passivation layer (“third dielectric layer 140” para. 0047 FIG. 1P and 1Z) that laterally surrounds the first seed layer and the first metal stud, wherein the first seed layer does not laterally surround the first metal stud within the first passivation layer (sidewall of the “seed material S22” is coplanar with “metal layer M22” due to the photoresist removal process shown in FIG. 1N-1O, para. 0046);
a planarized surface formed of the first passivation layer and the first metal stud (“second upper surface 141” of the “third dielectric layer 140” is aligned with the “second surface 137” of the “second redistribution circuit 135”, para. 0062), wherein the planarized surface does not include the first seed layer (“seed material S22” is under the “metal layer M22” and not aligned with “second upper surface 141” and “second surface 137”);
a second passivation layer (“fourth dielectric layer 170” para. 0067) over the first passivation layer;
an opening (“fourth opening 172” para. 0050 FIG. 1R) in the second passivation layer;
a second seed layer (“seed layer S33” para. 0052 FIG. 1S) on the second passivation layer, within the opening in the second passivation layer and over the first metal stud (“seed layer S33” is formed within “fourth opening 172” and in contact with “second surface 157” of the metal layer, para. 0051-0052); and
a second metal stud (“metal layer M33” para. 0052 FIG. 1S) on the second seed layer within the opening in the second passivation layer (a portion of “metal layer M33” is formed on the “seed layer S33” within the “fourth opening 172”).
Regarding claim 6, Lau teaches the composite contact bump structure of claim 5, further comprising a solder material (“solder ball 195” para. 0060) on top of the second metal stud.
Regarding claim 15, Lau teaches the composite contact bump structure of claim 5, wherein the second metal stud protrudes away from the second passivation layer (“seed layer S33” and “metal layer M33” protrude away from “surface 171” of the “fourth dielectric layer 170”, para. 0067).
Regarding claim 16, Lau teaches composite contact bump structure of claim 5, wherein the second metal stud and the first metal stud are formed of a same metal (based on the shadings of the “metal layer M22” and “metal layer M33”, the examiner understands they are the same material).
Regarding claim 22, Lau teaches the composite contact bump structure of claim 5, further comprising a redistribution layer (“second redistribution layer RDL22” para. 0049) between the first metal stud and the second metal stud.
Regarding claim 23, Lau teaches the composite contact bump structure of claim 22, wherein the second metal stud is connected to the first metal stud through a wiring trace in the redistribution layer (The portion of the “metal layer M22” in the “third opening 132” is electrically connected to “metal layer M33” through the “second redistribution layer RDL22”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lau as applied to claim 6 in view of Yu et al. US 20210358854 A1 (hereinafter referred to as Yu) and Bezama et al. US 20110147922 A1 (hereinafter referred to as Bezama).
Regarding claim 7, Lau teaches the composite contact bump structure of claim 6 but fails to teach wherein the solder material is a C4 bump on top of the second metal stud.
Nevertheless, Yu teaches “Die connectors 66A and 66B” electrically connected to “under-bump metallizations (UBMs) 130” and “conductive connectors 132” formed on “under-bump metallizations (UBMs) 130” (para. 0056, 0086 FIG. 14). The “conductive connectors 132” bond to a “substrate core 302” (para. 0103 FIG. 14). As further taught in Bezama et al. US 20110147922 A1, C4 bumps are common interconnect structures between devices (Bezama para. 0002). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that solder C4 bumps are known for connecting electronic devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the composite contact bump structure in Lau with the C4 bump taught between Yu and Bezama. C4 bumps are known alternatives for interconnecting electronic devices.
Regarding claim 8, Lau, modified by Yu and Bezama, teaches the composite contact bump structure of claim 7, wherein the C4 bump is thicker than a thickness of the second metal stud protruding away from the second passivation layer (as suggested in FIG. 9 and 13, the thickness of "conductive connector 132" is greater than the thickness of "UBM 130" that protrudes past "insulating layer 128").
Regarding claim 9, Lau, modified by Yu and Bezama, teaches 9 the composite contact bump structure of claim 7, wherein the second metal stud is wider than the first metal stud (The portion of the “metal layer M22” in the “third opening 132” has a narrower width than “metal layer M33”).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lau as applied to claim 5 above, in view of Ohsumi US 20040201097 A1 (hereinafter referred to as Ohsumi).
Lau teaches the composite contact bump structure of claim 5 but fails to teach wherein a center point of the second metal stud is offset from a center point of the first metal stud by at least a half maximum width of the second metal stud.
Nevertheless, Ohsumi teaches
wherein a center point of the second metal stud (center point of “columnar electrode 117”, para. 0088 FIG. 9) is offset from a center point of the first metal stud (center point of “metal wiring layer 111” para. 0088 FIG. 9) by at least a half maximum width of the second metal stud (FIG. 9 suggests that “columnar electrode 117” is shifted from the center point of “metal wiring layer 111” more than at least a half width of “columnar electrode 117”).
Lau and Ohsumi teach interconnect structures with multiple metal layers. Ohsumi has the “columnar electrode 117” shifted by the “metal wiring layer 111” so that the pitch of a plurality of the “columnar electrodes 117” can be made greater than the pitch of the “electrode pads 109” of “semiconductor substrate 107” (para. 0076). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that shifting the centers of “metal layer 464” and “copper layer 37” can be done so that the pitch of the “metal layer 464” is more relaxed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the composite contact bump structure in Lau with the offset between first and second metal studs as taught in Ohsumi. Shifting the second metal studs allows for manipulation of the pitch.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lau as applied to claim 5 above, in view of Baek et al. US 20180053732 A1 (hereinafter referred to as Baek).
Regarding claim 20, Lau teaches the composite contact bump structure of claim 5 but fails to teach wherein the routing line connects to a second first metal stud.
Nevertheless, Baek teaches
wherein the routing line (“redistribution layer 142” para. 0081 FIG. 13) connects to a second first metal stud (“via 143” under “first redistribution layer 112a”, FIG. 13).
Lau and Baek teach interconnect structures with multiple metal layers. The “second connection member 140” comprises “redistribution layers 142” and “vias 143” that are connected to each other and may consist of the same material (para. 0096 and 0098-0099). The “vias 143” and “redistribution layers 142” are connected to the “connection pads 122” of the “semiconductor chip 120” (para. 0093, 0099 FIG. 13). The “vias 143” are in contact with the “first redistribution layer 112a” of the “first connection member 110” (para. 0088) that connects to the “interposer substrate 210” and the memory package containing “memory 240” (para. 0107 FIG. 13). “Redistribution layer 142” also connects with the “under-bump metal layer 160” (para. 0101). As such, the “via 143” under “first redistribution layer 112a” and “redistribution layer 142” interconnect “semiconductor chip 120” with multiple devices. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “via 143” further connected to “redistribution layer 142” would allow multiple components to be connected to the “semiconductor chip 120”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the composite contact bump structure in Lau with the second first metal stud as taught in Baek. The second metal stud connected to the routing line further distributes signal to more components, increasing the device integration within the same package.
Regarding claim 21, Lau, modified by Baek, teaches the composite contact bump structure of claim 5, wherein the second passivation layer (“passivation layer 150” para. 0100 FIG. 13) spans over the routing line (“passivation layer 150” covers portions of “redistribution layer 142” except where “under-bump metal layer 160”, the second metal stud, is formed, para. 0101).
Claims 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al US 20220336333 A1 (hereinafter referred to as Lau), in view of Yu et al US 20210358854 A1 (hereinafter referred to as Yu).
Regarding claim 24, Lau teaches
(Currently amended) An electronic package (“package structure 100b” para. 0067 FIG. 2) comprising:
a first die (structure from “first lower surface 113” to “solder ball 195”, para. 0054, 0060 FIG. 1Z) embedded in a molding compound layer (“molding compound 190” para. 0058), the first die comprising:
a metal wiring layer (“first redistribution circuit 125” para. 0041);
a first seed layer (“seed material S22”, para. 0046) on the metal wiring layer;
a first metal stud (The portion of the “metal layer M22” in the “third opening 132” can be considered the metal stud, para. 0043, 0046.) and a first routing line protruding from the first seed layer, wherein the first routing line is integrally formed with the first metal stud (leftward extending portion of “metal layer M22” on “dielectric layer 130” is considered a routing line);
a first passivation layer (“third dielectric layer 140” para. 0047 FIG. 1P and 1Z) that laterally surrounds the first seed layer and the first metal stud, wherein the first seed layer does not laterally surround the first metal stud within the first passivation layer (sidewall of the “seed material S22” is coplanar with “metal layer M22” due to the photoresist removal process shown in FIG. 1N-1O, para. 0046);
a planarized surface formed of the first passivation layer and the first metal stud (“second upper surface 141” of the “third dielectric layer 140” is aligned with the “second surface 137” of the “second redistribution circuit 135”, para. 0062), wherein the planarized surface does not include the first seed layer (“seed material S22” is under the “metal layer M22” and not aligned with “second upper surface 141” and “second surface 137”);
a second passivation layer (“fourth dielectric layer 170” para. 0067) over the first passivation layer
an opening in the second passivation layer (“fourth opening 172” para. 0050 FIG. 1R);
a second seed layer (“seed layer S33” para. 0052 FIG. 1S) on the second passivation layer, within the opening in the second passivation layer and on the first metal stud (“seed layer S33” is formed within “fourth opening 172” and in contact with “second surface 157” of the metal layer, para. 0051-0052); and
a second metal stud (“metal layer M33” para. 0052 FIG. 1S) on the second seed layer within the opening in the second passivation layer (a portion of “metal layer M33” is formed on the “seed layer S33” within the “fourth opening 172”).
However, Lau fails to teach a planarized surface formed of the first passivation layer, the first metal stud, and the molding compound layer, the second passivation layer spanning over the molding compound layer.
Nevertheless, Yu teaches
a planarized surface formed of the first passivation layer, the first metal stud, and the molding compound layer (top surfaces of "insulating layer 68", “encapsulant 112”, and "die connectors 66A, 66B" are coplanar, para. 0073 FIG. 8-9 and 14),
the second passivation layer ("insulating layers 116, 120, 124, and 128" para. 0074 FIG. 9 and 14) spanning over the molding compound layer ("insulating layers 116, 120, 124, and 128" is over "insulating layer 68" and "encapsulant 112").
Lau and Yu teach packages with multilevel interconnections. The package in Lau comprises a single die having a first metal stud “metal layer M22” connected to a second metal stud “metal layer M33” connected through “second redistribution layer RDL22”. Meanwhile, the package in Yu features a plurality of “integrated circuit die 10 and 20” having first metal studs “Die connectors 66A and 66B” connected to second metal studs “UBMs 130” through a “redistribution structure 114” (para. 0056, 0061, 0085). The “encapsulant 112” surrounds and protects both “integrated circuit die 10 and 20” (para. 0072). “Redistribution structure 114” interconnects “die connectors 66A and 66B” with each other and to “substrate core 302” and “package components 200” (para. 0092, 0103). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that multiple die can be integrated into a same package by coupling their “die connectors 66A and 66B” to a same “redistribution structure 114”. The die can be protected by surrounding them with “encapsulant 112” before forming “redistribution structure 114”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic package in Lau with the additional components taught in Yu. Instead of a single component, a plurality of components having first metal studs can be integrated into the electronic package by surrounding them in molding compounds and forming a common redistribution structure on their first metal studs.
Regarding claim 26, Lau, modified by Yu, teaches the electronic package of claim 24, further comprising a second die (“integrated circuit die 20” para. 0074) embedded within the molding compound layer, and a redistribution layer (“redistribution structure 114” para. 0074 FIG. 9) spanning over the first die, the second die, and the molding compound layer, wherein the redistribution layer includes a die-to-die routing (“trace 118B” that extends from “die 10” to “die 20”, para. 0076 FIG. 9) connecting another metal stud on the metal wiring layer of the first die to the second die (FIG. 9 shows a “trace 118B” contacting a “die connector 66A, 66B” in “die 10” and a “die connector 66A, 66B” in “die 20”).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lau, modified by Yu, as applied to claim 24, in view of Lim et al. US 20110095418 A1 (hereinafter referred to as Lim).
Lau, modified by Yu teaches the electronic package of claim 24 but fails to teach further comprising a dummy second metal stud over the first die, wherein the dummy second metal stud is not electrically connected to the first die.
Nevertheless, Lim teaches
further comprising a dummy second metal stud (“bump 132” para. 0087 FIG. 1B) over the first die (“semiconductor chip 150” para. 0087 FIG. 1A-1B), wherein the dummy second metal stud is not electrically connected to the first die (“bump 132” is not connected to “enter chip pad 161”, para. 0087).
Lau, modified by Yu, and Lim teach external interconnection structures. The “semiconductor chip 150” includes dummy bumps such as “bump 132” to physical support “semiconductor chip 150” on the “package substrate 110”. Meanwhile, “bumps 131 and 141” are the ones that provide a signal path for the “semiconductor chip 150” (para. 0087-0088). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that extra bumps electrically disconnected from “semiconductor chip 150” can serve to physically support the chip on a substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic package taught between Lau and Yu with the dummy second metal stud taught in Lim. Dummy second metal studs can help physically support the die.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Lau, modified by Yu, as applied to claim 24, in view of Gong et al. US 20180233462 A1 (hereinafter referred to as Gong).
Lau, modified by Yu, teaches the electronic package of claim 24, further comprising a redistribution layer (“second redistribution layer RDL22” Lau para. 0049 FIG. 2 and “redistribution structure 114” in Yu para. 0074) between the first metal stud and the second metal stud.
However, Yu fails to teach a seal ring structure within the redistribution layer.
Nevertheless, Gong teaches
a seal ring structure (“seal ring 150” para. 0020 FIG. 1-2) within the redistribution layer (“RDL 220” para. 0020 FIG. 2).
Lau, modified by Yu, and Gong teach interconnect structures on semiconductor chips. The “RDL 220” includes the “seal ring 150” as a grounding path (para. 0023) and as protection against cracking and delamination of “RDL 220” (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “seal ring 150” can be implemented in the redistribution layer taught between Lau and Yu for electric and physical protection.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic package taught between Lau and Yu with the ring seal structure taught in Gong. The ring seal structure protects the redistribution layer from delamination and cracking while also serving as a ground path.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898