DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 4/30/2026. Claims 1-3, 5-11, 13-20 and 22-24 are pending and have been examined. Claims 1, 5, 9, 13, 18, and 22 have been amended. Claims 4, 12 and 21 have been canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-11, 13-20 and 22-24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “A computing system” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “a generative adversarial network…convert the input data from a first domain into a frequency domain…a generative model, and a discriminative model …wherein the generative model and the discriminative model operate in a frequency domain…wherein one or more of the generative model or discriminative model…” which describe a process that under its broadest reasonable interpretation encompasses mathematical concepts. That is other than reciting generic computing components (e.g. network controller, accelerator including logic and substrates, transformation hardware, array of processing elements, global instruction buffer, a plurality of local instruction buffers) nothing in the claimed elements precludes the steps from practically being performed in the mind with the aid of pen and paper.
For example, the claim discusses a generative adversarial network, performing input data conversion from first domain to frequency domain and a generative model and a discriminative model operating in a frequency domain, thus the limitations encompass mathematical calculations and/or equations (MPEP 2106.04(a)(2)(I)) (see paragraphs [0002, 0023-0026, 0076] and Fig. 3: wherein conversion uses a discrete cosine transform and the models of the GAN comprise convolution operations)
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation/equation in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
a network controller…accelerator coupled to the network controller, wherein the accelerator includes logic coupled to one or more substrates, the logic including: transformation hardware… the transformation hardware… an array of processing elements, a global instruction buffer coupled to the array of processing elements… single instruction multiple data (SIMD) instructions to columns in the array of processing elements, and a plurality of local instruction buffers coupled to the array of processing elements and the global instruction buffer, wherein the plurality of local instruction buffers… multiple instruction multiple data (MIMD) instructions to rows in the array of processing elements
obtain input data… selectively issue single instruction multiple data (SIMD) instructions… selectively issue multiple instruction multiple data (MIMD) instructions
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)) (note it can also be viewed as nothing more than an attempt to generally link the use of the judicial exception to the technological environment of accelerators and SIMD/MIMD processing (MPEP 2106.05(h)) and (b) recites insignificant extra-solution activity (i.e. data gathering and outputting of particular type of data (such as SIMD/MIMD data)) (See MPEP 2106.05 (g and h)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (e.g. “apply it”) (see MPEP 2106.05(f)) and/or it can also be viewed as nothing more than an attempt to generally link the use of the judicial exception to the technological environment of accelerators and MIMD/SIMD processing (MPEP 2106.05(h)); (b) recites insignificant extra-solution activity of data gathering and outputting (see MPEP 2106.05(g-h)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
5. Claim 2, dependent upon claim 1, further recites “…wherein operation of the generative model and the discriminative model in the frequency domain includes element-by-element multiplication operations”, which discloses an additional abstract idea of operations in frequency domain including multiplication operations. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
6. Claim 3, dependent upon claim 1, further recites “…wherein operation of the generative model and the discriminative model in the frequency domain bypasses one or more convolution operations” which discloses an additional abstract idea of operations in frequency domain bypassing one or more convolution operations (e.g. the operations include at least one convolution operation). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
7. Claim 5, dependent upon claim 1, further recites “…wherein each processing element in the array of processing elements includes data access hardware to retrieve the input data and data processing hardware to process the retrieved input data, and wherein the data access hardware is separate from the data processing hardware”, which discloses additional limitations which use mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (e.g. “apply it”) (see MPEP 2106.05(f)) and/or it can also be viewed as nothing more than an attempt to generally link the use of the judicial exception to the technological environment of SIMD/MIMD processing (MPEP 2106.05(h). The additional limitations also disclose retrieving input data which can be viewed as an insignificant extra-solution activity (e.g. data gathering) which is well-understood, routine and conventional (MPEP 2106.05(d and g) (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
8. Claim 6, dependent upon claim 5, further recites “…wherein each data processing hardware includes zero detection hardware to detect zero values in the input data”, which discloses an additional abstract idea of detecting zero values which can be an evaluation or determination (e.g. a mental process). The claim further includes additional limitations which use mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (e.g. “apply it”) (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
9. Claim 7, dependent upon claim 1, further recites “…further including a random number generator coupled to the generative model, wherein the random number generator is to insert zero values into an output to the generative model”, which discloses additional limitations which use mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (e.g. “apply it”) (see MPEP 2106.05(f)). The additional limitations also disclose outputting zero values which can be viewed as an insignificant extra-solution activity (e.g. data outputting) which is well-understood, routine and conventional (MPEP 2106.05(d and g) (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
10. Claim 8, dependent upon claim 1, further recites “…further including a loss function generator coupled to the discriminative model and the generative models”, which discloses additional limitations which use mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (e.g. “apply it”) (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
11. Claims 9 and 18 are similarly rejected on the same basis as claim 1 above.
12. Claims 10-11, 13-17, 19-20 and 22-24 are similarly rejected on the same basis as claims 2-3 and 5-8 above. (Note: Claim 17 includes an additional limitation not explicitly mirrored in claims 2-8, however the additional limitations merely recite generic computing components and thus fall under MPEP 2106.05(f). Thus, the additional limitations would not integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.)
Claim Rejections - 35 USC § 103
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claim(s) 1-3, 5, 9-11, 13, 17-20 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference, “FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks” hereby referred to as FlexiGAN, NPL reference “Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain”, hereby referred to as Frequency Domain and further in view of Kale, PGPUB No. 2022/0043696.
In regards to claim 1, FlexiGAN discloses a generative adversarial network (GAN) accelerator (see pages 65-68: wherein a FPGA accelerator for a GAN network is disclosed (See Figs. 2 and 5)) wherein the GAN accelerator includes logic, the logic including: a generative model, and a discriminative model (see pages 66-67 and section IV: wherein FPGA includes logic (e.g. JSON file information, Etc.) including generative and discriminative models (See Fig. 2)) wherein the generative model and the discriminative model are to operate in a domain. (See page 65, section I: wherein the generative and discriminative model operate in a domain. “GANs [1] automatically generate bigger and richer datasets from a small labeled set and have been proven to be effective in various domains…”) wherein one or more of the generative model or the discriminative model include: an array of processing elements (FlexiGAN, page 68, See Fig. 5: wherein a GAN accelerator includes a plurality of compute engines) a global instruction buffer coupled to the array of processing elements, wherein the global instruction buffer is to selectively issue single instruction multiple data (SIMD) instructions to columns in the array of processing elements, and a plurality of local instruction buffers coupled to the array of processing elements and the global instruction buffer, wherein the plurality of local instruction buffers are to selectively issue multiple instruction multiple data (MIMD) instructions to rows in the array of processing elements. (FlexiGAN: see pages 68-69, section VI and Fig. 5)
FlexiGAN does not disclose A computing system comprising: a network controller to obtain input data; a network accelerator coupled to the network controller, wherein the network accelerator includes logic coupled to one or more substrates, the logic including: transformation hardware to convert the input data from a first domain into a frequency domain, a model coupled to the transformation hardware, wherein the model operates in the frequency domain.
Frequency Domain discloses network accelerator includes logic including: transformation hardware to convert the input data from a first domain into a frequency domain (page 4, section 5, and Fig. 11(a): wherein a hardware network accelerator includes an FFT/IFFT module that converts input data from a first domain to frequency domain (also see Fig. 2(c)) a model coupled to the transformation hardware, wherein the model operates in the frequency domain. (page 1 and last page conclusion: wherein CNN model (implemented using complex multiplier/accumulator) is indirectly coupled to FFT/IFFT module and wherein CNN model operates in a frequency domain (See Figs. 2(c), and 11(a))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the GAN accelerator of FlexiGAN to perform in a frequency domain as the accelerator taught in Frequency Domain. It would have been obvious to one of ordinary skill in the art because operating a neural network model that performs convolutions in a frequency domain can improve speed, energy efficiency and reduce memory overhead in an accelerator (See Frequency Domain, page 2, section 1 and last page section 6).
The combination FlexiGAN and Frequency Domain does not disclose A computing system comprising: a network controller to obtain input data; a network accelerator coupled to the network controller, wherein the network accelerator includes logic coupled to one or more substrates.
Kale discloses A computing system ([0207-0208] and Figs. 12-13) comprising: a network controller to obtain input data ([0208-0210]: wherein network interface (element 341) reads input data for ANN (element 211)) a network accelerator coupled to the network controller ([0208-0210]: wherein deep learning accelerator (element 103) is indirectly coupled to network interface (element 341) (See Fig. 13)) wherein the network accelerator includes logic coupled to one or more substrates. ([0055-0056]: wherein deep learning accelerator includes logic coupled to one or more substrates (e.g. semiconductor substrate of CMOS or integrated circuit dies of FPGA))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the GAN accelerator of FlexiGAN and Frequency Domain to be a part of a system including a network controller and include substrate as the neural network accelerator of Kale. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (using a network accelerator including one or more substrates in a system using a network controller to obtain inputs for the network accelerator as taught in Kale) to a known device (GAN accelerator of FlexiGAN and Frequency Domain) ready for improvement to yield predictable results (a system including a network controller and a GAN accelerator, including one or more substrates) for the benefit of using an accelerator in a network system environment as to improve networking operations and data communications across a network (also see Kale [0025]) (MPEP 2143, Example D).
Claim 9 is similarly rejected on the same basis as claim 1 above as claim 9 is the accelerator corresponding to the system of claim 1 above. (Note: claim 9 includes an additional limitation stating “wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware”. The references disclose “wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware” (FlexiGAN: pages 65-67: discloses an FPGA which includes configurable hardware| Frequency Domain: page 1, abstract and page 5, section 5.1: wherein ASIC and FPGA hardware is disclosed |Kale [0055-0056])
Claim 18 is similarly rejected on the same basis as claim 1 above as claim 18 is the method corresponding to the system of claim 1 above. (Note: claim 18 includes an additional limitation stating “supply the converted input data to a discriminative model”. The examiner asserts that the combination of FlexiGAN and Frequency Domain would disclose the above limitation (see FlexiGAN: pages 66-67 and section IV (See Fig. 2) |Frequency Domain: page 1 and last page conclusion (See Figs. 2(c) and 11(a))
In regards to claim 2, the combination of FlexiGAN, Frequency Domain and Kale discloses The computing system of claim 1 (see rejection of claim 1 above) wherein operation of the generative model and the discriminative model in the frequency domain includes element-by-element multiplication operations. (Frequency Domain: page 5, section 5.1: “As Figure 11(b) shows, the computation engine is designed to accumulate each output feature plane after element-wise multiplication” (also see abstract and section 6 conclusion: which disclose pointwise and element wise multiplications))
Claim 10 is similarly rejected on the same basis as claim 2 above as claim 10 is the accelerator corresponding to the system of claim 2 above.
Claim 19 is similarly rejected on the same basis as claim 2 above as claim 19 is the method corresponding to the system of claim 2 above.
In regards to claim 3, the combination of FlexiGAN, Frequency Domain and Kale discloses The computing system of claim 1 (see rejection of claim 1 above) wherein operation of the generative model and the discriminative model in the frequency domain bypasses one or more convolution operations. (Frequency Domain: see abstract and section 6 conclusion: which discloses replacing convolutions (e.g., bypassing convolutions) with element wise multiplications)
Claim 11 is similarly rejected on the same basis as claim 3 above as claim 11 is the accelerator corresponding to the system of claim 3 above.
Claim 20 is similarly rejected on the same basis as claim 3 above as claim 20 is the method corresponding to the system of claim 3 above.
In regards to claim 5, the combination of FlexiGAN, Frequency Domain and Kale discloses The computing system of claim 4 (see rejection of claim 4 above) wherein each processing element in the array of processing elements includes data access hardware to retrieve the input data and data processing hardware to process the retrieved input data, and wherein the data access hardware is separate from the data processing hardware. (FlexiGAN, pages 68-69, See Figs. 5-6: wherein a GAN accelerator includes a plurality of compute engines each including separate data retrieval hardware and data processing hardware)
Claim 13 is similarly rejected on the same basis as claim 5 above as claim 13 is the accelerator corresponding to the system of claim 5 above.
Claim 22 is similarly rejected on the same basis as claim 5 above as claim 22 is the method corresponding to the system of claim 5 above.
In regards to claim 17, the combination of FlexiGAN, Frequency Domain and Kale discloses The GAN accelerator of claim 9 (see rejection of claim 9 above) wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. (Kale [0055-0056]: wherein an accelerator logic includes CMOS which is a type of transistor (MOSFET) which would include a transistor channel region positioned within one or more substrates)
15. Claim(s) 6, 14 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over FlexiGAN, Frequency Domain, Kale and further in view of Desai, PGUB No. 2019/0041961.
In regards to claim 6, the combination of FlexiGAN, Frequency Domain and Kale discloses The computing system of claim 5 (see rejection of claim 5 above) wherein each data processing hardware (FlexiGAN: see pages 68-69, section VI and Fig. 5)
The combination of FlexiGAN, Frequency Domain and Kale does not disclose zero detection hardware to detect zero values in the input data.
Desai discloses zero detection hardware to detect zero values in the input data. ([0225 and 0230])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the compute engines of FlexiGAN to include compute hardware to detect zero values in input values as taught in Desai. It would have been obvious to one of ordinary skill in the art because detecting zero values can be used to clock gate zero activations and save compute power in neural network architectures (Desai [0230]).
Claim 14 is similarly rejected on the same basis as claim 6 above as claim 14 is the accelerator corresponding to the system of claim 6 above.
Claim 23 is similarly rejected on the same basis as claim 6 above as claim 23 is the method corresponding to the system of claim 6 above.
16. Claim(s) 7, 15 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over FlexiGAN, Frequency Domain, Kale and further in view of Hegde, PGUB No. 2021/0103822.
In regards to claim 7, the combination of FlexiGAN, Frequency Domain and Kale discloses The computing system of claim 1 (see rejection of claim 1 above) insert zero values into an output to the generative model (FlexiGAN, pages 66-68: “… The primary operation in generative models (transposed convolution or TranConv) fundamentally differs from the one in discriminative models (convolution or Conv). The Conv operation shrinks the input while TranConv expands it by first inserting zeros within its rows and columns (see Fig. 3a))
The combination of FlexiGAN, Frequency Domain and Kale does not explicitly disclose further including a random number generator coupled to the generative model, wherein the random number generator is to insert zero values into an output to the generative model. While, FlexiGAN discloses inserting zeroes into an output of a generative model, it does not disclose using a random number generator to insert zeroes into the output.
Hedge discloses further including a random number generator coupled to the generative model, wherein the random number generator is to insert zero values into an output to the generative model. ([0067, 0071 and 0078]: wherein latent space vector generator is generating random numbers including zeroes, and the generator is coupled to a generator model as to insert random zeroes (See Figs. 2-3))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the insertion of zeroes into a generative model of a generative adversarial network as taught in FlexiGAN to be performed by a random number generator as taught in the generative adversarial network of Hedge. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a random number generator to insert zeroes into a generative model as taught in Hedge) for another (generically inserting zeroes into a generative model as taught in FlexiGAN) to yield predictable results (using a random number generator to insert zeroes into an output of a generative model) (MPEP 2143, Example B). In addition, using a random number generator to insert values into a generative model allows the generator to produce novel/realistic data which would improve the robustness of generative adversarial networks.
Claim 15 is similarly rejected on the same basis as claim 7 above as claim 15 is the accelerator corresponding to the system of claim 7 above.
Claim 24 is similarly rejected on the same basis as claim 7 above as claim 24 is the method corresponding to the system of claim 7 above.
17. Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over FlexiGAN, Frequency Domain, Kale and further in view of Jin, PGPUB No. 2021/0343305.
In regards to claim 8, the combination of FlexiGAN, Frequency Domain and Kale discloses The computing system of claim 1 (see rejection of claim 1 above).
The combination of FlexiGAN, Frequency Domain and Kale does not disclose further including a loss function generator coupled to the discriminative model and the generative model.
Jin discloses further including a loss function generator coupled to the discriminative model and the generative model. (See Fig. 3: wherein a loss function generator (element 330) is coupled to a discriminator model (element 320) and a generative model (element 230))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the generative adversarial network as taught in FlexiGAN to be include a loss function generator as the generative adversarial network taught in Jin. It would have been obvious to one of ordinary skill in the art because using a loss function allows updates to the generative and discriminator models to improve performance of the models and reduce errors in a GANs (Jin [0044]).
Claim 16 is similarly rejected on the same basis as claim 8 above as claim 16 is the accelerator corresponding to the system of claim 8 above.
Response to Arguments
18. Applicant's arguments with regards to 35 USC 101, of the remarks on filed 4/30/2026, have been fully considered but they are not persuasive. Therefore, the 35 USC 101 rejections of claims 1-3, 5-11, 13-20 and 22-24 have been maintained.
19. Applicant first argues on page 7 of the remarks filed on 4/30/2026, in the substance that:
“The Office asserts that the claims are directed to a judicial exception, specifically the abstract idea of "mathematical concepts" that can be practically performed in the mind with the aid of pen and paper. Applicant respectfully disagrees. The claims do not recite any specific mathematical formula, equation, or calculation. Instead, independent claim 1 recites specific hardware components, including a "network controller," a "GAN accelerator," and "transformation hardware." Furthermore, the volume and complexity of converting input data from a time domain into a frequency domain and operating generative and discriminative machine learning models within that frequency domain cannot practically be performed in the human mind in real-time. As noted in SRI Int'l, Inc. v. Cisco Systems, Inc., 930 F.3d 1295 (Fed. Cir. 2019), limitations requiring complex data processing by specific hardware cannot be considered mental processes. Therefore, the claims are not directed to a judicial exception under Subject Matter Eligibility Step 2A, Prong 1.”
The applicant argues above that the claim does not recite any specific mathematical formula, equation or calculation. However, the examiner respectfully disagrees as the claims explicitly recite converting input data from a first domain into a frequency domain and converting data is a mathematical concept as discussed in MPEP 2106.04(a)(2)(I) (See MPEP 2106.04(a)(2)(I)(A-C) “…a conversion between binary coded decimal and pure binary, Benson, 409 U.S. at 64, 175 USPQ at 674… using a formula to convert geospatial coordinates into natural numbers, Burnett v. Panasonic Corp., 741 Fed. Appx. 777, 780 (Fed. Cir. 2018) …”) Furthermore, paragraphs [0002, 0023-0026 and 0076] of the instant application explicitly disclose a discrete cosine transform is used for the conversion and that is a mathematical operation/algorithm used to perform the conversion of the data to the frequency domain. Thus, the claimed conversion is performed by an algorithm implemented on a generic computing component (e.g. transformation hardware). Furthermore, the claimed models are machine learning models implemented using convolution operations (e.g. math) as disclosed in paragraph [0002]. Thus, the claims include mathematical concepts implemented using generic hardware (accelerator, transformation hardware and network controller).
Additionally, it appears the applicant is arguing that a human mind with the aid of pen and paper could not convert input data from a time domain to a frequency domain, due to complexity. However, the examiner respectfully disagrees as a small input data set could be converted to a frequency domain as taught in a signals and systems or digital signal processing class. In such a class, a person is taught how to convert a small input data set using the human mind (with aid of pen and paper) to a frequency domain using mathematical operators such as Fourier transforms (e.g., conversion from x(t) to x (ꞷ)).
20. Applicant then argues on pages 7-8 of the remarks filed on 4/30/2026, in the substance that:
“Even if the claims were found to recite or involve an abstract idea, they integrate that alleged exception into a practical application by improving the functioning of a computer, satisfying Subject Matter Eligibility Step 2A, Prong 2. The Office improperly dismisses the recited "GAN accelerator," "transformation hardware," and "network controller" as generic computing components. This is an improper high-level overgeneralization of the claims. The claims recite a specific hardware architecture wherein logic coupled to one or more substrates includes transformation hardware that uniquely converts input data into a frequency domain specifically for the operation of both a generative model and a discriminative model in that frequency domain. This is a specific hardware arrangement designed to solve the technical problem of computational inefficiencies in traditional spatial-domain GAN operations. It is not a mere generic computer being used as a tool to perform an abstract idea, but a uniquely configured machine architecture.
This specific hardware architecture provides a tangible improvement to the functioning of the GAN accelerator itself. Specifically, the specification at paragraph [0028] describes that operating the generative and discriminative models in the frequency domain using the claimed transformation hardware allows for traditional convolution operations to be bypassed and replaced by simple element-by-element multiplication operations. This significantly reduces computational requirements and latency without negatively impacting accuracy. Under MPEP 2106.04(d) and Enfish, LLC v. Microsoft Corp., 822 F.3d 1327 (Fed. Cir. 2016), claims that are directed to an improvement in the functioning of a computer-such as reducing computational load and improving processing efficiency in a hardware neural network accelerator-are integrated into a practical application and are patent-eligible. Furthermore, as reinforced by Ex Parte Desjardins, Appeal No. 2024-000567 (which is binding precedent that appears to have been ignored), claims that recite specific techniques and hardware configurations that improve the operation of the underlying hardware are patent-eligible under Step 2A, Prong 2. Accordingly, the claims are patent-eligible under 35 U.S.C. 101. Withdrawal of the rejection is respectfully requested.”
It appears applicant argues above that the claim limitations do not recite generic computing components but rather claim a specific machine architecture used to solve computational efficiencies. Thus, it appears applicant is arguing the use of a particular machine as disclosed in MPEP 2106.05(b). However, the examiner respectfully disagrees. MPEP 2106.05(b) states “…It is important to note that a general-purpose computer that applies a judicial exception, such as an abstract idea, by use of conventional computer functions does not qualify as a particular machine….If applicant amends a claim to add a generic computer or generic computer components and asserts that the claim recites significantly more because the generic computer is 'specially programmed' (as in Alappat, now considered superseded) or is a 'particular machine' (as in Bilski), the examiner should look at whether the added elements integrate the exception into a practical application or provide significantly more than the judicial exception. Merely adding a generic computer, generic computer components, or a programmed computer to perform generic computer functions does not automatically overcome an eligibility rejection. Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S. 208, 223-24, 110 USPQ2d 1976, 1983-84 (2014). See In re Alappat, 33 F.3d 1526, 1545, 31 USPQ2d 1545, 1558 (Fed. Cir. 1994); In re Bilski, 545 F.3d 943, 88 USPQ2d 1385 (Fed. Cir. 2008).” The examiner notes that the above argued limitations stating “a GAN accelerator”, “transformation hardware”, and “network controller” are all generic computing components used to implement machine learning models and perform conversion (e.g. the components are merely hardware used to perform the mathematics), thus they do not qualify as a particular machine. Furthermore, the additional limitations are generic computing components (e.g. an array of processing elements, instruction buffers, and SIMD/MIMD instructions) which can be viewed at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)).
The applicant then further argues that operating the GAN accelerator in a frequency domain provides an improvement to a functioning of a computer as disclosed in MPEP 2106.05(a), as the applicant argues that the conversion to frequency domain allows for traditional convolution operations to be bypassed and replaced by simple element-by-element multiplication operations. However, contrary to applicant’s assertions this reflects an improvement to the abstract idea itself (e.g. math) rather than the hardware accelerator because applicant is stating a mathematical operation (convolution operations which are typically performed using multiply-accumulate operations) are replaced with another mathematical operation (element by element multiplication) which is simpler. Thus, the improvement appears to be to the abstract idea and not the functioning of the accelerator itself. MPEP 2106.04 (a)(2)(I) states “…and thus ‘‘the discovery of [a mathematical formula] cannot support a patent unless there is some other inventive concept in its application.’’ Flook, 437 U.S. at 594, 198 USPQ at 199.” While, MPEP 2106.04(1) states “The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions. For example, the mathematical formula in Flook, …Flook, 437 U.S. at 591-92, 198 USPQ2d at 198 ("the novelty of the mathematical algorithm is not a determining factor at all")”. Thus, it is clear from the MPEP that an improvement or new mathematical calculation/formula is still a judicial exception and not an improvement to a functioning of a computer. The instant application appears to be claiming a novel judicial exception that is executed by using a computer (e.g. accelerator) as a tool (MPEP 2106.05(f)) (i.e., the instant application uses known generic or conventional accelerators, hardware, processing elements, buffers and instructions).
Then applicant argues that as in MPEP 2106.04(d) the claims are directed towards an improvement in the functioning of a computer-such as reducing computational load and improving efficiency. However, the examiner respectfully disagrees. MPEP 2106.04(d)(1-2), which details evaluating improvements to the functioning of a computer or technology and states “Conversely, if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology…The application or use of the judicial exception in this manner meaningfully limits the claim by going beyond generally linking the use of the judicial exception to a particular technological environment.” The examiner asserts that the applicant has merely stated in a conclusory manner that replacing convolution operations with element-by-element multiplication operations somehow reduces computational load and improves processing efficiency in a neural network accelerator without any detail necessary to indicate how efficiency is improved. Furthermore, the claims merely generally link the use of the judicial exceptions to generative adversarial networks and none of the claimed limitations meaningfully limit the claims. Thus, the claimed invention does not reflect an improvement.
21. Applicant's arguments filed on 4/30/2026 with regards to the 35 USC 103 rejections have been fully considered but they are not persuasive. Thus, the previous 35 USC 103 rejections regarding claims 1-3, 5-11, 13-20 and 22-24 have been maintained.
22. Applicant first argues the 35 USC 103 rejections on pages 9-10 of the remarks filed on 4/30/2026, in the substance that:
“The cited references fail to teach or suggest a generative model operating in the
frequency domain. The Office acknowledges that FlexiGAN teaches operating in the spatial domain and relies on "Frequency Domain" to teach operating models in the frequency domain. However, Frequency Domain explicitly and exclusively teaches accelerating Convolutional Neural Networks (CNNs) in the frequency domain (see Frequency Domain, Abstract, "accelerator for energy-efficient CNN training"). CNNs are discriminative models. Frequency Domain does not teach or suggest operating a generative model in the frequency domain. Because neither FlexiGAN nor Frequency Domain teaches a generative model operating in the frequency domain, the combination fails to establish a prima facie case of obviousness.”
The examiner respectfully disagrees with the above assertions because the combination of references would disclose utilizing both a generative and discriminative model in a frequency domain. As the applicant asserts above the Frequency Domain discloses accelerating convolutional neural networks in a frequency domain. While, FlexiGAN discloses a generative model and a discriminative model in a spatial domain, and the 103 modification modifies both of the models to operate in a frequency domain. Contrary to applicants’ assertions that CNNs are only discriminative models, CNN’s can also be used to implement generative models. In particular, FlexiGAN explicitly discloses that the generative model is implemented using transposed convolutions, which is still a type of convolution which would be implemented using a CNN (see introduction and sections III and V). Furthermore, pages 71 and 72 of FlexiGAN refer to a DC-GAN which refers to a NPL reference “Unsupervised Representation Learning
with Deep Convolutional Generative Adversarial Networks”, in which a Convolution GAN network is disclosed in which the generative and discriminative models are both CNN’s. Thus, the modification of FlexiGAN with Frequency Domain would disclose implementing CNNs of both the generative and discriminative model in a frequency domain. It would have been obvious to one of ordinary skill in the art because operating a neural network model that performs convolutions in a frequency domain can improve speed, energy efficiency and reduce memory overhead in an accelerator (See Frequency Domain, page 2, section 1 and last page section 6).
23. Applicant then argues the 35 USC 103 rejections on page 10 of the remarks filed on 4/30/2026, in the substance that:
“Furthermore, the proposed combination of FlexiGAN and Frequency Domain would destroy the principle of operation of FlexiGAN. The Office proposes modifying FlexiGAN to operate in the frequency domain based on the teachings of Frequency Domain. However, doing so would destroy the core principle of operation of FlexiGAN. FlexiGAN's entire architecture is explicitly designed to address the inefficiency of "ineffectual operations" (i.e., multiplications with zero) that occur in the spatial domain during transposed convolutions due to zero-insertion (see FlexiGAN, page 2, "Architecture challenges for GAN acceleration"). FlexiGAN solves this by selectively skipping these irregularly inserted zeros. Transforming the input data into the frequency domain, as taught by Frequency Domain, converts sparse data containing zeros into dense data without zeros. Thus, operating in the frequency domain would eliminate the very sparsity that FlexiGAN's architecture is specifically designed to exploit, rendering its specialized hardware completely moot. Under MPEP 2143.01(V), a proposed modification cannot destroy the intended function or principle of operation of the primary reference. Therefore, a person of ordinary skill in the art would not be motivated to combine the teachings of Frequency Domain with FlexiGAN.”
The examiner respectfully disagrees because transforming input data which includes zeros to frequency domain does not eliminate all the zeros as the applicant has indicated above. Thus, operating FlexiGAN in the frequency domain would not destroy the principal operation of FlexiGAN.
Furthermore, even if the conversion would eliminate the zeros in the frequency domain, the principal operation of FlexiGAN as the applicant has indicated above is to address the inefficiencies of performing multiplication operations with zero by skipping zero operations. Thus, if converting the data to a frequency domain removes the extra zero values from the data set, then the inefficient multiplication operations would also be removed. Thus, modifying FlexiGAN to convert input data to a frequency domain as to avoid or prevent zero multiplication operations would not destroy the principal operation of FlexiGAN but is an alternative way of avoiding ineffectual operations, which would provide an improvement of eliminating memory overhead (See Frequency Domain, page 2, section I). Said another away it could be viewed as a simple substitution of one element (avoiding ineffectual operations by removing zero values by converting input data to a frequency domain) for another (avoiding ineffectual operations by skipping zero values) to yield predictable results (avoiding ineffectual operations which include a zero operand) (MPEP 2143, Example B).
24. Applicant then argues the 35 USC 103 rejections on page 10 of the remarks filed on 4/30/2026, in the substance that:
“Additionally, the combination does not appear to describe "wherein one or more of the generative model or the discriminative model include: an array of processing elements, a global instruction buffer coupled to the array of processing elements, wherein the global instruction buffer is to selectively issue single instruction multiple data (SIMD) instructions to columns in the array of processing elements, and a plurality of local instruction buffers coupled to the array of processing elements and the global instruction buffer, wherein the plurality of local instruction buffers are to selectively issue multiple instruction multiple data (MIMD) instructions to rows in the array of processing elements." FlexiGAN can operate in a MIMD-SIMD mode, but that appears to be the opposite of what is claimed.
The examiner respectfully disagrees with the applicants’ assertions above. The applicant has not indicated in what way the functionality of FlexiGAN does not disclose the above claim language. The examiner notes that Fig. 5 of applicant’s disclosure which illustrates the above claimed language is the exact same architecture of FlexiGAN Fig. 5 on page 68. It appears that section VI on pages 68-69 disclose the above claimed functionality.
The examiner is unclear which portions of the reference the applicant disagrees with and requests clarification regarding the above assertions.
Conclusion
25. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
26. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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