DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/08/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites “a dummy line comprising an end directly connected to the power line, and another end that is disconnected such that the dummy line is configured to be a sub-line of the power line”. Applicant’s publication [0240] mentions that DLI may be connected…the power lines PL but it does not mention that an end is directly connected to the power line. Claim 20 recites similar limitations. Other claims are rejected due to the respective dependencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. U.S. Patent Publication No. 2019/0278145 (hereinafter Tanaka) in view of Liu U.S. Patent Publication No. 2010/0320472 (hereinafter Liu) and further in view of Che et al. U.S. Patent Publication No. 2020/0273928 (hereinafter Che).
PNG
media_image1.png
703
750
media_image1.png
Greyscale
Consider claim 1, Tanaka teaches a display device comprising: a display area including a first area, a second area, and a third area in a first direction (Figure 6, display area includes at least three areas), the second area being between the first area and the third area (Figure 6, area (e.g. area corresponding to 15) in between edge areas); first signal lines in the display area and extending in the first direction (Figures 6-7, 11(K)); second signal lines in the display area and extending in a second direction (Figures 6-7, 12); pixels in the display area and connected to the first signal lines and the second signal lines (Figure 10c, pixels connected to lines 11 and 12); a first pad area at a side of the second area in the second direction (Figure 6, first pad area corresponding to 14A or 14B); first lines in the second area and connected from the second area to the first pad area (Figure 6, vertical lines 120P (see also figure 10c)); a power line in the display area and connected to the pixels, the power line being one of a first power configured to supply a first power voltage to pixel circuits of the pixels and a second power line configured to supply a second power voltage to element of the pixels (Figure 10b, VSS or CKA and 151); and bridges in the display area and connecting corresponding ones of the second signal lines in the first area among the second signal lines and the first lines (Figure 6, horizontal lines of 120P (see also figure 10c)), the bridges being disposed across the first area and the second area (Figure 6, horizontal lines of 120P located in the center region and peripheral regions), wherein the first area includes first pixel columns comprising the second signal lines in the first area from among the second signal lines (Figure 10c, columns of pixels in first area (peripheral region) connected to data line 12P), wherein the second area includes second pixel columns comprising others of the second signal lines in the second area from among the second signal lines and first lines from among the first lines (Figure 10c, column of pixels in second area (e.g. region located adjacent to RG) connected to 12Q and 11; and 120P), wherein each of the second pixel columns comprises a number of the first lines corresponding to a ratio of a number of the first pixel columns to a number of the second pixel columns (Figure 10c, vertical line 120P corresponding to a ratio of a number of columns connected to 12P to a number of columns connected to 12Q (e.g. a second pixel column comprises 4/4 first lines), and wherein at least one of the bridges extends parallel to the first direction (Figures 6, 10c shows that horizontal line 120P extents parallel to x-direction, bridge (see annotation above)) on both sides with respect to a connected first line among the first lines (Figure 6 and 10c, connected 1st line (see annotation above)) such that the at least one of the bridges electrically connects one of the second signal lines in the first area and another one of the first lines in the second area (bridge, another one 1st line (see annotation)), the connected first line being electrically connected to at least another one of the bridges and extending along a boundary between the first area and the second area (connected 1st line (See annotation)).
Tanaka does not appear to specifically disclose a dummy line comprising an end directly connected to the power line, and another end that is disconnected such that the dummy line is configured to be a sub-line of the power line.
However, in a related field of endeavor, Liu teaches a pixel electrode structure with high display quality [0003], and further teaches a dummy line comprising an end directly connected to the power line, and another end that is disconnected such that the dummy line is configured to be a sub-line of the power line (Figure 10, dummy portion of 90 comprises an end connected directly to 88 or Vcom (see node connection in the top-center of the figure) and an end portion that is disconnected (e.g. see top-end portion of 90)).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide dummy lines as taught by Liu the common lines 88 are connected to the dummy lines 90 to improve the stability of the second common voltage signal as suggested in [0039].
Takano does not appear to specifically disclose light-emitting element of the pixels.
However, in a related field of endeavor, Che teaches a pixel circuit in figure 2 and further teaches light-emitting element of the pixels (Figures 2-3, pixel 22 and LED 38).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide light-emitting elements as taught by Che with the benefit that each diode has an organic light-emitting emissive layer (sometimes referred to as emissive material or an emissive layer structure) such as emissive layer. Emissive layer is an electroluminescent organic layer that emits light in response to applied current through diode. In a color display, emissive layers in the array of pixels in the display include red emissive layers for emitting red light in red pixels, green emissive layers for emitting green light in green pixels, and blue emissive layers for emitting blue light in blue pixels as suggested in [0057].
Consider claim 2, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches wherein each of the second pixel columns comprises the first lines corresponding to a number proportional to the number of the first pixel columns and a number of the second signal lines in each of the first pixel columns (Figure 10c, vertical line 120P corresponding to a number proportional to number of columns connected to 12P to a number of columns connected to 12Q (e.g. a second pixel column comprises a first line proportional to 4/4)).
Consider claim 3, Tanaka, Liu and Che teach all the limitations of claim 2.
Tanaka does not appear to specifically disclose wherein each of the second pixel columns comprises the number of the first lines inversely proportional to the number of the second pixel columns.
However, Tanaka teaches wherein each of the second pixel columns comprises the number of the first lines with respect to the number of the second pixel columns (Figure 10c, vertical line 120P with respect to number of columns connected to 12Q). In addition, Tanaka teaches in figures 5-6 that the size of the display can be variable as indicated by the dots.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular number of first lines in order to meet design choices or particular display size. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Consider claim 4, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches wherein each of the second pixel columns comprises the same number of the first lines as a number of the second signal lines in each of the first pixel columns (Figure 10c, 4 first lines 120P, 4 first pixel columns 12P), and wherein the second area comprises the same number of the second pixel columns as the number of the first pixel columns in the first area (Figure 10c, 4 columns connected to 12Q and 4 columns connected to 12P).
Consider claim 5, Tanaka, Liu and Che teach all the limitations of claim 1.
Tanaka does not appear to specifically disclose wherein each of the second pixel columns comprises the number of the first lines corresponding to 1/K of a number of the second signal lines in each of the first pixel columns, wherein K is a positive integer greater than or equal to 2, and wherein the second area comprises the number of the second pixel columns corresponding to K times the number of the first pixel columns.
However, Tanaka teaches wherein each of the second pixel columns comprises the number of the first lines corresponding to 1/K of a number of the second signal lines in each of the first pixel columns (Figure 10c, 120P, 12P), and wherein the second area comprises the number of the second pixel columns corresponding to K times the number of the first pixel columns (Figure 10c, 12Q and 12P). In addition, Tanaka teaches in figures 5-6 that the size of the display can be variable as indicated by the dots.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular number of lines in order to meet design choices or particular display size. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Consider claim 6, Tanaka, Liu and Che teach all the limitations of claim 1.
Tanaka teaches wherein a ratio of a number of the second signal lines in each of the first pixel columns to a number of the first lines in each of the second pixel columns is N:M, wherein each of N and M is a positive integer greater than or equal to 2, and wherein a ratio of the number of the first pixel columns to the number of the second pixel columns is M:N.
However, Tanaka teaches wherein a ratio of a number of the second signal lines in each of the first pixel columns to a number of the first lines in each of the second pixel columns is N:M (Figure 10c, 120P, 12P), and wherein a ratio of the number of the first pixel columns to the number of the second pixel columns is M:N (Figure 10c, 12Q and 12P). In addition, Tanaka teaches in figures 5-6 that the size of the display can be variable as indicated by the dots.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular ratio in order to meet design choices or particular display size. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Consider claim 7, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches a pad-free area at one side of the first area in the second direction (Figure 6, pad-free area below 12P).
Consider claim 8, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches wherein the first lines extend in the second direction from the second area and are connected to the first pad area (Figure 6, 120P (see also figure 10c)), and wherein the second signal lines in the second area from among the second signal lines extend in the second direction from the second area and are connected to the first pad area (Figure 6, 12Q (see also figure 10c)).
Consider claim 9, Tanaka, Liu and Che teach all the limitations of claim 8. In addition, Tanaka teaches first pads in the first pad area and electrically connected to the second signal lines in the first area through the first lines and the bridges (Figure 10c, 120P and 12P); and second pads in the first pad area and electrically connected to the second signal lines in the second area (Figure 10c, 12Q (see also figure 6)).
Consider claim 10, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches a second pad area at one side of the third area in the second direction (Figure 6, corresponding RG area), wherein second signal lines in the third area from among the second signal lines extend in the second direction from the third area and are connected to the second pad area (Figure 10a, 12Q and RG).
Consider claim 11, Tanaka, Liu and Che teach all the limitations of claim 10. In addition, Tanaka teaches second lines in the third area, extending in the second direction from the third area, and connected to the second pad area (Figure 7, 151), wherein the second lines are electrically connected to the first signal lines in the third area (Figure 7, 11K and 151).
Consider claim 12, Tanaka, Liu and Che teach all the limitations of claim 11. In addition, Tanaka teaches third pads in the second pad area and electrically connected to the first signal lines through the second lines (Figure 7, 11K and 151); and fourth pads in the second pad area and electrically connected to the second signal lines in the third area (Figure 10a, 12Q (see also figure 6)).
Consider claim 13, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches a fourth area around the third area (Figure 10A, fourth area considered area connected to VSS at the edge of the figure); and a third pad area at one side of the fourth area in the second direction (Figure 10A, corresponding pad (see also figures 6-7)).
Consider claim 14, Tanaka, Liu and Che teach all the limitations of claim 13. In addition, Tanaka teaches a third line in the fourth area, connected to the power line, extending in the second direction from the fourth area, and connected to the third pad area (Figure 10a, VSS); fifth pads in the third pad area and electrically connected to the power line through the third line (Figures 6-7 and figure 10a); and sixth pads in the third pad area and electrically connected to second signal lines in the fourth area from among the second signal lines (Figure 10a, 12Q (see also figures 6-7)).
Consider claim 15, Tanaka, Liu and Che teach all the limitations of claim 14. In addition, Liu teaches a dummy line extending in the second direction and connected to the power line in the display area (Figure 10, Dummy data line 90 and 88).
Consider claim 16, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches wherein the first lines are respectively between ones of the pixel circuits of ones of the pixels in ones of the second pixel columns adjacent to each other in the first direction (Figure 10c, vertical part of 120P and pixels), or around others of the pixel circuits of others of the pixels in a first or last one of the second pixel columns of the second area.
Consider claim 17, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches wherein the bridges are between two pixel rows adjacent to each other in the second direction (Figure 10c, horizontal part of 120P).
Consider claim 18, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches wherein the first area is at both edges of the display area in the first direction (Figure 6, area corresponding to 12P), wherein the second area is directly adjacent to the first area in the first direction (Figure 6, area adjacent to the area corresponding to 12P), and wherein the third area is at a center of the display area in the first direction (Figure 6, RG).
Consider claim 19, Tanaka, Liu and Che teach all the limitations of claim 1. In addition, Tanaka teaches a pad area including the first pad area and a second pad area adjacent to the first pad area and at one side of the third area in the second direction (Figure 6, pad corresponding to 14 and 15); and a pad-free area at both sides of the pad area in the first direction and at one side of the first area in the second direction (Figure 6, pad-free below the area corresponding to 12P).
Consider claim 20, Tanaka teaches a display device comprising: a display panel comprising blocks arranged in a first direction (Figure 6, blocks corresponding to 14a-b); and driving circuits on pad areas of each of the blocks and arranged along the first direction (Figure 6, 14-15), wherein each of the blocks comprises: a display area including a first area and a second area along the first direction (Figure 6, area corresponding to 12P and 12Q), and comprising first signal lines extending in the first direction (Figure 7, 11k), second signal lines extending in a second direction (Figure 6, 12), and pixels connected to the first signal lines and the second signal lines (Figure 10c, pixels connected to 11 and 12); a pad-free area and a pad area at one side of the first area and the second area in the second direction, respectively (Figure 6); first lines in the second area and connected from the second area to the pad area (Figure 6, 120P (see also figure 10c)); a power line in the display area and connected to the pixels, the power line being one of a first power configured to supply a first power voltage to pixel circuits of the pixels and a second power line configured to supply a second power voltage to element of the pixels (Figure 10b, VSS or CKA and 151); and bridges connecting corresponding ones of the second signal lines in the first area from among the second signal lines to the first lines, the bridges being disposed across the first area and the second area (Figure 6, 120P and 12P), wherein the first area includes first pixel columns comprising the second signal lines in the first area from among the second signal lines (Figure 10c, 12P), wherein the second area includes second pixel columns comprising others of the second signal lines in the second area and corresponding ones of the first lines (Figure 10c, 12Q and 120P), wherein each of the second pixel columns comprises a number of the first lines corresponding to a ratio of a number of the first pixel columns to a number of the second pixel columns (Figure 10c, vertical line 120P corresponding to a ratio of a number of columns connected to 12P to a number of columns connected to 12Q (e.g. a second pixel column comprises 4/4 first lines), and wherein at least one of the bridges extends parallel to the first direction (Figures 6, 10c shows that horizontal line 120P extents parallel to x-direction, bridge (see annotation above)) on both sides with respect to a connected first line among the first lines (Figure 6 and 10c, connected 1st line (see annotation above)) such that the at least one of the bridges electrically connects one of the second signal lines in the first area and another one of the first lines in the second area (bridge, another one 1st line (see annotation)), the connected first line being electrically connected to at least another one of the bridges and extending along a boundary between the first area and the second area (connected 1st line (See annotation)).
Tanaka does not appear to specifically disclose a dummy line comprising an end directly connected to the power line, and another end that is disconnected such that the dummy line is configured to be a sub-line of the power line.
However, in a related field of endeavor, Liu teaches a pixel electrode structure with high display quality [0003], and further teaches a dummy line comprising an end directly connected to the power line, and another end that is disconnected such that the dummy line is configured to be a sub-line of the power line (Figure 10, dummy portion of 90 comprises an end connected directly to 88 or Vcom (see node connection in the top-center of the figure) and an end portion that is disconnected (e.g. see top-end portion of 90)).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide dummy lines as taught by Liu the common lines 88 are connected to the dummy lines 90 to improve the stability of the second common voltage signal as suggested in [0039].
Takano does not appear to specifically disclose light-emitting element of the pixels.
However, in a related field of endeavor, Che teaches a pixel circuit in figure 2 and further teaches light-emitting element of the pixels (Figures 2-3, pixel 22 and LED 38).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide light-emitting elements as taught by Che with the benefit that each diode has an organic light-emitting emissive layer (sometimes referred to as emissive material or an emissive layer structure) such as emissive layer. Emissive layer is an electroluminescent organic layer that emits light in response to applied current through diode. In a color display, emissive layers in the array of pixels in the display include red emissive layers for emitting red light in red pixels, green emissive layers for emitting green light in green pixels, and blue emissive layers for emitting blue light in blue pixels as suggested in [0057].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Liu and Che).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO W FLORES whose telephone number is (571)272-5512. The examiner can normally be reached Monday-Friday, 7am-4pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMR A AWAD can be reached at (571)272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
Prosecution Insights