Prosecution Insights
Last updated: October 02, 2026
Application No. 18/058,200

ELECTRICAL CIRCUIT DEVICE AND MOTOR VEHICLE

Final Rejection §103
Filed
Nov 22, 2022
Priority
Nov 24, 2021 — DE 102021130733.3
Examiner
BUTTAR, MANDEEP S
Art Unit
2835
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Audi AG
OA Round
6 (Final)
80%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
441 granted / 553 resolved
+11.7% vs TC avg
Strong +16% interview lift
Without
With
+16.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
15 currently pending
Career history
563
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
58.1%
+18.1% vs TC avg
§102
26.6%
-13.4% vs TC avg
§112
10.6%
-29.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicants’ arguments with respect to claim 1 have been considered, but are moot in light of the new ground of rejection set forth below. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3, 5, and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over YOHEI (JP 7319945 B2) in view of Yoshino (U.S 2010/0321889 A1) and, further, in view of XU (U.S 2019/0372063 A1). In regards to Claim 1, Yohei discloses an electrical circuit device (Fig.3, #1), comprising: a power electronics circuit (Fig.1, #3) with at least one power electronics module (Fig.3, #4a-4c is a power module #4a-4c), a filter device (Fig.3, #50 in conjunction with #20), a heat sink (Fig.3, #7 in conjunction with #60 which is integral with said heat sink, see “The first partition wall 60 may be formed integrally with the metal case 7”), a connector (Fig.2, #6 is the connector) configured to be coupled to a device external to the electrical circuit device (Fig.1-3, #6 is connected to an external DC source), and two busbars (Fig.3, #12a and #12b) connecting the connector to the power electronics circuit (Fig.3), wherein the two busbars each include an elongated section between opposing ends of each respective busbar, the elongated sections of each of the two busbars being parallel to one another (Fig.3, #12a and #12b are elongated busbars being parallel to one another), wherein the two busbars are arranged on a same end of the electrical circuit device (Fig.3, #12a/12b are on the same end of the device #1) wherein the elongated sections of the two busbars are arranged adjacent to one another on the heat sink (Fig.3, #12a/12b are adjacent to one another and on top of #7 in conjunction with #60) or one above the other on the heat sink, wherein the filter device is at least partially coupled to one of the two busbars (Fig.3, #50 is connected to #12 through #11), wherein the power electronics module and at least a portion of at least one of the two busbars are thermally connected to the heat sink (Fig.3-4, #6 and #12a/12b are thermally connected to #7 in conjunction with #60 and #11) and wherein at least one of the two busbars is in thermal engagement with a surface of the heat sink (Fig.3-4, #12a/12b are thermally connected to a surface of #7 in conjunction with #60 and #11, see “The second DC bus bar 11 is in contact with the first partition wall 60 via the second thermally conductive member 62”). Yohei fails to explicitly disclose: A busbar is in direct thermal engagement with a surface of the heat sink and an intermediate layer disposed between the two busbars such that each of the two busbars contact the intermediate layer However, Yoshino discloses: A busbar (Fig.16, #136) is in direct thermal engagement with a surface of the heat sink (Fig.16, #16 is in direct thermal engagement #40, see paragraph [0024 & 0094], as such the office notes that with the combination of Yohei in view of Yoshino, the bus bars that are thermally engaged with the heatsink (as taught by Yohei) would be modified to be directly in contact with a surface of said heat sink (as taught by Yoshino) to dissipate heat carried via the bus bars). Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the bus bars that are thermally engaged with the heatsink (as taught by Yohei) to be directly in contact with a surface of said heat sink (as taught by Yoshino) to dissipate heat carried via the bus bars. By directly contacting the bus bars with the heatsink, would minimize thermal resistance and creates a simplified design using less components/steps. Additionally, MPEP 2143.02 (I) notes that all the claimed elements were known in the prior art and one of ordinary skill in the art at the time of the invention could have combined and/or modified the elements as claimed by known methods with no change in their respective functions, and the combination and/or modification would have yielded predictable results to one of ordinary skill in the art at the time of the invention; wherein there is no criticality established within the instant specification (See page 4, lines 13-19, which discloses the busbars can directly or indirectly contact the heat sink). As such, by directly connecting the busbar to the heatsink surface would be within the purview of one of ordinary skill in the art at the time of the invention was filed as Yoshino discloses a busbar directly in contact to a heatsink to dissipate heat carried via the busbars (See MPEP 2143.02, citing, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007)). Furthermore, Yohei in view of Yoshino fail to disclose: an intermediate layer disposed between the two busbars such that each of the two busbars contact the intermediate layer. However, XU discloses: An intermediate layer (Fig.2a, #206, which can be a case and/or molding made of plastic, see paragraph [0026-0028]) disposed between the two busbars (Fig.2a, #206 is configured to spatially positions of the bus bars #208/#210) such that each of the two busbars contact the intermediate layer (Fig.2a, portion of #206 is between the two bus bars #208a and #208b, as such the office notes that with the combination of Yohei in view of Yoshino and XU, the housing containing the busbars spaced apart extending parallel to one another on the same side of the device (as taught by Yohei) would be modified to place intermediate layer/portion between the bus bars (as taught by XU) to isolated said bars from one another). Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the housing containing the busbars spaced apart extending parallel to one another on the same side of the device (as taught by Yohei) would be modified to place intermediate layer/portion between the bus bars (as taught by XU) to isolated said bars from one another. By including an insulating intermediate layer between said busbars, would prevent accidentally shorts which could damage the inverter. In regards to Claim 2, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 1, wherein the filter device has at least one capacitor (Yohei Fig.3, #50 is a smoothing capacitor) connected to at least one of the two busbars (Yohei Fig.3, #50 is connected to #11) and/or at least one inductance element coupled to at least one of the two busbars (Yohei Fig.3, #26). In regards to Claim 3, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 2, wherein the at least one inductance element is a ferrite core (Yohei Fig.3, #26 is a ferrite core (noise elimination core) to suppress EMI). In regards to Claim 5, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 1, wherein the filter device comprises an inductance element arranged at the connector and/or surrounding the connector (Yohei, Fig.3, #26 is arranged at the connector in the back). In regards to Claim 9, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 1, wherein the heat sink has one or more cooling channels extending inside the heat sink (Yohei, Fig.4, #8 is a coolant channel extending in #7). In regards to Claim 10, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 1, wherein the power electronics circuit is configured as an inverter (Yohei Fig.1-4, #1 is an inverter, see technical field and background art). In regards to Claim 11, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 1, wherein the power electronics circuit is configured as a multiphase pulse inverter (Yohei, Fig.3, #12a-12c, each represents a different phase for AC power when converting from DC power, see “The power semiconductor circuit section 4 includes power semiconductor modules 4a, 4b, and 4c. Power semiconductor module 4 a is connected to the U phase of motor generator 5 . Power semiconductor module 4 b is connected to the V phase of motor generator 5 . Power semiconductor module 4 c is connected to the W phase of motor generator 5”). In regards to Claim 12, Yohei in view of Yoshino and XU discloses a motor vehicle comprising an electrical circuit device according to claim 1(Yoshino, Paragraph [0048], discloses the converter can be installed within a vehicle). In regards to Claim 13, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 1, wherein the two busbars terminate at the connector at a common connector location (Yohei, Fig.2-3, #10/11 terminate at the common connector location located behind #6). Claim 3 is rejected in the alternative under 35 U.S.C. 103 as being unpatentable over YOHEI (JP 7319945 B2) in view of Yoshino (U.S 2010/0321889 A1), XU (U.S 2019/0372063 A1), and further, in view of Krause (U.S 2019/0036506 A1). In regards to Claim 3, Yohei in view of Yoshino and XU disclose the electrical circuit device according to claim 2, wherein the at least one inductance element (Yohei Fig.3, #26) having a core (Yohei Fig.3, #26 (noise elimination core) to suppress EMI which comprise inherent physical characteristic having a wire wrapped around some magnetic core). Yohei in view of Yoshino and XU fail to explicitly disclose: The inductor having a ferrite core. However, Krause discloses: The inductor having a ferrite core (Fig.2, #203a-c are inductors having a ferrite core, see paragraph [0059], as such the office notes that with the combination of Yohei in view of Yoshino, XU, and Krause, the electrical circuit device having an inductor (as taught by Yohei) would be modified such that the inductor has a ferrite core (as taught by Krause) to create a magnetic field). Therefore, MPEP 2143.02 (I) notes that all the claimed elements were known in the prior art and one of ordinary skill in the art at the time of the invention could have combined and/or modified the elements as claimed by known methods with no change in their respective functions, and the combination and/or modification would have yielded predictable results to one of ordinary skill in the art at the time of the invention. As such, by including an inductor having a ferrite core would be within the purview of one of ordinary skill in the art at the time of the invention was filed as Yohei discloses a noise elimination core in line with the busbars. By including an inductor having a ferrite core would provide a high magnetic permeability to the coil, thus increasing the magnetic field and inductance (See MPEP 2143.02, citing, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007)). Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over YOHEI (JP 7319945 B2) in view of Yoshino (U.S 2010/0321889 A1), XU (U.S 2019/0372063 A1), and further, in view of Rigbers (U.S 2022/0304184). In regards to Claim 4, Yohei in view of Yoshino and XU discloses the electrical circuit device according to claim 2. Yohei in view of Yoshino and XU fail to disclose: Wherein the filter device comprises at least one common mode choke, at least one common mode capacitor and/or at least one differential mode capacitor. However, Rigbers discloses: Wherein the filter device comprises at least one common mode choke (Rigbers Fig.1 and paragraph [0031]), at least one common mode capacitor and/or at least one differential mode capacitor (as such the office notes that with the combination of Yohei in view of Yoshino, XU, and Rigbers, the filter device comprising a capacitor (as taught by Yohei) would be modified to be a common node choke (as taught by Rigbers) to help block high frequency signals). Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the modified the filter device comprising a capacitor (as taught by Yohei) to further include a common node choke (as taught by Rigbers) to help block any high frequency signals. By including an inductor in conjunction with a common node choke, would help reduce electrical noise, frequency noise, and switching. In regards to Claim 8, Yohei in view of Yoshino and XU disclose the electrical circuit device according to claim 1. Yohei in view of Yoshino and XU fail to disclose: Wherein the power electronics circuit comprises a direct current link capacitor, wherein the two busbars are connected to the direct current link capacitor. However, Rigbers discloses: wherein the power electronics circuit comprises a direct current link capacitor (abstract, which discloses #21 are link capacitors), wherein the busbars are connected to the direct current link capacitor (Fig.1, #50 are both electrically connected to #21, as such the office notes that with the combination of Yohei in view of Yoshino, XU, and Rigbers, the power electronics circuit (as taught by Yohei) would be modified to include a direct current link capacitor connected to two busbars (as taught by Rigbers) to help create an EMC filter for the converter). Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the power electronics circuit (as taught by Yohei) to include a direct current link capacitor (as taught by Rigbers) to help create and EMC filter for the converter. By including a direct current link capacitor within the device, would prevent unwanted noise from interrupting the AC/DC conversions and improve efficiency by stabilizing voltage to minimize energy losses. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over YOHEI (JP 7319945 B2) in view of Yoshino (U.S 2010/0321889 A1), XU (U.S 2019/0372063 A1), and further, in view of Boehmer (U.S 2022/0345027 A1). In regards to Claim 6, Yohei in view of Yoshino and XU disclose the electrical circuit device according to claim 1. Yohei in view of Yoshino and XU fail to disclose: Wherein the busbar is thermally bonded to the heat sink over at least 50% of its length. However, Boehmer discloses: Wherein the busbar (Fig.6, #DCS +/-) is thermally bonded (paragraph [0087], using thermally conductive thermosetting composition to bond said busbar) to the heat sink (Fig.6, #KK) over at least 50% of its length (Fig.6, which discloses the busbar having at least 50% over the heatsink #KK, as such the office notes that with the combination of Yohei in view of Yoshino, XU, and Boehmer, the busbars (as taught by Yohei) would be modified to be thermally bonded to the heatsink (as taught by Boehmer) such that its bonded over at least 50% of length to dissipate heat). Therefore, it would of have been obvious to one of ordinary skill in the art at the time the application was filed to have modified the busbars (as taught by Yohei) to be thermally bonded to the heatsink (as taught by Boehmer) such that it’s bonded over at least 50% of length to dissipate heat. By bonding the busbars to the heatsink, would help dissipate the heat generated by the large current flowing through said busbar, thus ensuring the longevity of the device. Conclusion Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANDEEP S BUTTAR whose telephone number is (571)272-4768. The examiner can normally be reached 7:00AM-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MANDEEP S BUTTAR/Primary Examiner, Art Unit 2841
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Prosecution Timeline

Show 7 earlier events
Jun 10, 2025
Non-Final Rejection mailed — §103
Jul 18, 2025
Non-Final Rejection mailed — §103
Oct 10, 2025
Response Filed
Dec 18, 2025
Non-Final Rejection mailed — §103
Mar 17, 2026
Applicant Interview (Telephonic)
Mar 18, 2026
Examiner Interview Summary
May 18, 2026
Response Filed
Sep 01, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

7-8
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+16.0%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

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