DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on October 3, 2025. Claims 1, 5-7 and 9 have been amended. Claim 15 has been added. Claims 2 and 11 have been canceled. Claims 9-10 and 12-14 have been withdrawn. Currently, claims 1, 3-8, and 15 are pending.
Applicant’s amendment to claims 5 and 7 successfully overcomes the objections of claims 5 and 7 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed October 3, 2025, have been fully considered but they are not persuasive.
The Applicants argue, on pages 8-9:
However, it is unclear how such a modification could be accomplished or even suggested
from the cited combination.
Hioka teaches "a magnetic flux converging plate 10 mounted on the back surface of the
semiconductor substrate 1 through intermediation of the adhesive layer 40" (col. 3, ll. 1-
7). As illustrated in FIG. 4A of Hioka, an adhesive (adhesive layer) 40 is applied onto the
magnetic flux converging plate 10 formed on the plating substrate 30 in the steps
illustrated in FIG. 3A to FIG. 3E (col 5, ll. 1-7). The adhesive 40 is required to have
stronger adhesiveness to the semiconductor substrate 1 than to the base conductive layer
11 or the plating substrate 30. According to Hioka, when the annealing treatment is
performed, the magnetic flux converging plate 10 may warp, but the semiconductor
substrate 1 adheres to the magnetic flux converging plate 10 through intermediation of
the adhesive 40 (col. 5, ll. 14-23).
In contrast, George teaches to apply an interlayer between a substrate and a coating,
which may be polymeric or inorganic material such as metal oxide (para. [0009]). As
such, it is unclear how one skilled in the art would be led to incorporate the interlayer of
George in Hioka, as Hioka does not teach to apply a coating on a substrate but to adhere
a plate to a semiconductor and there is no reason in Hioka for a coating to reduce gas
diffusion as in George (George, para. [0006-7]).
The Examiner responds:
The Examiner respectfully disagrees. First, George does not limit itself to only being applied to coatings reducing gas diffusion. George teaches that layer 104 can be a coating but can also generally be a layer ([0029]). Also, George teaches that “[s]tructures including layers of different coefficients of thermal expansion may be used for a variety of purposes” ([0005]) and that “[t]he present invention generally relates to multi-layer structures that include an interlayer to reduce stress in layers adjacent the interlayer that would otherwise occur, because of a mismatch between the coefficients of thermal expansion of the layers that are adjacent the interlayer” ([0008]).
Second, an ordinary artisan would be motivated to look to George because of a problem described in Hioka. Hioka describes the problem that “large stress is generated on the silicon substrate because the thermal expansion coefficients of a metal magnetic body and the silicon substrate or the protective film made of polyimide or other materials are significantly different from each other. The stress affects the magnetic sensor” (col. 1, lines 50-60). While Hioka addresses this problem by alleviating the effects of the stress rather than alleviating the stress itself, an ordinary artisan can look to George to alleviate the stress itself. While Hioka does not use George’s specific example for reducing gas diffusion, a person having ordinary skill in the art can look to George for its general teaching of using an interlayer in multi-layer structures to reduce stress in adjacent layers.
The Applicants argue:
Further, under no circumstances would one skilled in the art replace the adhesive layer of
Hioka with the interlayer of George, as such would run contrary to the purpose of the
adhesive and allow the plate to detach from the substrate. While the rejection asserts that
the use of an interlayer would be expected to form a multi-layer structure including an
interlayer to relieve stress in the structure, this rationale expands the teachings of George
into an unsupported assumption that the interlayer inherently relieves stress and ignores
the differences in materials, components and objectives of the respective references.
Again, there is no teaching in the cited references that could lead one skilled in the art to
the addition of the interlayer of George in the adhesive connection of Hioka, as there is
no reasonable expectation of success or reasoned rationale for the proposed combination.
The Examiner responds:
The Examiner respectfully disagrees. First, replacing the adhesive layer of Hioka with the interlayer of George does not render the sensor as a whole of Hioka unsatisfactory for its intended purpose (see MPEP 2143.01). The sensor of Hioka modified by George can still work as long as it is not moved around to the point that the plate detaches from the substrate. Hioka also does not teach away from other ways of adhering the plate to the substrate.
Second, George is not used to teach that the interlayer inherently relieves stress. As described in the previous Office Action and in the rejection below, George teaches an organic-inorganic hybrid polymer compound (106) on the first component (102) (see Fig. 1), for minimizing stress caused by mismatch between the first (102) and second components (104, Fig. 1, [0031]) ([0032]). To clarify further, George explains, in [0031]-[0032], that the interlayer 106 relieves stress by having a coefficient of thermal expansion (CTE) between the respective coefficients of thermal expansion of substrate 102 and layer 104. A person having ordinary skill in the art can use this general teaching and apply this to Hioka, even though layer 104 of George is a metal oxide while Hioka’s layer is a metal plate. Metals generally have higher CTEs than metal oxides (both are higher than silicon’s CTE of 2.6 x 10-6/°C), so it would be easier for the ordinary artisan to find an interlayer having a CTE between the CTEs of Hioka’s layers 1 and 10.
Third, the reasonable expectation of success requirement refers to "the likelihood of success" in combining or modifying prior art disclosures to meet the limitations of the claimed invention. See MPEP 2143.02; see also Elekta Ltd. v. ZAP Surgical Sys., Inc., 81 F.4th 1368, 1375, 2023 USPQ2d 1100 (Fed. Cir. 2023) and Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359, 1367, 119 USPQ2d 1171, 1176 (Fed. Cir. 2016). There is a reasonable likelihood that the limitations of Claim 1 is met by modifying Hioka with George’s interlayer because George’s interlayer has a CTE between the CTEs of Hioka’s layers 1 and 10.
The Applicants argue:
In particular, it is noted that Hioka already asserts to solve the problem of stresses
between Hall elements and an IMC by arranging the Hall elements on one face of the
substrate and the IMC at the opposite face with epoxy adhesive. Even if one skilled in the
art would search for improving the solution of Hioka, there is no reason to consider
George.
The Examiner responds:
The Examiner respectfully disagrees. As already described above, Hioka addresses this problem of stresses by alleviating the effects of the stress rather than directly alleviating the stress itself. An ordinary artisan would consider George to directly alleviate the stress by using its general teaching of using an interlayer in multi-layer structures to reduce stress in adjacent layers.
The Applicants argue:
As discussed previously, George is directed to chemical coating by decomposition of
gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition processes. However, the technique is applied to
multilayers for OLED panels. George never mentions sensors or related components, but
instead seeks to improve attachment of a moisture (oxide or nitride) barrier to the
protected underlying protected polymer layer.
The Examiner responds:
The Examiner respectfully disagrees. While George does not mention sensors, George is in a similar field of endeavor as Hioka because both are in the field of multilayer circuits. George also states that “[s]tructures including layers of different coefficients of thermal expansion may be used for a variety of purposes” ([0005]) and that “[t]he present invention generally relates to multi-layer structures that include an interlayer to reduce stress in layers adjacent the interlayer that would otherwise occur, because of a mismatch between the coefficients of thermal expansion of the layers that are adjacent the interlayer” ([0008], emphasis added).
The Applicants argue:
In contrast to the cited prior art, the current disclosure teaches in at least para. [13] that:
[13] It is an advantage of embodiments of the present invention that a buffer
layer compensates for stress between two adjacent different materials,
reducing for example thermal stress and potential delamination. This
facilitates manufacturing steps including high-temperature deposition, such
as ALD, for providing the second component, and limits build-up of stresses
from other high-temperature processes like molding. In sensing devices,
stress reduction provides also signal drift reduction.
No comparable arrangement or advantage is considered or otherwise suggested in the
combination of Hioka and George.
The Examiner responds:
The Examiner respectfully disagrees. As set forth in the previous Office Action and in the rejection below, George teaches that the advantage of interlayer 106 is minimizing stress caused by mismatch between the first (102) and second components (104, Fig. 1, [0031]) ([0032]), in order to form “[a] multi-layer structure including an interlayer to relieve stress in the structure” (Abstract). George also shows that layer 104 is deposited using ALD techniques ([0031]). Finally, regarding the advantage of “signal drift reduction,” the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). The advantage of “signal drift reduction” would flow naturally from an ordinary artisan modifying the sensor of Hioka with the providing an interlayer by MLD of George, in order to form a multi-layer structure including an interlayer to relieve stress in the structure.
Thus, Hioka in view of George renders obvious the limitations of amended claim 1. As a result, the rejection of claim 1 and its dependent claims is maintained.
All other arguments have been fully addressed in prior Office Actions or in the rejections set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, 7-8, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hioka et al. (US 10429453) in view of George et al. (US 20150072119).
Regarding claim 1, Hioka teaches a method of manufacturing an integrated sensor (col. 1, lines 10-20), the method comprising providing a first component being a substrate (1, Fig. 1) comprising a first material being a semiconductor (col. 1, lines 60-67; semiconductor substrate),
providing a second component (10, Fig. 1) over the first component (1) (see Fig. 1), the second component comprising a second material different from the first, the second material being a metal or molding material (col. 3, lines 20-35; col. 1, lines 50-60; magnetic flux converging plate made of metal), and
providing an interlayer (40; col. 3, lines 1-5) of a third material (col. 5, lines 5-10) on the first component (1) (see Fig. 1).
Hioka does not explicitly teach providing an interlayer by molecular layer deposition of a third material being an organic-inorganic hybrid polymer compound on the first component, for minimizing stress caused by mismatch between the first and second components.
In a similar field of endeavor, George teaches, in Fig. 1, providing an interlayer by molecular layer deposition of a third material being an organic-inorganic hybrid polymer compound (106, [0033]) on the first component (102; [0029]-[0030]) (see Fig. 1), for minimizing stress caused by mismatch between the first (102) and second components (104, Fig. 1, [0031]) ([0032]), in order to form “[a] multi-layer structure including an interlayer to relieve stress in the structure” (Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a sensor of Hioka with the providing an interlayer by MLD of George, in order to form a multi-layer structure including an interlayer to relieve stress in the structure.
Regarding claim 3, Hioka in view of George teaches the limitations of claim 1. Hioka further teaches, in Fig. 1, that providing the first component comprises providing a semiconductor substrate (1) including integrated circuitry (col. 3, line 60 – col. 4, line 5).
Regarding claim 4, Hioka in view of George teaches the limitations of claim 3. Hioka further teaches, in Fig. 1, that providing a second component comprises forming a metallic layer (10; col. 3, lines 20-35; col. 1, lines 50-60; metal magnetic body) over the semiconductor substrate (1) (see Fig. 1).
Regarding claim 5, Hioka in view of George teaches the limitations of claim 4. Hioka further teaches that the forming a metallic layer (10) comprises forming Hall effect plates or integrated magnetic concentrators (col. 3, lines 20-35; col. 1, lines 50-60; magnetic flux converging plate).
Regarding claim 7, Hioka in view of George teaches the limitations of claim 1. George further teaches, in Fig. 1, that the providing an interlayer (106) comprises providing a conformal interlayer (see Fig. 1 how interlayer 106 conforms to the top surface of the first component 102 and the bottom surface of the second component 104).
Regarding claim 8, Hioka in view of George teaches the limitations of claim 1. George further teaches that providing the interlayer (106) comprises providing alucone ([0033]).
Regarding claim 15, Hioka in view of George teaches the limitations of claim 1. George further teaches that the providing an interlayer (106) comprises providing an interlayer (200 nm, [0057]) 125 times thinner than the first component (102) ([0037]; 25 μm).
However, Hioka in view of George does not explicitly teach that the providing an interlayer comprises providing an interlayer 100 times thinner than the first component and/or the second component. Nonetheless, the skilled artisan would know too that the thicknesses of the layers would impact the amount of stress relieved (George, [0034]).
The specific claimed thicknesses, absent any criticality, is only considered to be the “optimum” thicknesses disclosed by Hioka in view of George that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired stress amount, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an interlayer being 100 times thinner than the first component and/or the second component is used, as already suggested by Hioka in view of George.
Since the applicant has not established the criticality (see next paragraph) of the thicknesses stated and since these thicknesses are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Hioka in view of George.
Please note that the specification contains no disclosure of either the critical nature of the claimed lengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hioka et al. (US 10429453) in view of George et al. (US 20150072119), and further in view of Vangerven et al. (US 20200300898).
Regarding claim 6, Hioka in view of George teaches the limitations of claim 1. Hioka in view of George does not explicitly teach that providing the second component comprises packaging the integrated sensor by providing a molding material.
In a similar field of endeavor, Vangerven teaches that providing the second component comprises packaging the integrated sensor by providing a molding material ([0076], [0084]), for the purpose of providing “high signal-to-noise (S/R) ratio” ([0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a sensor of Hioka in view of George with the providing a molding material of Vangerven, for the purpose of providing high signal-to-noise (S/R) ratio.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893