Attorney’s Docket Number: GFSG2022048-US-NP
Filing Date: 11/28/2022
Inventors: Rajoo et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed on 4/21/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendments filed on 4/21/2026, responding to the Office action mailed 2/27/2026,
has been entered. Applicant amended claims 8, 16, and 21. The present Office action is made with all
the suggested amendments being fully considered.
Response to Amendments/Arguments
Applicant’s amendments have overcome the claim rejections of 35 U.S.C. 112 and 35 U.S.C. 103 as previously formulated in the Non-Final Office actioned mailed on 2/27/2026. Accordingly, the claim rejections of 35 U.S.C. 112 and 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 8-11, 13-18, and 20-23. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Election/Restrictions
Applicant’s request for rejoinder is dependent on the allowance of claims 8-11, 13-18, and 20-23, and since there are new rejections as necessitated by the amendments, claims 1-2 and 4-7 are not in condition for rejoinder. Accordingly, pending in this application are claims 8-11, 13-18, and 20-23.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chockalingam (US 20210134742 A1) in view of Kellam (US 5580668 A) further in view of Goh (US 9972589 B1) and Cheng (US 11024593 B2).
Regarding claim 8, Chockalingam (see, e.g., figs. 2B-2F) shows most aspects of the instant invention including a method comprising:
Exposing an upper surface (see, e.g., fig. 2B) of a copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”);
Forming a conductive layer (e.g., planar barrier 218, see fig. 2E) directly on the exposed upper surface of the copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”), the conductive layer (e.g., planar barrier 218) consisting of a palladium layer (see, e.g., paragraph 56 “In some embodiments of the disclosure, the planar barrier 218 may include palladium…”);
Forming a copper interconnect (e.g., bonding wire 220, see fig. 2F + paragraph 59 “In this embodiment of the disclosure, the bonding wire is preferably copper”) directly on the conductive layer (e.g., planar barrier 218).
Chockalingam (see, e.g., figs. 2B-2F), however, fails to show annealing after forming the conductive layer to convert the conductive layer into a stack including the palladium layer and a copper palladium alloy layer below the palladium layer.
Kellam (see, e.g., figs. 1A-1C or 2A-2C), in a similar device to Chockalingam, teaches annealing (see, e.g., paragraph 7) after forming a conductive layer (e.g., palladium film 12 + aluminum 13) to convert the conductive layer (e.g., palladium film 12 + aluminum 13) into a stack including a palladium layer (e.g., palladium film 12) and an aluminum palladium alloy layer (e.g., aluminum alloy film 14) over the palladium layer (e.g., palladium film 12).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the annealing step of Kellam on the palladium layer of Chockalingam, in order to diversify the materials and improve the electrical properties of the conductive layer within the device.
Chockalingam in view of Kellam, however, fails to teach the post-annealed stack includes a copper palladium alloy, or that the copper palladium alloy is below the palladium layer.
Goh (see, e.g., fig. 2A), in a similar device to Chockalingam in view of Kellam, teaches an alloy (see, e.g., paragraph 57 “…combination of copper…aluminum, palladium…and/or alloys thereof”) of copper palladium as an alternative to aluminum palladium.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of
filing the invention to include the conductive alloy of copper palladium within the conductive stack of Chockalingam in view of Kellam, because many are recognized in the semiconductor art for their usage in conductive materials, as taught by Goh, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). In addition, note that Chockalingam in view of Kellam possesses a palladium-copper interface pre-annealing step.
Chockalingam in view of Kellam further in view of Goh, however, fails to explicitly teach the copper palladium alloy is below the palladium layer.
Cheng (see, e.g., fig. 8), in a similar device to Chockalingam in view of Kellam further in view of Goh, teaches a conductive layer comprising a copper layer (e.g., copper-containing layer 60) below a palladium layer (e.g., metal cap layer 62 + paragraph 36 “…palladium containing layer”).
Accordingly, it would have been obvious to one or ordinary skill in the art at the time of filing the invention to include the palladium over copper configuration of Cheng within the conductive layer of Chockalingam in view of Kellam further in view of Goh pre-annealing step, in order to achieve the expected result of providing a distinct palladium and copper profile within the bonding area during treatment and fabrication of the device. Also note that the annealing of Kellam is performed on an aluminum film over a palladium film, resulting in an aluminum alloy film over the palladium film post-annealing process, hence the annealing process carried out on the palladium over copper configuration of Chockalingam in view of Kellam further in view of Goh and Cheng would result in a palladium film over a copper palladium alloy (note the interface between the palladium and copper). In addition, note the limited arrangements possible between the palladium and copper layer within the conductive layer of Chockalingam in view of Kellam further in view of Goh and Cheng, i.e., palladium-over-copper or copper-over-palladium and since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as long as the palladium and copper are configured uniformly and within the conductive bonding area, as already suggested by Cheng. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding claim 9, Kellam (see, e.g., table 1) teaches a stack (e.g., palladium + aluminum) has a thickness between 15 to 100 nanometers (see, e.g., paragraph 13… “…10 nm palladium, then, finally, 20 nm aluminum”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the 30 nm stack configuration of Kellam within the stack of Chockalingam in view of Kellam further in view of Goh and Cheng, in order to achieve the expected result of limiting the cost of material fabrication while manufacturing the device, while simultaneously providing a distinct palladium and aluminum/copper (note the alternative materials to aluminum as argued earlier) profile as desired.
Regarding claim 14, Chockalingam (see, e.g., figs. 2B-2F) shows forming the palladium layer (e.g., planar barrier 218 + paragraph 56 “In some embodiments of the disclosure, the planar barrier 218 may include palladium…”) includes electroless depositing the palladium layer (see, e.g., paragraph 55 “The planar barrier 218 may be preferably deposited using electroless plating…”).
Regarding claim 15, Chockalingam (see, e.g., figs. 2B-2F) shows the copper interconnect (e.g., bonding wire 220, see fig. 2F + paragraph 59 “In this embodiment of the disclosure, the bonding wire is preferably copper”) forming includes forming one of: forming a copper wire bond (see, e.g., paragraphs 58 and 59) on the copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”), or forming both a copper redistribution layer (RDL) and a solder ball on the copper RDL.
Regarding claim 16, Chockalingam (see, e.g., figs. 2B-2F) shows most aspects of the instant invention including a method comprising:
Exposing an upper surface (see, e.g., fig. 2B) of a copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”) at a bottom of an opening defined in at least one dielectric layer (e.g., capping layer 206 + paragraph 50 “The capping layer 206 may be a dielectric material…”), wherein a passivation layer (e.g., passivation layer 208) is on sidewalls of the opening above the copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”);
Forming a conductive layer (e.g., planar barrier 218, see fig. 2E) directly on the exposed upper surface of the copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”), the conductive layer (e.g., planar barrier 218) consisting of a palladium layer (see, e.g., paragraph 56 “In some embodiments of the disclosure, the planar barrier 218 may include palladium…”);
Forming a copper interconnect (e.g., bonding wire 220, see fig. 2F + paragraph 59 “In this embodiment of the disclosure, the bonding wire is preferably copper”) directly on the conductive layer (e.g., planar barrier 218);
Chockalingam (see, e.g., figs. 2B-2F), however, fails to show annealing after forming the conductive layer to convert the conductive layer into a stack including the palladium layer and a copper palladium alloy layer below the palladium layer.
Kellam (see, e.g., figs. 1A-1C or 2A-2C), in a similar device to Chockalingam, teaches annealing (see, e.g., paragraph 7) after forming a conductive layer (e.g., palladium film 12 + aluminum 13) to convert the conductive layer (e.g., palladium film 12 + aluminum 13) into a stack including a palladium layer (e.g., palladium film 12) and an aluminum palladium alloy layer (e.g., aluminum alloy film 12) over the palladium layer (e.g., palladium film 12).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the annealing step of Kellam on the palladium layer of Chockalingam, in order to diversify the materials and improve the electrical properties of the conductive layer within the device.
Chockalingam in view of Kellam, however, fails to teach the stack includes a copper palladium alloy, and the copper palladium alloy is below the palladium layer.
Goh (see, e.g., fig. 2A), in a similar device to Chockalingam in view of Kellam, teaches an alloy (see, e.g., paragraph 57 “…combination of copper…aluminum, palladium…and/or alloys thereof”) of copper palladium as an alternative to aluminum palladium.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of
filing the invention to include the conductive alloy of copper palladium within the conductive stack of Chockalingam in view of Kellam, because many are recognized in the semiconductor art for their usage in conductive materials, as taught by Goh, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Chockalingam in view of Kellam further in view of Goh, however, fails to explicitly teach the copper palladium alloy is below the palladium layer.
Cheng (see, e.g., fig. 8), in a similar device to Chockalingam in view of Kellam further in view of Goh, teaches a conductive layer comprising a copper layer (e.g., copper-containing layer 60) below palladium layer (e.g., metal cap layer 62 + paragraph 36 “…palladium containing layer”).
Accordingly, it would have been obvious to one or ordinary skill in the art at the time of filing the invention to include the palladium over copper configuration of Cheng within the conductive layer of Chockalingam in view of Kellam further in view of Goh pre-annealing configuration, in order to achieve the expected result of providing a distinct palladium and copper profile within the bonding area during treatment and fabrication of the device. Also note that the annealing of Kellam is performed on an aluminum film over a palladium film, resulting in an aluminum alloy film over the palladium film post-annealing process, hence the annealing process carried out on the palladium over copper configuration of Chockalingam in view of Kellam further in view of Goh and Cheng would result in a palladium film over a copper palladium alloy (note the interface between the palladium and copper). In addition, note the limited arrangements of the palladium and copper layers possible within the conductive layer of Chockalingam in view of Kellam further in view of Goh and Cheng, i.e., palladium-over-copper or copper-over-palladium and since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as long as the palladium and copper are configured uniformly and within the conductive bonding area, as already suggested by Cheng. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding claim 17, Kellam (see, e.g., table 1) teaches a stack (e.g., palladium + aluminum) has a thickness between 15 to 100 nanometers (see, e.g., paragraph 13… “…10 nm palladium, then, finally, 20 nm aluminum”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the 30 nm stack configuration of Kellam within the stack of Chockalingam in view of Kellam further in view of Goh and Cheng, in order to provide the expected result of limiting the cost of material fabrication while manufacturing the device, while simultaneously providing a distinct palladium and aluminum/copper (note the alternative materials to aluminum as argued earlier) profile as desired.
Regarding claim 20, Chockalingam (see, e.g., figs. 2B-2F) shows the copper interconnect (e.g., bonding wire 220, see fig. 2F + paragraph 59 “In this embodiment of the disclosure, the bonding wire is preferably copper”) forming includes forming one of: forming a copper wire bond (see, e.g., paragraphs 58 and 59) on the copper bond pad (e.g., bond pad 204 + paragraph 50 “In an embodiment of the disclosure, the bond pad 204 may be formed of copper”), or forming both a copper redistribution layer (RDL) and a solder ball on the copper RDL.
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chockalingam in view of Kellam further in view of Goh, Cheng, and Lin (US 20160276307 A1).
Regarding claim 10, Chockalingam in view of Kellam further in view of Goh and Cheng fails to teach cleaning the conductive layer prior to forming the copper interconnect.
Lin (see, e.g., fig. 11h), in a similar device to Chockalingam in view of Kellam further in view of Goh and Cheng, teaches cleaning (see, e.g., paragraph 124 “A plasma clean is also performed to clean any contaminants from the exposed conductive layer 310, using reactive iron etching (RIE) or downstream/microwave plasma with O2…”) a conductive layer (e.g., exposed conductive layer 310).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the cleaning step of Lin on the conductive layer of Chockalingam in view of Kellam further in view of Goh and Cheng, in order to achieve the expected result of removing potential contaminants present on the conductive layer before connecting it with the interconnect structure, increasing reliability and efficiency and preventing probable defects of the device (see paragraph 124 of Lin).
Regarding claim 18, Chockalingam in view of Kellam further in view of Goh and Cheng fails to teach cleaning the conductive layer prior to forming the copper interconnect.
Lin (see, e.g., fig. 11h), in a similar device to Chockalingam in view of Kellam further in view of Goh and Cheng, teaches cleaning (see, e.g., paragraph 124 “A plasma clean is also performed to clean any contaminants from the exposed conductive layer 310, using reactive iron etching (RIE) or downstream/microwave plasma with O2…”) a conductive layer (e.g., exposed conductive layer 310).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the cleaning step of Lin on the conductive layer of Chockalingam in view of Kellam further in view of Goh and Cheng, in order to achieve the expected result of removing potential contaminants present on the conductive layer before connecting it with the interconnect structure, increasing reliability and efficiency and preventing probable defects of the device (see paragraph 124 of Lin).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chockalingam in view of Kellam further in view of Goh, Cheng, Lin, and Clemens (US 4291322 A).
Regarding claim 11, Lin teaches the plasma clean includes performing a plasma etch (see, e.g., paragraph 124 “A plasma clean is also performed to clean any contaminants from the exposed conductive layer 310, using … downstream/microwave plasma “).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the plasma etch of Lin in the cleaning method of Chockalingam in view of Kellam further in view of Goh, Cheng, and Lin, as the inclusion of the plasma etch was well-understood at the time in the art as a known process/step in the plasma cleaning process (as taught by paragraph 124 of Lin).
Chockalingam in view of Kellam further in view of Goh, and Cheng, and Lin, however, fails to teach the plasma etch uses an etch chemistry including hydrogen in a ratio of 5% to 10% and a remaining portion including one of argon or nitrogen.
Clemens (see, e.g., fig. 7), in a similar device to Chockalingam in view of Kellam further in view of Goh, Cheng, and Lin, teaches a plasma etch comprising an etch chemistry including hydrogen in a ratio of 5 to 10% and a remaining portion including one of argon or nitrogen (see, e.g., paragraph 21 “plasma etch utilizing CCL.sub.4 at a flow rate of 350 cm.sup.3 /min which was mixed with a combination of 92 percent Argon and 8 percent Hydrogen”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the hydrogen-argon ratio of Clemens in the plasma etch of Chockalingam in view of Kellam further in view of Goh, Cheng, and Lin, as this ratio was well-understood at the time of filing the invention to provide the appropriate hydrogen concentration within the plasma etching step.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chockalingam in view of Kellam further in view of Goh, Cheng, and Scarbrough (US 20220278051 A1).
Regarding claim 13, Chockalingam (see, e.g., figs 2B-2F) shows exposing the upper surface includes performing a dry etching (see, e.g., paragraph 51 “The bond pad opening 210 may be formed by using a material removal process, such as a dry etching process”).
Chockalingam in view of Kellam further in view of Goh and Cheng, however, fails to teach exposing the upper surface includes performing a plasma-based etching.
Scarbrough (see, e.g., fig. 1H), in a similar device to Chockalingam in view of Kellam further in view of Goh and Cheng, teaches plasma-etching is a known-type of the dry etching process (see, e.g., paragraph 60 “…may be formed using anisotropic dry etching, such as one or more of RIE, deep RIE, plasma etching…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the plasma-based etching in the dry etching step of Chockalingam in view of Kellam further in view of Goh and Cheng, as plasma-based etching was well-understood in the art as a known methodology as a type of dry etching (see, e.g., paragraph 60 of Scarbrough).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chockalingam in view of Kellam further in view of Goh, Cheng, Paek (US 20120175758 A1), and Cho (US 8564107 B2).
Regarding claim 21, Chockalingam in view of Kellam further in view of Goh and Cheng fails to teach wherein the palladium layer of the stack includes a first thickness and the copper palladium alloy layer of the stack includes a second thickness, different from the first thickness.
Paek (see, e.g., fig. 4), in a similar device to Chockalingam in view of Kellam further in view of Goh and Cheng, teaches a copper palladium alloy layer (e.g., second metal layer 300 + paragraph 55 “…second metal layer 300 may be formed by electroplating…palladium alloy…if the second metal layer 300 is formed of a palladium alloy, metal that may be added to palladium may include…copper”) includes a thickness (see, e.g., paragraph 55 “…the thickness of the second metal layer 300 may be approximately, 1 .mu.m to 3 .mu.m…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the copper palladium alloy thickness of Paek within the copper palladium alloy layer of Chockalingam in view of Kellam further in view of Goh and Cheng, in order to achieve the expected result of limiting the cost of material fabrication while manufacturing the device, while simultaneously providing a distinct copper palladium alloy layer profile as desired.
Chockalingam in view of Kellam further in view of Goh, Cheng, and Paek, however, fails to teach a palladium layer comprises a different thickness than the copper palladium alloy profile thickness.
Cho (see, e.g., figs. 1-2), in a similar device to Chockalingam in view of Kellam further in view of Goh, Cheng, and Paek, teaches a palladium layer (e.g., palladium plating layer 40) comprising a thickness (see, e.g., paragraph 16 “…formed in a thickness of .02 to .08 .mu.m.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness of the palladium layer of Cho within the palladium layer of Chockalingam in view of Kellam further in view of Goh, Cheng, and Paek, in order to achieve the expected result of limiting the cost of material fabrication while manufacturing the device, while simultaneously providing a distinct palladium layer profile as desired.
Regarding claim 22, Chockalingam in view of Kellam further in view of Goh and Cheng fails to teach wherein the palladium layer of the stack includes a first thickness and the copper palladium alloy layer of the stack includes a second thickness, different from the first thickness.
Paek (see, e.g., fig. 4), in a similar device to Chockalingam in view of Kellam further in view of Goh and Cheng, teaches a copper palladium alloy layer (e.g., second metal layer 300 + paragraph 55 “…second metal layer 300 may be formed by electroplating…palladium alloy…if the second metal layer 300 is formed of a palladium alloy, metal that may be added to palladium may include…copper”) includes a thickness (see, e.g., paragraph 55 “…the thickness of the second metal layer 300 may be approximately, 1 .mu.m to 3 .mu.m…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the copper palladium alloy thickness of Paek within the copper palladium alloy layer of Chockalingam in view of Kellam further in view of Goh and Cheng, in order to achieve the expected result of limiting the cost of material fabrication while manufacturing the device, while simultaneously providing a distinct copper palladium alloy layer profile as desired.
Chockalingam in view of Kellam further in view of Goh, Cheng, and Paek, however, fails to teach a palladium layer comprises a different thickness than the copper palladium alloy profile thickness.
Cho (see, e.g., figs. 1-2), in a similar device to Chockalingam in view of Kellam further in view of Goh, Cheng, and Paek, teaches a palladium layer (e.g., palladium plating layer 40) comprising a thickness (see, e.g., paragraph 16 “…formed in a thickness of .02 to .08 .mu.m.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness of the palladium layer of Cho within the palladium layer of Chockalingam in view of Kellam further in view of Goh, Cheng, and Paek, in order to achieve the expected result of limiting the cost of material fabrication while manufacturing the device, while simultaneously providing a distinct palladium layer profile as desired.
Regarding claim 23, Chockalingam in view of Kellam further in view of Goh, Cheng, Paek, and Cho teaches the first thickness is less than the second thickness (e.g., note that the first thickness is .02 to .08 .mu.m., per Cho, and the second thickness is .1 .mu.m. to 3 .mu.m., per Paek).
Accordingly, it would have been obvious to one of ordinary skill in the art the time of filing the invention to include the differing thicknesses of Paek and Cho, in order to diversify the stack configuration and manufacture the desired stability profile while simultaneously limiting the price of material (see, e.g., paragraph 55 of Paek). Also see the comments above with respect to the rejection of claim 21, which are considered to be relevant here.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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