Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection Withdrawal
Applicant’s amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Drawings Objection Withdrawal
Applicant’s amendment of Claim 2 is acknowledged. Thus, the objection to drawings is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 11 and 13-16 rejected under 35 U.S.C. 103 as being unpatentable over Pan (U.S. Patent Pub. No. 2020/0051607) of record, in view of Chae (U.S. Patent Pub. No. 2008/0128757), in view of Kim (U.S. Patent Pub. No. 2019/0103407).
Regarding Claim 1
FIG. 1 of Pan discloses a semiconductor memory device comprising: a semiconductor substrate (106); a data storage layer including capacitors (119) arranged on the semiconductor substrate; a switching element layer on the data storage layer and including transistors (120) connected to respective ones of the capacitors; and a wiring layer (134) on the switching element layer and including bit lines (138) connected to respective ones of the transistors, wherein the respective transistors include an active pattern (128) having a lengthwise axis parallel to a top surface of the semiconductor substrate, a word line (132) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall and a second sidewall of the active pattern, and a ferroelectric layer (HfO2 130) between the word line and the first portion of the active patter.
Pan is silent with respect to “the word line surrounds a first sidewall, a second sidewall and a top surface of the active pattern” and “the lengthwise axis of the active pattern intersects the word line and the bit lines”.
FIG. 1C of Chae discloses a similar semiconductor memory device, comprising an active pattern (120) having a lengthwise axis (horizontal) parallel to a top surface of the semiconductor substrate (110), a word line (WL) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the first portion of the active pattern, wherein the lengthwise axis of the active pattern intersects the word line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Chae. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of improving the degree of integration and reliability ([0033] of Chae).
Pan as modified by Chae is silent with respect to the lengthwise axis of the active pattern intersects the bit lines.
FIG. 2 of Kim discloses a similar semiconductor memory device, comprising an active pattern (SP) having a lengthwise axis parallel to a top surface of the semiconductor substrate (100), a word line (WL) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the first portion of the active pattern, wherein the lengthwise axis of the active pattern intersects the word line and the bit lines (BL).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Kim. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of highly integrated 3D memory devices ([0003] of Kim).
Regarding Claim 2
FIG. 2 of Kim discloses the word line extends in a first direction that is parallel to a top surface of the semiconductor substrate, the bit lines extends in a second direction that intersects the first direction, and the active pattern has the lengthwise axis in a third direction that is parallel to the top surface of the semiconductor substrate and intersects the first and second directions.
Regarding Claim 3
FIG. 1 of Pan discloses shielding lines (between 138) in regions between the bit lines.
Regarding Claim 4
FIG. 1 of Pan discloses a lower contact pattern (protrusion of 122) contacting a bottom surface of the active pattern at one side of the word line; and an upper contact pattern (136) contacting a top surface of the active pattern at an opposite side of the word line.
Regarding Claim 5
FIG. 1 of Pan discloses one of the capacitors is connected to the lower contact pattern, and one of the bit lines (138) is connected to the upper contact pattern (136).
Regarding Claim 6
FIG. 1 of Pan discloses the capacitors includes: a plate electrode (107 [0075]) on the semiconductor substrate (106); first electrodes (126) two-dimensionally arranged on the plate electrode; second electrodes (122) on the first electrodes; and capacitor dielectric layers (124) between the first electrodes and the second electrodes, respectively.
Regarding Claim 7
FIG. 1 of Pan discloses each of the first electrodes (126) includes a bottom part contacting the plate electrode and a sidewall part extending vertically from the bottom part.
Regarding Claim 8
FIG. 1 of Pan discloses the ferroelectric layer includes at least one of HfO2, Si-doped HfO2 (HfSiO2), Al-doped HfO2 (HfAlO2), HfSiON, HfZnO, HIZrO2, ZrO2, ZrSiO2, HfZrSiO2, ZrSiON, LaAlO2, HfDyO2, or HfScO2 [0085].
Regarding Claim 11
FIG. 1 of Pan discloses a semiconductor memory device comprising: a plate electrode (107) on a semiconductor substrate (106); first electrodes (126) two-dimensionally arranged on the plate electrode; second electrodes (122) on the first electrodes; capacitor dielectric layers (124) between the first electrodes and the second electrodes, respectively; an active pattern (128) having a lengthwise axis parallel to a top surface of the semiconductor substrate and connected to one of the second electrodes; a word line (132) crossing a first portion of the active pattern; a ferroelectric layer (HfO2 130) between the word line and the first portion of the active pattern; and a bit line (138) crossing the word line and connected to a second portion of the active pattern [0085, 0087].
Pan is silent with respect to “the lengthwise axis of the active pattern intersects the word line and the bit lines”.
FIG. 1 of Chae discloses a similar semiconductor memory device, comprising an active pattern (120) having a lengthwise axis (horizontal) parallel to a top surface of the semiconductor substrate (110), a word line (WL) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the first portion of the active pattern, wherein the lengthwise axis of the active pattern intersects the word line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Chae. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of improving the degree of integration and reliability ([0033] of Chae).
Pan as modified by Chae is silent with respect to the lengthwise axis of the active pattern intersects the bit lines.
FIG. 2 of Kim discloses a similar semiconductor memory device, comprising an active pattern (SP) having a lengthwise axis parallel to a top surface of the semiconductor substrate (100), a word line (WL) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the first portion of the active pattern, wherein the lengthwise axis of the active pattern intersects the word line and the bit lines (BL).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Kim. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of highly integrated 3D memory devices ([0003] of Kim).
Regarding Claim 13
FIG. 1 of Pan discloses a shielding line (between 138) extending parallel to the bit line and located at a same level as the bit line.
Regarding Claim 14
FIG. 1 of Pan discloses each of the first electrodes (126) includes a bottom part contacting the plate electrode and a sidewall part extending vertically from the bottom part.
Regarding Claim 15
FIG. 1 of Pan discloses the word line crosses both sidewalls of the active pattern.
Regarding Claim 16
FIG. 1 of Pan discloses a lower contact pattern (protrusion of 122) connecting one of the second electrodes to the active pattern at one side of the word line; and an upper contact pattern (136) connecting the active pattern to the bit line at an opposite side of the word line.
Claims 9 and 10 rejected under 35 U.S.C. 103 as being unpatentable over Pan, Chae and Kim, in view of Minami (U.S. Patent Pub. No. 2011/0188288) of record.
Regarding Claim 9
Pan as modified by Chae and Kim discloses Claim 1.
Pan as modified by Chae and Kim is silent with respect to “a gate dielectric layer between the ferroelectric layer and the active pattern”.
FIG. 43 of Minami discloses a similar semiconductor memory device, comprising a gate dielectric layer (217) between the ferroelectric layer (227) and the active pattern (30).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Minami. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of reducing the cell size ([0003] of Minami).
Regarding Claim 10
FIG. 43 of Minami discloses a gate dielectric layer (217) between the ferroelectric layer (227) and the active pattern; and a sub-gate electrode (213) between the ferroelectric layer and the gate dielectric layer [0099].
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Pan, Chae and Kim, in view of Ikeda (U.S. Patent No. 11,056,175) of record.
Regarding Claim 17
Pan as modified by Chae and Kim discloses Claim 16.
Pan as modified by Chae and Kim is silent with respect to “a width of the active pattern is less than a width of the upper contact pattern and is less than a width of the lower contact pattern”.
FIG. 1 of Ikeda discloses a similar semiconductor memory device, wherein a width of the active pattern (AA) is less than a width of the upper contact pattern (CC) and is less than a width of the lower contact pattern (BC).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Ikeda. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of reducing device size (Col. Lines 15-29 of Ikeda).
Claims 12 and 18-20 rejected under 35 U.S.C. 103 as being unpatentable over Pan, Chae and Kim, in view of Cho (U.S. Patent Pub. No. 2009/0068814) of record.
Regarding Claim 12
Pan as modified by Chae and Kim discloses Claim 11, wherein the word line extends in a first direction parallel to the top surface of the semiconductor substrate, the bit line extends in a second direction parallel to the top surface of the semiconductor substrate and perpendicular to the first direction [0072].
Pan as modified by Chae and Kim is silent with respect to “the first electrodes are spaced apart from one another by a same first distance in the first direction and a same second distance in the second direction”.
FIG. 2 of Cho discloses a similar semiconductor memory device, wherein the first electrodes are spaced apart from one another by a same first distance in the first direction and a same second distance in the second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Cho. The ordinary artisan would have been motivated to modify Pan in the above manner, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
Regarding Claim 18
FIG. 1 of Pan discloses a semiconductor memory device comprising: a plate electrode (107) on a semiconductor substrate (106); first electrodes (126) in a dielectric layer (112) covering the plate electrode and connected to the plate electrode; second electrodes (122) on the first electrodes; capacitor dielectric layers (124) between the first electrodes and the second electrodes, respectively; lower contact patterns (protrusion of 122) passing through a first interlayer insulating layer covering the first and second electrodes on the mold layer, the lower contact patterns connected to the second electrodes, respectively; active patterns (128) on the first interlayer insulating layer and having a lengthwise axis parallel to a top surface of the semiconductor substrate, each of the active patterns connected to a first pair of the lower contact patterns; word lines (132) extending in a first direction and crossing a first portions of the active patterns on the first interlayer insulating layer; a ferroelectric layer (HfO2 130) between the word lines and the first portions of the active patterns; upper contact patterns (136) connected to second portions of the active patterns between the word lines; bit lines (138) extending in a second direction and crossing the word lines, the bit lines connected to the upper contact patterns; and shielding lines (between 138) extending in the second direction and respectively provided in regions between the bit lines.
Pan is silent with respect to “the lengthwise axis of the active pattern intersects the word line and the bit lines”.
FIG. 1 of Chae discloses a similar semiconductor memory device, comprising an active pattern (120) having a lengthwise axis (horizontal) parallel to a top surface of the semiconductor substrate (110), a word line (WL) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the first portion of the active pattern, wherein the lengthwise axis of the active pattern intersects the word line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Chae. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of improving the degree of integration and reliability ([0033] of Chae).
Pan as modified by Chae is silent with respect to the lengthwise axis of the active pattern intersects the bit lines.
FIG. 2 of Kim discloses a similar semiconductor memory device, comprising an active pattern (SP) having a lengthwise axis parallel to a top surface of the semiconductor substrate (100), a word line (WL) that crosses a first portion of the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the first portion of the active pattern, wherein the lengthwise axis of the active pattern intersects the word line and the bit lines (BL).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Kim. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of highly integrated 3D memory devices ([0003] of Kim).
The limitation “mold” is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113.
Furthermore, FIG. 4 of Cho discloses a similar semiconductor memory device, wherein the silicon oxide layer 112 of Pan can be made by mold [0081].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Cho. The ordinary artisan would have been motivated to modify Pan in the above manner, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
Regarding Claim 19
FIG. 1 of Pan discloses the lower contact patterns are in contact with top surfaces of the second electrodes.
Regarding Claim 20
FIG. 2 of Cho discloses the first electrodes are spaced apart from one another by a same first distance in the first direction a same second distance in the second direction.
Pertinent Art
Pertinent art includes US 20020134997, 20050112819, 20120051137, 20140054538 and 20200111793.
Response to Arguments
Applicant’s arguments with respect to Claims 1, 11 and 18 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Prosecution Insights