SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Applicant's response to the Office Final Action filed on 7/2/2026 is acknowledged. Applicant amended claims 1, 12, 14, and 19; and cancelled claim 13. Applicant added claims 26. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 20240021618) (hereafter Chin), in view of Kim et al. (US 2018/0145072) (hereafter Kim072), in further view of Liaw et al. (US 2016/0155670) (hereafter Liaw). Regarding claim 1, Chin discloses a semiconductor device comprising: a first active fin (52 of 53B in Fig. 23A, paragraph 0054) extending in a first direction (stacking direction in Fig. 23A) and having first fin-type patterns (52 of 53B in Fig. 23A) aligned with each other with a first separation region (lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A, paragraph 0056) therebetween; a second active fin (leftmost 52 and middle 52 of 53C in Fig. 23A, paragraph 0054) extending in the first direction (stacking direction in Fig. 23A) and having second fin-type patterns (leftmost 52 and middle 52 of 53C in Fig. 23A) aligned with each other with a second separation region (upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A, paragraph 0056) therebetween, wherein an entirety of the first separation region (lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A) and an entirety of the second separation region (upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A) are arranged to not overlap (see Fig. 23A, wherein an entirety of lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A does not overlap an entirety of upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A) each other in a second direction (horizontal direction in Fig. 23A) that intersects the first direction (stacking direction in Fig. 23A), and wherein a first trench region (region where 56 is formed between 51 of 53B and 51 of 53C in Fig. 23A) between the first (52 of 53B in Fig. 23A) and second active fins (leftmost 52 and middle 52 of 53C in Fig. 23A) has a first depth (vertical length of 56 which is located between 51 of 53B and 51 of 53C in Fig. 23A); a third active fin (52 of 53A in Fig. 23A, paragraph 0054) extending in the first direction (stacking direction in Fig. 23A) adjacent to the first active fin (52 of 53B in Fig. 23A), wherein a second trench region (region where 56 is formed between 51 of 53A and 51 of 53B in Fig. 23A) between the first (52 of 53B in Fig. 23A) and third active fins (52 of 53A in Fig. 23A); a fourth active fin (rightmost 52 of 53C in Fig. 23A, paragraph 0054) extending in the first direction (stacking direction in Fig. 23A) adjacent to the second active fin (leftmost 52 and middle 52 of 53C in Fig. 23A), wherein a third trench region (region where 56 is formed between middle 52 of 53C and rightmost 52 in Fig. 23A) between the second (leftmost 52 and middle 52 of 53C in Fig. 23A) and fourth active fins (rightmost 52 of 53C in Fig. 23A); at least one first gate line 94 (Fig. 23A, paragraph 0061) extending in the second direction (horizontal direction in Fig. 23A) and intersecting the first (52 of 53B in Fig. 23A) and second active fins (leftmost 52 and middle 52 of 53C in Fig. 23A) and the third active fin (52 of 53A in Fig. 23A); and wherein the first fin-type patterns (52 of 53B in Fig. 23A) and the second fin-type patterns (leftmost 52 and middle 52 of 53C in Fig. 23A) are merged by the first trench region (region where 56 is formed between 51 of 53B and 51 of 53C in Fig. 23A), and wherein the second (region where 56 is formed between 51 of 53A and 51 of 53B in Fig. 23A) and third trench regions (region where 56 is formed between middle 52 of 53C and rightmost 52 in Fig. 23A) are connected to the first (56 between 52 of 53B in Fig. 23A) and second separation regions (56 between leftmost 52 and middle 52 of 53C in Fig. 23A), respectively. Chin does not disclose a second depth that is greater than the first depth; a third depth that is greater than the first depth; and wherein a bottom of the first separation region is at a same level as a bottom of the second trench region, and a bottom of the second separation region is at a same level as a bottom of the third trench region. Kim072 discloses a second depth D2 (Fig. 1A, paragraph 0030) that is greater than the first depth D1 (Fig. 1A, paragraph 0030); a third depth D3 (Fig. 1A, paragraph 0030) that is greater than the first depth D1 (Fig. 1A); and a bottom of the separation region (second 114b from the left corner of Fig. 1A, paragraph 0019) is at substantially a same level as a bottom of the second trench region (first 114b from the left corner of Fig. 1A, paragraph 0019). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin to form a second depth that is greater than the first depth; a third depth that is greater than the first depth; and wherein a bottom of the first separation region is at a same level as a bottom of the second trench region, and a bottom of the second separation region is at a same level as a bottom of the third trench region, as taught by Kim072, since depths (Kim072, paragraph 0029) of the first, second and third trenches 110a, 110b and 110c (Kim072, Fig. 1A, paragraph 0029) may be different from each other. In addition, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Chin and Kim072 do not disclose at least one second gate line extending in the second direction and intersecting the first and second active fins and the fourth active fin. Liaw discloses at least one second gate line 1420 (Fig. 14A, paragraph 0032) extending in the second direction (horizontal direction in Fig. 14A) and intersecting the first (1404 and 1406 in Fig. 14A, paragraph 0032) and second active fins (1408 and 1410 in Fig. 14A, paragraph 0032) and the fourth active fin 1412 (Fig. 14A, paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 to form at least one second gate line extending in the second direction and intersecting the first and second active fins and the fourth active fin, as taught by Liaw, since one such multi-gate device (Liaw, paragraph 0002) that has been introduced is the fin field-effect transistor (FinFET) such that their three-dimensional structure (Liaw, paragraph 0002) allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. Regarding claim 2, Chin further discloses the semiconductor device of claim 1, wherein each of the first fin-type patterns (52 of 53B in Fig. 23A) has a first central region (middle portion of 52 of 53B in Fig. 23A), overlapping the second separation region (upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A) in the second direction (horizontal direction in Fig. 23A), and first (right portion of 56 between 52 of 53A and 51 of 53B in Fig. 23A) and second end regions (left portion of 56 between 51 of 53B and 51 of 53C in Fig. 23A) on opposite sides of the first central region (middle portion of 52 of 53B in Fig. 23A), and wherein each of the second fin-type patterns (leftmost 52 and middle 52 of 53C in Fig. 23A) has a second central region (middle portion of 52 of 53C in Fig. 23A), overlapping the first separation region (lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A) in the second direction (horizontal direction in Fig. 23A), and third (right portion of 56 between 51 of 53B and 51 of 53C) and fourth end regions (56 between middle 52 and rightmost 52 of 53C in Fig. 23A) on opposite sides of the second central region (middle portion of 52 of 53C in Fig. 23A). Regarding claim 3, Chin further discloses the semiconductor device of claim 2, wherein the first end region (right portion of 56 between 52 of 53A and 51 of 53B in Fig. 23A) and the fourth end region (56 between middle 52 and rightmost 52 of 53C in Fig. 23A) overlap each other in the second direction (horizontal direction in Fig. 23A) and the second end region (left portion of 56 between 51 of 53B and 51 of 53C in Fig. 23A) and the third end region (right portion of 56 between 51 of 53B and 51 of 53C) overlap each other in second direction (horizontal direction in Fig. 23A). Regarding claim 4, Chin in view of Kim072 and Liaw discloses the semiconductor device of claim 3, however Chin and Kim072 do not disclose the at least one first gate line comprises a plurality of first gate lines respectively intersecting the third active fin and the first and fourth end regions overlapping each other, and wherein the at least one second gate line comprises a plurality of second gate lines respectively intersecting the fourth active fin and the second and third end regions overlapping each other. Liaw discloses the at least one first gate line (1414 and 1416 in Fig. 14A) comprises a plurality of first gate lines (1414 and 1416 in Fig. 14A) respectively intersecting the third active fin 1402 (Fig. 14A, paragraph 0032) and the first (region on the left-hand side of 1404 in Fig. 14A) and fourth end regions (region on the right-hand side of 1410 in Fig. 14A) overlapping each other, and wherein the at least one second gate line (1418 and 1420 in Fig. 14A) comprises a plurality of second gate lines (1418 and 1420 in Fig. 14A) respectively intersecting the fourth active fin 1412 (Fig. 14A) and the second (region on the right-hand side of 1406 in Fig. 14A) and third end regions (region on the left-hand side of 1408 in Fig. 14A) overlapping each other. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 to form the at least one first gate line comprises a plurality of first gate lines respectively intersecting the third active fin and the first and fourth end regions overlapping each other, and wherein the at least one second gate line comprises a plurality of second gate lines respectively intersecting the fourth active fin and the second and third end regions overlapping each other, as taught by Liaw, since one such multi-gate device (Liaw, paragraph 0002) that has been introduced is the fin field-effect transistor (FinFET) such that their three-dimensional structure (Liaw, paragraph 0002) allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. Regarding claim 5, Chin further discloses the semiconductor device of claim 3, wherein the first (52 of 53B in Fig. 23A) and second active fins (leftmost 52 and middle 52 of 53C in Fig. 23A) have a first conductivity type (see paragraph 0021, wherein “the first and second active fins have a first conductivity type, and the third and fourth active fins have a second conductivity type”), and the third (52 of 53A in Fig. 23A) and fourth active fins (rightmost 52 of 53C in Fig. 23A) have a second conductivity type (see paragraph 0021). Regarding claim 8, Chin further discloses the semiconductor device of claim 1, wherein the first (52 of 53B in Fig. 23A) and second fin-type patterns (leftmost 52 and middle 52 of 53C in Fig. 23A) have end surfaces defined by the first (lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A) and second separation regions (upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A), respectively, and each of the end surfaces of the first (52 of 53B in Fig. 23A) and second fin-type patterns (leftmost 52 and middle 52 of 53C in Fig. 23A) has a portion (lateral surface of 52 of 53B in Fig. 23A) that is substantially perpendicular (see Fig. 23A, wherein lateral surface of 52 of 53B is in stacking direction) to the first direction (stacking direction in Fig. 23A) in plan view. Claims 6, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chin in view of Kim072 and Liaw as applied to claims 1 and 3 above, and further in view of Tokranov et al. (US 2021/0358865) (hereafter Tokranov). Regarding claim 6, Chin in view of Kim072 and Liaw discloses the semiconductor device of claim 3, however Chin, Kim072, and Liaw do not disclose a third gate line extending in the second direction and aligned with the at least one first gate line, and intersecting the fourth active fin; and a fourth gate line extending in the second direction and aligned with the at least one second gate line, and intersecting the third active fin. Tokranov discloses a third gate line (third 130 from the left corner of Fig. 6, paragraph 0027) extending in the second direction (vertical direction in Fig. 6) and aligned with the at least one first gate line (first 130 from the left corner of Fig. 6, paragraph 0027), and intersecting the fourth active fin 104H (Fig. 6, paragraph 0033); and a fourth gate line (fourth 130 from the left corner of Fig. 6, paragraph 0027) extending in the second direction (vertical direction in Fig. 6) and aligned with the at least one second gate line (second 130 from the left corner of Fig. 6, paragraph 0027), and intersecting the third active fin 104I (Fig. 6, paragraph 0033). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 and Liaw to form a third gate line extending in the second direction and aligned with the at least one first gate line, and intersecting the fourth active fin; and a fourth gate line extending in the second direction and aligned with the at least one second gate line, and intersecting the third active fin, as taught by Tokranov, since the IC product 100 (Tokranov, Fig. 6, paragraph 0015) may comprise a plurality of FinFET transistor devices, wherein each of the FinFET transistor devices may comprise any desired number of fins 104 (Tokranov, Fig. 6, paragraph 0015). Regarding claim 10, Chin further discloses the semiconductor device of claim 1, wherein the first trench region (region where 56 is formed between 51 of 53B and 51 of 53C in Fig. 23A) defines opposing side surfaces of the first (52 of 53B in Fig. 23A) and second fin-type patterns (leftmost 52 and middle 52 of 53C in Fig. 23A). Chin, Kim072, and Liaw do not disclose a portion extending to the first or second separation regions in the first direction. Tokranov discloses a portion (portion of 110 between second and third vertical regions of 102 from the left corner of Fig. 7) extending to the first or second separation regions (upper portion of 110 in Fig. 7) in the first direction (horizontal direction in Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 and Liaw to form a portion extending to the first or second separation regions in the first direction, as taught by Tokranov, since the formation of a deep isolation structure 110 (Tokranov, Fig. 7, paragraph 0019) in the substrate 102 (Tokranov, Fig. 7, paragraph 0019) that electrically isolates adjacent transistor devices from one another. Regarding claim 11, Chin in view of Kim072 and Liaw discloses the semiconductor device of claim 10, however Chin, Kim072, and Liaw do not disclose the portion of the first trench region has a bottom at substantially a same level as a bottom of the first trench region, which defines a step difference with respect to the bottom of the first or second separation regions. Tokranov discloses the portion of the first trench region (portion of 110 between second and third vertical regions of 102 from the left corner of Fig. 7) has a bottom at substantially a same level as a bottom of the first trench region (lower portion of 110 between second and third vertical regions of 102 from the left corner of Fig. 7), which defines a step difference with respect to the bottom of the first or second separation regions (upper portion of 110 in Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 and Liaw to form the portion of the first trench region has a bottom at substantially a same level as a bottom of the first trench region, which defines a step difference with respect to the bottom of the first or second separation regions, as taught by Tokranov, since the formation of a deep isolation structure 110 (Tokranov, Fig. 7, paragraph 0019) in the substrate 102 (Tokranov, Fig. 7, paragraph 0019) that electrically isolates adjacent transistor devices from one another. Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chin in view of Kim072 and Liaw as applied to claim 1 above, and further in view of Kim et al. (US 2020/0403086) (hereafter Kim086). Regarding claim 7, Chin in view of Kim072 and Liaw discloses the semiconductor device of claim 1, however Chin, Kim072, and Liaw do not disclose the first and second separation regions comprise external corners adjacent to the third and fourth active fins, respectively, and the external corners comprise a convexly rounded portion in plan view. Kim086 discloses the first and second separation regions 320-2 (Fig. 3C, paragraph 0057) comprise external corners (corners at bottom portion of 320-2 in Fig. 3C) adjacent to the third 310-1 (Fig. 3C, paragraph 0056) and fourth active fins 310-2 (Fig. 3C, paragraph 0056), respectively, and the external corners (corners at bottom portion of 320-2 in Fig. 3C) comprise a convexly rounded portion in plan view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 and Liaw to form the first and second separation regions comprise external corners adjacent to the third and fourth active fins, respectively, and the external corners comprise a convexly rounded portion in plan view, as taught by Kim086, since an H-shaped fin structure (Kim086, paragraph 0054) is manufactured using the rectangular-shaped mandrels, each of the mandrels may have a rounded-rectangular shape in which each vertex of the rectangular-shaped mandrels is rounded, and thus, the subsequently-formed spacers may also have the rounded-rectangular shape such that a fin structure (Kim086, paragraph 0020) having a two-dimensional (2D) shape in the plan view should have a greater effective fin width (W.sub.eff) than the 1D-shaped fin. Regarding claim 9, Chin in view of Kim072 and Liaw discloses the semiconductor device of claim 1, however Chin, Kim072, and Liaw do not disclose the first and second separation regions comprise internal corners adjacent to the second and first active fins, respectively, and the internal corners comprise a concavely rounded portion in plan view. Kim086 discloses the first and second separation regions 320-2 (Fig. 3C, paragraph 0057) comprise internal corners (corners at bottom portion of 320-2 in Fig. 3C) adjacent to the second 310-2 (Fig. 3C, paragraph 0056) and first active fins 310-1 (Fig. 3C, paragraph 0056), respectively, and the internal corners (corners at bottom portion of 320-2 in Fig. 3C) comprise a concavely rounded portion in plan view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 and Liaw to form the first and second separation regions comprise internal corners adjacent to the second and first active fins, respectively, and the internal corners comprise a concavely rounded portion in plan view, as taught by Kim086, since an H-shaped fin structure (Kim086, paragraph 0054) is manufactured using the rectangular-shaped mandrels, each of the mandrels may have a rounded-rectangular shape in which each vertex of the rectangular-shaped mandrels is rounded, and thus, the subsequently-formed spacers may also have the rounded-rectangular shape such that a fin structure (Kim086, paragraph 0020) having a two-dimensional (2D) shape in the plan view should have a greater effective fin width (W.sub.eff) than the 1D-shaped fin. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chin in view of Kim072 and Liaw as applied to claim 1 above, and further in view of Jhan et al. (US 2022/0384431) (hereafter Jhan). Regarding claim 12, Chin further discloses the semiconductor device of claim 1, wherein the third (52 of 53A in Fig. 23A) and fourth active fins (rightmost 52 of 53C in Fig. 23A) continuously extend in the first direction (stacking direction in Fig. 23A) free of a separation region (upper portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A, paragraph 0056). Chin, Kim072, and Liaw do not disclose a distance between the first and second active fins in the second direction is smaller than a distance between the first and third active fins or a distance between the second and fourth active fins in the second direction, and the distance between the first and third active fins is substantially the same as the distance between the second and fourth active fins. Jhan discloses a distance G1 (Fig. 14, paragraph 0029) between the first (element number is not shown in Fig. 15 but see third 110 from the left corner of Fig. 2, paragraph 0027) and second active fins (element number is not shown in Fig. 15 but see fourth 110 from the left corner of Fig. 2, paragraph 0027) in the second direction (vertical direction in Fig. 15) is smaller than a distance G2 (Fig. 14, paragraph 0029) between the first (element number is not shown in Fig. 15 but see third 110 from the left corner of Fig. 2, paragraph 0027) and third active fins (element number is not shown in Fig. 15 but see second 110 from the left corner of Fig. 2, paragraph 0027) or a distance between the second and fourth active fins in the second direction, and the distance G2 (Fig. 14, paragraph 0029) between the first (element number is not shown in Fig. 15 but see third 110 from the left corner of Fig. 2, paragraph 0027) and third active fins (element number is not shown in Fig. 15 but see second 110 from the left corner of Fig. 2, paragraph 0027) is substantially the same as the distance G2 (Fig. 14) between the second (element number is not shown in Fig. 15 but see fourth 110 from the left corner of Fig. 2, paragraph 0027) and fourth active fins (element number is not shown in Fig. 15 but see fifth 110 from the left corner of Fig. 2, paragraph 0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Kim072 and Liaw to form a distance between the first and second active fins in the second direction is smaller than a distance between the first and third active fins or a distance between the second and fourth active fins in the second direction, and the distance between the first and third active fins is substantially the same as the distance between the second and fourth active fins, as taught by Jhan, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Claims 14-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 20240021618) (hereafter Chin), in view of Tokranov et al. (US 2021/0358865) (hereafter Tokranov), in more view of Kim et al. (US 2018/0145072) (hereafter Kim072), in further view of Liaw et al. (US 2016/0155670) (hereafter Liaw). Regarding claim 14, Chin discloses a semiconductor device comprising: a first active fin (52 of 53B in Fig. 23A, paragraph 0054) extending in a first direction (stacking direction in Fig. 23A) and having first (left 52 of 53B in Fig. 23A) and second fin-type patterns (right 52 of 53B in Fig. 23A) separated by a separation region (56 between left 52 of 53B and right 52 of 53B in Fig. 23A, paragraph 0056); a second active fin (52 of 53C in Fig. 23A, paragraph 0054) extending in the first direction (stacking direction in Fig. 23A) and having a central region (middle 52 of 53C in Fig. 23A, paragraph 0022) overlapping the separation region (56 between left 52 of 53B and right 52 of 53B in Fig. 23A) in a second direction (horizontal direction in Fig. 23A) that intersects the first direction (stacking direction in Fig. 23A), and first (left side surface of left 52 of 53C in Fig. 23A) and second end regions (right side surface of right 52 of 53C in Fig. 23A) overlapping the first (left 52 of 53B in Fig. 23A) and second fin-type patterns (right 52 of 53B in Fig. 23A), respectively, in the second direction (horizontal direction in Fig. 23A), wherein a first trench region (region where 56 is formed between 51 of 53B and 51 of 53C in Fig. 23A) defining opposing side surfaces (right side surface of 52 of 53B and left side surface of 52 of 53C in Fig. 23A) of the first (52 of 53B in Fig. 23A) and second active fins (52 of 53C in Fig. 23A) has a first depth (vertical length of 56 which is located between 51 of 53B and 51 of 53C in Fig. 23A); a third active fin (52 of 53A in Fig. 23A, paragraph 0054) extending in the first direction (stacking direction in Fig. 23A) and having one side surface (right side surface of 52 of 53A in Fig. 23A) opposing another side surface (left side surface of 52 of 53B in Fig. 23A) of the first active fin (52 of 53B in Fig. 23A), wherein a second trench region (region where 56 is formed between 52 of 53A and 51 of 53B in Fig. 23A) defining the another side surface (left side surface of 52 of 53B in Fig. 23A) of the first active fin (52 of 53B in Fig. 23A) and the one side surface (right side surface of 52 of 53B in Fig. 23A) of the third active fin (52 of 53A in Fig. 23A), the second trench (region where 56 is formed between 52 of 53A and 51 of 53B in Fig. 23A) separating the first active fin (52 of 53B in Fig. 23A) and the third active fin (52 of 53A in Fig. 23A) in the second direction (horizontal direction in Fig. 23A); a first gate line 94 (Fig. 23A, paragraph 0061) extending the second direction (horizontal direction in Fig. 23A) and intersecting the first fin-type pattern (left 52 of 53B in Fig. 23A) of the first active fin (52 of 53B in Fig. 23A) and a first portion of the second active fin (52 of 53C in Fig. 23A); and wherein the first (left 52 of 53B in Fig. 23A) and second fin-type patterns (right 52 of 53B in Fig. 23A) of the first active fin (52 of 53B in Fig. 23A) are merged with the second active fin (52 of 53C in Fig. 23A) by the first trench region (region where 56 is formed between 51 of 53B and 51 of 53C in Fig. 23A), and wherein the second trench region (region where 56 is formed between 52 of 53A and 51 of 53B in Fig. 23A) is connected to the separation region 56 (Fig. 23A). Chin does not disclose the separation region separating the first and second fin-type patterns in the first direction. Tokranov discloses the separation region (portion of 110 between 104J in Fig. 6, paragraph 0019) separating the first (left 104J in Fig. 6, paragraph 0037) and second fin-type patterns (right 104J in Fig. 6, paragraph 0037) in the first direction (horizontal direction in Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin to form the separation region separating the first and second fin-type patterns in the first direction, as taught by Tokranov, since a deep isolation structure 110 (comprising the insulating material 114) (Tokranov, Fig. 6, paragraph 0019) in the substrate 102 (Tokranov, Fig. 6, paragraph 0019) that electrically isolates adjacent transistor devices from one another. Chin and Tokranov do not disclose a second depth that is greater than the first depth; and a bottom of the separation region is at substantially a same level as a bottom of the second trench region. Kim072 discloses a second depth D2 (Fig. 1A, paragraph 0030) that is greater than the first depth D1 (Fig. 1A, paragraph 0030); and a bottom of the separation region (second 114b from the left corner of Fig. 1A, paragraph 0019) is at substantially a same level as a bottom of the second trench region (first 114b from the left corner of Fig. 1A, paragraph 0019). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Tokranov to form a second depth that is greater than the first depth; and a bottom of the separation region is at substantially a same level as a bottom of the second trench region, as taught by Kim072, since depths (Kim072, paragraph 0029) of the first, second and third trenches 110a, 110b and 110c (Kim072, Fig. 1A, paragraph 0029) may be different from each other. In addition, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Chin, Tokranov, and Kim072 do not disclose a second gate line extending in the second direction and intersecting the second fin-type pattern of the first active fin and a second portion of the second active fin. Liaw discloses a second gate line 1420 (Fig. 14A, paragraph 0032) extending in the second direction (horizontal direction in Fig. 14A) and intersecting the second fin-type pattern of the first active fin (1404 and 1406 in Fig. 14A, paragraph 0032) and a second portion of the second active fin (1408 and 1410 in Fig. 14A, paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Tokranov and Kim072 to form a second gate line extending in the second direction and intersecting the second fin-type pattern of the first active fin and a second portion of the second active fin, as taught by Liaw, since one such multi-gate device (Liaw, paragraph 0002) that has been introduced is the fin field-effect transistor (FinFET) such that their three-dimensional structure (Liaw, paragraph 0002) allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. Regarding claim 15, Chin in view of Tokranov, Kim072, and Liaw discloses the semiconductor device of claim 14, however Chin, Tokranov, and Kim072 do not disclose at least one of the first or second gate lines extends in the second direction to intersect the third active fin. Liaw discloses at least one of the first or second gate lines 1418 (Fig. 14A, paragraph 0032) extends in the second direction (horizontal direction in Fig. 14A) to intersect the third active fin 1402 (Fig. 14A, paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Tokranov and Kim072 to form at least one of the first or second gate lines extends in the second direction to intersect the third active fin, as taught by Liaw, since one such multi-gate device (Liaw, paragraph 0002) that has been introduced is the fin field-effect transistor (FinFET) such that their three-dimensional structure (Liaw, paragraph 0002) allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. Regarding claim 16, Chin further discloses the semiconductor device of claim 14, wherein each of the first (left 52 of 53B in Fig. 23A) and second fin-type patterns (right 52 of 53B in Fig. 23A) has an end surface defined by the separation region (56 between left 52 of 53B and right 52 of 53B in Fig. 23A). Chin, Tokranov, and Kim072 do not disclose the end surface of each of the first and second fin-type patterns comprises a portion that is substantially perpendicular to the first direction in plan view. Liaw discloses the end surface (top surface of 1404 and 1406 in Fig. 14A) of each of the first 1404 (Fig. 14A, paragraph 0032) and second fin-type patterns 1406 (Fig. 14A, paragraph 0032) comprises a portion that is substantially perpendicular to the first direction (stacking direction in Fig. 14A) in plan view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Tokranov and Kim072 to form the end surface of each of the first and second fin-type patterns comprises a portion that is substantially perpendicular to the first direction in plan view, as taught by Liaw, since one such multi-gate device (Liaw, paragraph 0002) that has been introduced is the fin field-effect transistor (FinFET) such that their three-dimensional structure (Liaw, paragraph 0002) allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. Regarding claim 18, Chin in view of Tokranov, Kim072, and Liaw discloses the semiconductor device of claim 14, however Chin does not disclose the first trench region comprises a portion extending to the separation region in the first direction, and wherein the portion of the first trench region comprises a bottom at substantially a same level as a bottom level of the first trench region, which defines a step difference with respect to the bottom of the separation region. Tokranov discloses the first trench region (lower portion of 110 between second and third vertical regions of 102 from the left corner of Fig. 7) comprises a portion extending to the separation region (upper portion of 110 in Fig. 7) in the first direction (vertical direction in Fig. 7), and wherein the portion of the first trench region (lower portion of 110 between second and third vertical regions of 102 from the left corner of Fig. 23A) comprises a bottom at substantially a same level as a bottom level of the first trench region (lower portion of 110 between second and third vertical regions of 102 from the left corner of Fig. 23A), which defines a step difference with respect to the bottom of the separation region (upper portion of 110 in Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin to form the first trench region comprises a portion extending to the separation region in the first direction, and wherein the portion of the first trench region comprises a bottom at substantially a same level as a bottom level of the first trench region, which defines a step difference with respect to the bottom of the separation region, as taught by Tokranov, since the formation of a deep isolation structure 110 (Tokranov, Fig. 7, paragraph 0019) in the substrate 102 (Tokranov, Fig. 7, paragraph 0019) that electrically isolates adjacent transistor devices from one another. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chin in view of Tokranov and Kim072 and Liaw as applied to claim 16 above, and further in view of Kim et al. (US 2020/0403086) (hereafter Kim086). Regarding claim 17, Chin in view of Tokranov, Kim072, Liaw, and Kim086 discloses the semiconductor device of claim 16, however Chin, Tokranov, Kim072, and Liaw do not disclose the separation region comprises external corners adjacent to the third active fin, and internal corners adjacent to the second active fin, and wherein the external corners comprise a convexly rounded portion in plan view, and the internal corners comprise a concavely rounded portion in plan view. Kim086 discloses the separation region 320-2 (Fig. 3C, paragraph 0057) comprises external corners (corners at bottom portion of 320-2 in Fig. 3C) adjacent to the third active fin 310-2 (Fig. 3C, paragraph 0056), and internal corners (corners at the middle portion 320-2 in Fig. 3C) adjacent to the second active fin 310-1 (Fig. 3C, paragraph 0056), and wherein the external corners (corners at bottom portion of 320-2 in Fig. 3C) comprise a convexly rounded portion in plan view, and the internal corners (corners at the middle portion 320-2 in Fig. 3C) comprise a concavely rounded portion in plan view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chin in view of Tokranov, Kim072, and Liaw to form the separation region comprises external corners adjacent to the third active fin, and internal corners adjacent to the second active fin, and wherein the external corners comprise a convexly rounded portion in plan view, and the internal corners comprise a concavely rounded portion in plan view, as taught by Kim086, since an H-shaped fin structure (Kim086, paragraph 0054) is manufactured using the rectangular-shaped mandrels, each of the mandrels may have a rounded-rectangular shape in which each vertex of the rectangular-shaped mandrels is rounded, and thus, the subsequently-formed spacers may also have the rounded-rectangular shape such that a fin structure (Kim086, paragraph 0020) having a two-dimensional (2D) shape in the plan view should have a greater effective fin width (W.sub.eff) than the 1D-shaped fin. Allowable Subject Matter Claims 19-20 and 26 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Tokranov et al. (US 2021/0358865), discloses the first separation region (portion of 110 between 104J in Fig. 6) overlaps (see Fig. 6, wherein the portion of 110 between 104J vertically overlaps 104E) a central region of the third fin-type pattern (left 104H and 104E in Fig. 6) and the second separation region (portion of 110 between 104H in Fig. 6, paragraph 0038) overlaps (see Fig. 6, wherein portion of 110 between 104H vertically overlaps 104K) a central region of the second fin-type pattern (right 104J and 104K in Fig. 6) in a second direction (vertical direction in Fig. 6) that intersects the first direction (horizontal direction in Fig. 6), and the second fin-type patterns (right 104J and 104K in Fig. 6) overlaps the third fin-type pattern (left 104H and 104E in Fig. 6) in the second direction (vertical direction in Fig. 6) but fails to disclose the first separation region and the second separation region are arranged to not overlap each other in the first direction and the second direction. Additionally, the prior art does not teach or suggest a semiconductor device comprising: the first separation region and the second separation region are arranged to not overlap each other in the first direction and the second direction in combination with other elements of claim 19. A closest prior art, Tokranov et al. (US 2021/0358865), discloses a semiconductor device comprising: a first active fin (104J and 104K in Fig. 6, paragraph 0037) extending in a first direction (horizontal direction in Fig. 6) and having first (left 104J in Fig. 6) and second fin-type patterns (right 104J and 104K in Fig. 6) separated (see Fig. 6, wherein 104J is separated in horizontal direction) from each other in the first direction (horizontal direction in Fig. 6) by a first separation region (portion of 110 between 104J in Fig. 6, paragraph 0038); a second active fin (104H and 104E in Fig. 6, paragraph 0037) extending in the first direction (horizontal direction in Fig. 6) and having third (left 104H and 104E in Fig. 6) and fourth fin-type patterns (right 104H in Fig. 6) separated (see Fig. 6, wherein 104H is separated in horizontal direction) from each other in the first direction (horizontal direction in Fig. 6) by a second separation region (portion of 110 between 104H in Fig. 6, paragraph 0038), wherein the first separation region (portion of 110 between 104J in Fig. 6) overlaps (see Fig. 6, wherein the portion of 110 between 104J vertically overlaps 104E) a central region of the third fin-type pattern (left 104H and 104E in Fig. 6) and the second separation region (portion of 110 between 104H in Fig. 6, paragraph 0038) overlaps (see Fig. 6, wherein portion of 110 between 104H vertically overlaps 104K) a central region of the second fin-type pattern (right 104J and 104K in Fig. 6) in a second direction (vertical direction in Fig. 6) that intersects the first direction (horizontal direction in Fig. 6), and the second fin-type patterns (right 104J and 104K in Fig. 6) overlaps the third fin-type pattern (left 104H and 104E in Fig. 6) in the second direction (vertical direction in Fig. 6); a third active fin 104B (Fig. 6, paragraph 0037) extending in the first direction (horizontal direction in Fig. 6) adjacent to the first active fin (104J and 104K in Fig. 6); a fourth active fin 104A (Fig. 6, paragraph 0037) extending in the first direction (horizontal direction in Fig. 6) adjacent to the second active fin (104H and 104E in Fig. 6); first gate lines (first column of 130 from the left corner of Fig. 6, paragraph 0027) extending in the second direction (vertical direction in Fig. 6) and intersecting the third active fin 104B (Fig. 6) and overlapping portions of the second (right 104J and 104K in Fig. 6) and third fin-type patterns (left 104H and 104E in Fig. 6); and second gate lines (second column of 130 from the left corner of Fig. 6, paragraph 0027) extending in the second direction (vertical direction in Fig. 6) and intersecting the fourth active fin 104A (Fig. 6) and the overlapping portions of the second (right 104J and 104K in Fig. 6) and third fin-type patterns (left 104H and 104E in Fig. 6) but fails to teach the first separation region and the second separation region are arranged to not overlap each other in the first direction and the second direction; a first trench region between the first and second active fins and having a first depth that is smaller than a depth of the first and second separation regions; a second trench region between the first and third active fins and having a second depth that is greater than the first depth; a third trench region between the second and fourth active fins and having a third depth that is greater than the first depth as the context of claim 19. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 20 and 26 depend on claim 19. Response to Arguments 1. Applicant's arguments filed 7/2/2026 have been fully considered. 2. The applicant argues (REMARKS, second paragraph in page 9) that “Chin further describes a separation region between two fins. Id. The Office action alleges that the top portion of the separation region of Chin is a first separation region and the bottom portion of the separation region of Chin is a second separation region. One or ordinary skill in the art, in view of the specification understands that the separation region of Chin is the entire separation region and cannot be arbitrary split up into a top half and a bottom half. However, even if, arguendo, the separation region of Chin were divided into a top region and a bottom region, Chin does not teach or suggest an entirety of the first separation region arranged to not overlap an entirety of the second separation region. Thus, Chin does not teach or suggest "wherein an entirety of the first separation region and an entirety of the second separation region are arranged to not overlap each other in a second direction," as set forth in claim 1.” However, 56 in Fig. 23A of Chin et al. (US 20240021618) (hereafter Chin) can have multiple regions. In addition, the claim filed on 7/2/2026 did not disclose a limitation preventing 56 in Fig. 23A of Chin having multiple regions. Therefore, Chin discloses an entirety of the first separation region (lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A) and an entirety of the second separation region (upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A) are arranged to not overlap (see Fig. 23A, wherein an entirety of lower portion of 56 between left 52 of 53B and right 52 of 53B in Fig. 23A does not overlap an entirety of upper portion of 56 between leftmost 52 and middle 52 of 53C in Fig. 23A) each other in a second direction (horizontal direction in Fig. 23A) that intersects the first direction (stacking direction in Fig. 23A). 3. Applicant's arguments with respect to claims 14-18 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM. 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /L.B.K/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813