Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al CN113517281A, and in view of Yang et al US 20220367702 A1. Huang et al and Yang et will be referenced to as Huang and Yang respectively henceforth.
Regarding Claim 1,
Huang teaches:
“A semiconductor device comprising:
a cell (FIG. 1I) comprising a stack of structures stacked in a first direction (N-FET N1, P-FET P1, [0018], [0044], [0050], FIG. 1I: The first direction is vertical.), wherein the stack of structures comprises:
a first transistor ( P-FET P1, [0018], [0044], [0050], FIG. 1I, annotated FIG. 31. : 260-1 and 260-2 may each be doped n-type or p-type.);
a second transistor, wherein the first transistor is stacked [[on]] offset in the first direction from the [[a]] second transistor (N-FET N1, [0018], [0044], [0050], FIG. 1I, annotated FIG. 31: 260-1 and 260-2 may each be doped n-type or p-type. Though FIG. 1I shows N1 on P1 rather than P1 on N1, P1 on N1 may be done in another embodiment. The transistors are stacked vertically.), and a power rail layer (backside power rail 284, via 282, [0067-0068] FIG. 31) comprising a first buried power rail (via 282, [0067], FIG. 31)”
Huang doesn’t substantially teach:
“wherein the first transistor is offset in a second direction from the second transistor, wherein the first direction is normal to the second direction, and wherein the first transistor is not in direct contact with the second transistor; and
a second buried power rail, wherein the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor,”
However, Yang teaches:
“wherein the first transistor is offset in a second direction from the second transistor (Yang: [0046], FIG. 1A: 102A is offset horizontally from 102B. The second direction is horizontal.), wherein the first direction is normal to the second direction (horizontal is normal to vertical.), and wherein the first transistor is not in direct contact with the second transistor (Yang: FIG. 1A); and a second buried power rail (Yang: source/drain interconnect 103, [0029], FIG. 1A), wherein the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor (Yang: [0029], FIG. 1A: The coupling must be done by a fabrication system. The coupling between the first buried power rail and the first transistor is electronic and physical. The coupling between the second buried power rail and the second transistor is electronic and physical.) wherein the first buried power rail is offset in the second direction from the second buried power rail (Yang: FIG. 1A: 103 and 105 are offset horizontally from each other.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Huang is modifiable in view of Yang.
This is because one of ordinary skill in the art would recognize that individually connecting a PFET and an NFET (Yang: [0030]: 102A and 102B may be a PFET and NFET respectively.) to S/D power lines provides increased control to the PFET and NFET. This is because these individual connections reduce electrical interference from a PFET to an NFET and vice versa because these connections are spaced away from the transistor device they are not connected to. There is space for these individual connections in the device because of the offset of the PFET and NFET.
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Annotated FIG. 31
Regarding Claim 2,
Huang/Yang teaches:
“The semiconductor device of claim 1, wherein the first transistor is a p-channel field-effect transistor (PFET) (Huang: [0018]: P1 is a P-FET.).”
Regarding Claim 3,
Huang/Yang teaches:
“The semiconductor device of claim 1, wherein the second transistor is an n-channel field-effect transistor (NFET) (Huang: [0018]: N1 is a N-FET.). ”
Regarding Claim 4,
Huang/Yang teaches:
“The semiconductor device of claim 1 wherein the stack of structures further comprises[[ing]]:
a gate structure (Yang: gate structure, [0024], FIG. 1A) that couples the first transistor to the second transistor (Yang: [0029], FIG. 1A: the gate structure physically and electrically couples the first and second transistor.);
And a voltage (Huang: layer 277, [0060], FIG. 31: Power enters the device on backside power rail side and exits on the frontside.), (Huang: [0060]: 277 includes interconnects electrically connecting transistors. Further, 277 is the voltage out for 200.). ”
Regarding Claim 5,
Huang/Yang teaches:
“The semiconductor device of claim 1, wherein the power rail layer is coupled to a powered back-side delivery network located on a back-side of the semiconductor device (Huang: backside interconnects 286, [0068], FIG. 31: 284 may be considered to be a part of 286.).”
Regarding Claim 6,
Huang/Yang teaches:
“The semiconductor device of claim 1, wherein the first buried power rail and the second buried power rail are spaced unevenly within [[a]] the cell (Yang: FIG. 1A: 103 lies within the gate structure and 105 does not. Therefore, relative to the gate structure, 103 and 105 are unevenly spaced. This unevenness is motivated by the need for connection between 103 and 102B and 105 and 102A as seen in FIG. 1A.).”
Claims 7-8, and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang/Yang as applied to claims 1-6 above, and further in view of Lilak et al US 20200294998 A1. Lilak et al will be referenced to as Lilak henceforth.
Regarding Claim 7,
Huang/Yang teaches:
“A method for fabricating a semiconductor device by a fabrication system (Huang: a method of fabricating a semiconductor device 100, [0021], FIGs. 2A-2D), the method comprising:
forming, by the fabrication system, a cell of the semiconductor device (Huang: FIG. 1I) comprising a stack of structures stacked in a first direction (Huang: N-FET N1, P-FET P1, [0018], [0044], [0050], FIG. 1I: The first direction is vertical.), wherein forming the stack of structures comprises:
forming, by the fabrication system, a transistor region (Huang: semiconductor fins 218, [0023], FIG. 4B) on a substrate (Huang: substrate 201, [0023], FIG. 4B), wherein the transistor region comprises:
a first transistor (Huang: P-FET P1, [0018], [0044], [0050], FIG. 1I, annotated FIG. 31. : 260-1 and 260-2 may each be doped n-type or p-type.), and
a second transistor, wherein the first transistor is stacked offset in the first direction from the second transistor (Huang: N-FET N1, [0018], [0044], [0050], FIG. 1I, annotated FIG. 31: 260-1 and 260-2 may each be doped n-type or p-type. Though FIG. 1I shows N1 on P1 rather than P1 on N1, P1 on N1 may be done in another embodiment. The transistors are stacked vertically.), wherein the first transistor is offset in a second direction from the second transistor (Yang: [0046], FIG. 1A: 102A is offset horizontally from 102B. The second direction is horizontal.), wherein the first direction is normal to the second direction (horizontal is normal to vertical.), and wherein the first transistor is not in direct contact with the second transistor (Yang: FIG. 1A);
forming, by the fabrication system, an interconnect hierarchy on a top side of the transistor region (Huang: layer 277, [0060], FIG. 23: 277 contains an interconnect hierarchy on the front side of the device on top of the transistor region.); flipping, by the fabrication system, the semiconductor device onto the carrier wafer (Huang: carrier 370, [0061], FIG. 24: the device 200 is flipped onto the carrier wafer);
removing, by the fabrication system, the substrate (Huang: [0062], FIG. 25: The substrate is removed to expose 204, 239 and 230.);
and forming, by the fabrication system, two or more buried power rails within [[a]] the cell (Huang/Yang: Huang: [0067], FIGs. 29-30: Huang teaches the fabrication of 282 after the removal of the substrate.; Yang: source/drain interconnects 103 and 105, [0029], FIG. 1A: Yang teaches two buried power rails formed in a cell.) wherein the two or more buried power rails comprise:
a first buried power rail (Huang: via 282, [0067], FIG. 31) and a second buried power rail (Yang: source/drain interconnect 103, [0029], FIG. 1A), wherein the first buried power rail is coupled to the first transistor (Huang: FIG. 31: via 282 is electrically coupled with the first transistor.), and the second buried power rail is coupled to the second transistor (Yang: FIG. 1A: The second buried power rail is electrically coupled to the second transistor.), wherein the first buried power rail is offset in the second direction from the second buried power rail (Yang: FIG. 1A: 103 and 105 are horizontally offset from each other.).”
Huang/Yang doesn’t substantially teach:
“forming, by the fabrication system, a carrier wafer on top of the interconnect hierarchy;”
However, Lilak teaches:
“forming, by the fabrication system, a carrier wafer on top of the interconnect hierarchy (Lilak: temporary substrate, [0048]);”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Huang/Yang is modifiable in view of Lilak.
This is because Lilak teaches that a temporary substrate, a carrier wafer, may be bonded to the frontside of a semiconductor device to provide protection during the flipping process. Therefore, one of ordinary skill in the art would bond the substrate prior to flipping to protect further protect their semiconductor device physical damage.
Regarding Claim 8,
Huang/Yang/Lilak teaches:
“The method of claim 7, further comprising: coupling, by the fabrication system, the two or more buried power rails to a powered back-side delivery network located on a back-side of the semiconductor device (Huang: backside interconnects 286, [0068], FIG. 31: 284 may be considered to be a part of 286.).”
Regarding Claim 11,
Huang/Yang/Lilak teaches:
“The method of claim [[9]] 7, wherein the first transistor comprises at least one of a PFET or a NFET (Huang: [0018]: P1 is a P-FET.).”
Regarding Claim 12,
Huang/Yang/Lilak teaches:
“The method of claim [[9]] 7, wherein the second transistor comprises at least one of a NFET or PFET (Huang: [0018]: N1 is a N-FET.).”
Regarding Claim 13,
Huang/Yang/Lilak teaches:
“The method of claim [[9]] 7, wherein the transistor region further comprises a gate structure (Yang: gate structure, [0024], FIG. 1A) coupling the first transistor to the second transistor (Yang: [0029], FIG. 1A: the gate structure physically and electrically couples the first and second transistor.). ”
Regarding Claim 14,
Huang/Yang/Lilak teaches:
“The method of claim [[10]] 7. wherein the first buried power rail and the second buried power rail are spaced unevenly within the cell (Yang: FIG. 1A: 103 lies within the gate structure and 105 does not. Therefore, relative to the gate structure, 103 and 105 are unevenly spaced. This unevenness is motivated by the need for connection between 103 and 102B and 105 and 102A as seen in FIG. 1A.).”
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak and further in view of Huang and Yang.
Regarding Claim 15,
Lilak teaches:
“A method for fabricating a semiconductor device by a fabrication system (a method of fabricating a semiconductor device 100, [0021], FIGs. 2A-2D), the method comprising:
forming, by the fabrication system, a stack of structures of a cell (first PMOS, first NMOS, [0021],[0027], [0048], Lilak: annotated FIG. 1A: The gate electrode of the lower structure is optimized for a NMOS device. This optimization is done because the lower structure includes a NMOS device. The upper device region 108 may be stacked and bonded on the lower device region 104. Given that the first PMOS is part of 108 and the first NMOS is part of 104, then the first PMOS is stacked on the first NMOS.) of the semiconductor device, wherein the forming comprises:
forming (first PMOS, [0021], Lilak: annotated FIG. 1A: The gate electrode of the upper structure is optimized for a PMOS device. This optimization is done because the upper structure includes a PMOS device.) forming a second transistor (first NMOS, [0027], [0048], Lilak: annotated FIG. 1A: The gate electrode of the lower structure is optimized for a NMOS device. This optimization is done because the lower structure includes a NMOS device. The upper device region 108 may be stacked and bonded on the lower device region 104. Given that the first PMOS is part of 108 and the first NMOS is part of 104, then the first PMOS is stacked on the first NMOS.),”
Lilak doesn’t substantially teach:
“forming, by the fabrication system, a power rail layer”
However, Huang teaches:
“forming, by the fabrication system, a power rail layer (Huang: backside power rail 284, [0068], FIG. 30) of the cell (Huang: FIG. 30, annotated FIG. 31 #1: The power rail layer is coupled to the structures stacked in a first direction, wherein the stack comprises N1 and P1.)”
Neither Lilak nor Huang substantially teach:
“wherein the first transistor is stacked offset in the first direction from the second transistor, wherein the first transistor is offset in a second direction from the second transistor,
wherein the first direction is normal to the second direction, and wherein the first transistor is not in direct contact with the second transistor;
wherein the power rail layer comprises[[ing]] a first buried power rail and a second buried power rail;
and coupling, by the fabrication system, the first buried power rail to the first transistor and the second buried power rail to the second transistor, wherein the first buried power rail is offset in the second direction from the second buried power rail.”
However, Yang teaches:
“wherein the first transistor is stacked offset in the first direction from the second transistor (Yang: [0046], FIG. 1A: 102B is vertically offset from 102A. The first direction is vertical.), wherein the first transistor is offset in a second direction from the second transistor(Yang: [0046], FIG. 1A: 102A is horizontally offset from 102B. The first direction is vertical.),
wherein the first direction is normal to the second direction (horizontal is normal to vertical.), and wherein the first transistor is not in direct contact with the second transistor (Yang: FIG. 1A);
wherein the power rail layer comprises[[ing]] a first buried power rail and a second buried power rail (Huang/Yang: Yang: S/D interconnect 103, [0046], FIG. 1A: 103 is buried in 106 and provides power to 102A. Therefore 105 is electrically and physically coupled to 102A. One of ordinary skill in the art would recognize that power rail layers would be within a power rail layer.);
and coupling, by the fabrication system, the first buried power rail to the first transistor and the second buried power rail to the second transistor (Yang: [0029], FIG. 1A: The coupling must be done by a fabrication system.), wherein the first buried power rail is offset in the second direction from the second buried power rail (Yang: FIG. 1A: 103 and 105 are horizontally offset from each other.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lilak is modifiable in view of Huang.
This is because one of ordinary skill in the art would recognize that the backside power rail 284 of Huang provides the advantage of increasing the number of metal tracks for direct connection of source/drain contacts and vias, increasing the gate density for greater device integration, and reducing the resistance of the backside power rail given that the backside power rail has a greater width than the front side metal layers (Huang: [0068]).
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lilak/Huang is modifiable in view of Yang.
This is because one of ordinary skill in the art would recognize that individually connecting a PFET and an NFET (Yang: [0030]: 102A and 102B may be a PFET and NFET respectively.) to S/D power lines provides increased control to the PFET and NFET. This is because these individual connections reduce electrical interference from a PFET to an NFET and vice versa because these connections are spaced away from the transistor device they are not connected to. There is space for these individual connections in the device because of the offset of the PFET and NFET.
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Lilak: Annotated FIG. 1A #1
Regarding Claim 16,
Lilak/Huang/Yang teaches:
“The method of claim 15 further comprising: coupling, by the fabrication system, a first end of a gate structure to the first transistor (Yang: annotated FIG. 1A #1);
and coupling, by the fabrication system, a second end of the gate structure to the second transistor (Yang: annotated FIG. 1A #1).”
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Yang: Annotated FIG. 1A #1
Regarding Claim 17,
Lilak/Huang/Yang teaches:
“The method of claim 15, wherein the first transistor is a p-channel field-effect transistor (PFET) (Lilak: first PMOS is a P-FET.).”
Regarding Claim 18,
Lilak/Huang/Yang teaches:
“The method of claim 15, wherein the second transistor is an n-channel field-effect transistor (NFET) (Huang: [0018]: first NMOS is a N-FET.). ”
Regarding Claim 19,
Lilak/Huang/Yang teaches:
“The method of claim 15 further comprising: coupling, by the fabrication system, the power rail layer to a powered back-side delivery network (Huang: backside interconnects 286, [0068], FIG. 31: 284 may be considered to be a part of 286.).”
Regarding Claim 20,
Lilak/Huang/Yang teaches:
“The method of claim 15, wherein the first buried power rail and the second buried power rail are spaced unevenly within [[a]] the cell (Yang: FIG. 1A: 103 lies within the gate structure and 105 does not. Therefore, relative to the gate structure, 103 and 105 are unevenly spaced. This unevenness is motivated by the need for connection between 103 and 102B and 105 and 102A as seen in FIG. 1A.). ”
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Huang/Yang as applied to claims 1-6 above, and further in view of Narayan et al US 20230299068 A1. Narayan et al will be referenced to as Narayan henceforth.
Regarding Claim 21,
Huang/Yang teaches:
“The semiconductor device of claim 1,”
Huang/Yang doesn’t substantially teach alone:
“wherein the semiconductor device comprises a group of cells comprising the cell.”
However, Huang/Yang/Narayan teaches:
“wherein the semiconductor device comprises a group of cells comprising the cell (Huang/Yang/Narayan: Narayan: [0001-0003]: A cell is defined as a group of transistors, passive structures, and interconnects. Narayan teaches the use of a high cell density to form a computing device. One of ordinary skill in the art would therefore be motivated to repeat the cells of Huang/Yang/Narayan many times.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Huang/Yang is modifiable in view of Narayan.
This is because one of ordinary skill in the art understands that the use of many cells is needed to form a computationally powerful device. Therefore one of ordinary skill in the art would realize that the invention of Huang/Yang would be made many times in a single computing device to accomplish this goal.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Huang/Yang/Lilak as applied to claims 7-8 and 11-14 above, and further in view of Narayan.
Regarding Claim 22,
Huang/Yang/Lilak teaches:
“The method of claim 7,”
Huang/Yang/Lilak doesn’t substantially teach alone:
“wherein forming the cell comprises forming a group of cells comprising the cell.”
However, Huang/Yang/Lilak/Narayan teaches:
“wherein forming the cell comprises forming a group of cells comprising the cell (Huang/Yang/Narayan: Narayan: [0001-0003]: A cell is defined as a group of transistors, passive structures, and interconnects. Narayan teaches the use of high cell density to form a computing device.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Huang/Yang/Lilak is modifiable in view of Narayan.
This is because one of ordinary skill in the art understands that the use of many cells is needed to form a computationally powerful device. Therefore one of ordinary skill in the art would realize that the invention of Huang/Yang would be made many times in a single computing device to accomplish this goal.
Response to Arguments
Applicant’s amendments to the Claims have not overcome the Examiner’s 103 rejections.
During the Interview conducted on January 21 2026, the Examiner concluded that the amendments overcame the prior art rejection. This is because the Examiner believed that the second direction in, “wherein the first buried power rail is offset in the second direction from the second buried power rail” was vertical. However, upon further examination, the Examiner noticed that the second direction is horizontal and not vertical. This is because the semiconductor structures are stacked in the first direction, and therefore the first direction is vertical. The second direction and the first direction are normal to each other, and therefore the second direction is horizontal. In the prior art references, buried power rails are horizontally offset to each other.
The Examiner did search for the case in which the second direction is vertical and the first direction is horizontal, wherein the stack of structures is stacked in the second direction, as was suggested in the interview. The Examiner found US 20170141033 A1, and believes that this reference in combination with the prior references cited covers this case. For this reason, the Examiner suggests the Applicant amend the claims with limitations in addition to the amendments suggested in the interview.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the limitations of claim 21 in addition to the following limitation:
“wherein each cell in the plurality of cells is separated by a first gate cut and a second gate cut, wherein the first gate cut is stacked offset in the second direction from the second transistor, wherein the first transistor is stacked offset in the second direction from the second gate cut”
It would overcome the current rejections for the independent claims. The Examiner intends the second direction to be the vertical direction in the limitation written above. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812