DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 12/29/2025 in which claims 1, 2, 5, 8-15, and 17 were amended and claims 4, 6, 7, and 16 were cancelled.
Claims 1-3, 5, 8-15, and 17 are pending with claims 3, 5, 9, 10, 15, and 17 remain pending and claims 1, 2, 8, and 11-14 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yanagigawa (US 2016/0308529 and Yanagigawa hereinafter) in view of Tsukuda et al (US 6,054,748 and Tsukuda hereinafter).
As to claims 1, 2, 8, and 11: Yanagigawa discloses [claim 1] a semiconductor device (Fig. 4) comprising: a lead frame (Fig. 2; LEF; [0051]) or a metal back surface; a semiconductor substrate (comprising SUB and NEL; [0055]) having a first main surface (top of NEL, in which SN and PP are formed; [0055]-[0059]) and a second main surface (bottom of SUB) opposite to each other, the semiconductor substrate (SUB) being mounted on the lead frame (LEF) or on the metal back surface; a first region (EFR1; [0056]) and a second region (EFR2; [0055]) each defined in the semiconductor substrate (comprising SUB and NEL); a first switching element (Q1; [0056]) formed in the first region (EFR1) and configured to perform current conduction (vertical transistor structure; [0012] and [0055]) between the first main surface (top of NEL) and the second main surface (bottom of SUB); and a second switching element (Q2; [0056]) formed in the second region (EFR2) and connected in anti-series (Fig. 1; the circuit diagram shows the same diagram as disclosed and identified as “anti-series” in the instant specification, therefore, the structure of Figs. 1 and 4 of Yanagigawa is in “anti-series; [0049]-[0050]) to the first switching element (Q1); a first plug (Fig. 13; AH in openings in ZF in EFR1; [0068]) formed in the first region (EFR1) so as to penetrate an interlayer insulating film (ZF; [0067]); a second plug (Fig. 13; AH in openings in ZF in EFR2; [0068]) formed in the second region (EFR2) so as to penetrate the interlayer insulating film (ZF); a first source electrode (Fig. 13; AH outside of openings in ZF in EFR1; [0068]) formed in the first region (EFR1) so as to cover the interlayer insulating film (ZF); and a second source electrode (Fig. 13; AH outside of openings in ZF in EFR2; [0068]) formed in the second region (EFR2) so as to cover the interlayer insulating film (ZF), wherein the semiconductor substrate (comprising SUB and NEL) includes: a substrate body (SUB) of an N-type (n-type; [0055]) having the second main surface (bottom of SUB), the substrate body (SUB) being arranged so as to be in contact with the lead frame (LEF) or the metal back surface in the first region (EFR1) and in the second region (EFR2); and a semiconductor layer (NEL) of the N-type (n-type; [0055]), the semiconductor layer (NEL) being formed so as to be in contact with the substrate body (SUB), and the semiconductor layer (NEL) having the first main surface (top of NEL), wherein the first switching element (Q1) comprises: a first electrode (GE; [0057]) formed in a first trench (TRC; [0057]) formed in the semiconductor layer (NEL) with a first insulating film (GZ; [0057]) interposed therebetween; a first impurity region's (PM; [0057]) first portion (in EFR1) of a P-type (p-type; [0057]) formed in the semiconductor layer (NEL) so as to be in contact with the first insulating film (GZ) and formed from the first main surface (top of NEL) to a position shallower than a bottom of the first electrode (GE); and a second impurity region's (SN; [0057]) first portion (in EFR1) of the N-type (n-type; [0057]) formed in the first impurity region's (PM) first portion (in EFR1) so as to formed from the first main surface (top of NEL) to a position shallower than a bottom of the first impurity region's (PM) first portion (in EFR1); wherein the second switching element (Q2) comprises: a second electrode (GE; [0058]) formed in a second trench (TRC; [0058]) formed in the semiconductor layer (NEL) with a second insulating film (GZ; [0058]) interposed therebetween; a first impurity region's (PM; [0059]) second portion (in EFR2) of the P-type (p-type; [0059]) formed in the semiconductor layer (NEL) so as to be in contact with the second insulating film (GZ) and formed from the first main surface (top surface of NEL) to a position shallower than a bottom of the second electrode (GE); and a second impurity region's (SN; [0059]) second portion (in EFR2) of the N-type (n-type; [0059]) formed in the first impurity region's (PM) second portion (in EFR2) so as to extend from the first main surface (top surface of NEL) to a position shallower than a bottom of the first impurity region's (PM) second portion (in EFR2), wherein, in the semiconductor layer (NEL), a thickness (ELT1; [0055]) of a portion located in the first region (EFR1) and where the current conduction by the first switching element (Q1) is performed is a first thickness (ELT1), wherein, in the semiconductor layer (NEL), a thickness (ELT2; [0055]) of a portion located in the second region (Q2) and where current conduction by the second switching element (Q2) is performed is a second thickness (ELT2); [claim 2] wherein the first main surface (top surface of NEL) of the semiconductor substrate (comprising SUB and NEL) includes: a first main surface's first portion (portion of NEL in EFR1) located in the first region (EFR1); and a first main surface's second portion (portion of NEL in EFR2) located in the second region; [claim 8] wherein the second switching element (Q2) includes a second columnar body (CLM; [0059]) of the P-type (p-type; [0059] and [0063]) extending from the first impurity region's (PM) second portion (in EFR2) toward the substrate body (SUB); [claim 11] wherein the lead frame (Fig. 2; LEF; [0051]) is arranged on the second main surface (bottom surface) of the semiconductor substrate (SUB).
Yanagigawa fails to expressly disclose [claim 1] wherein the first thickness is less than the second thickness; [claim 2] wherein the first main surface's first portion is located closer to the second main surface than the first main surface's second portion.
Yanigigawa discloses in [0089] that it is desirable to reduce the on-resistance of the transistor Q1 in region EFR1 from the embodiment described in Fig. 4. Yanigigawa discloses a means to reduce the on-resistance of Q1 in EFR1 by changing the depth of the body region PM of Q1 relative to Q2.
Tsukuda discloses a substrate with two semiconductor switches therein, see Fig. 56 and col. 25, lines 12-34. Tsukuda discloses that for vertical MOSFETs, when the on-resistance is desired to be reduced of one transistor relative to another transistor, the thickness of the semiconductor layer 61 (equivalent to the semiconductor layer NEL of Yanagigawa) can be reduced of the one transistor relative to the thickness of the semiconductor layer 61 of the another transistor.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to reduce the thickness of NEL in EFR1 for transistor Q1 relative to the thickness of NEL in EFR2 for transistor Q2 (instead of changing the thickness of the body region PM), thereby improving the embodiment of Fig. 4 of Yanagigawa because the technique for reducing the on-resistance of Q1 relative to Q2 by removing a thickness from the top surface of the semiconductor layer NEL (whereby the first main surface in EFR1 is closer to the second main surface than the first main surface in EFR2) was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of Tsukuda for improving the on-resistance of one vertical transistor relative to another vertical transistor by removing a thickness from a top surface of the semiconductor layer 61 and the application of which would have resulted in the desirable and predictable results of having the on-resistance of Q1 reduced while keeping the on-resistance of Q2 the same as before (or higher than the modified Q1).
As to claims 13 and 14: Yanagigawa discloses [claim 13] a method of manufacturing a semiconductor device (Fig. 4), the method comprising: preparing a semiconductor substrate (comprising SUB and NEL; [0055]) having a first main surface (top of NEL in which SN and PP are formed; [0055]-[0059]) and a second main surface (bottom of SUB) opposite to each other, wherein a first region (EFR1; [0056]) and a second region (EFR2; [0056]) are each defined in the semiconductor substrate (comprising SUB and NEL), wherein the semiconductor substrate (comprising SUB and NEL) includes a substrate body (SUB; [0055]) of an N-type (n-type; [0055]) and a semiconductor layer (NEL; [0055]) of the N-type (n-type; [0055]), wherein the substrate body (SUB) has the second main surface (bottom of SUB), wherein the semiconductor layer (NEL) is formed so as to be in contact with the substrate body (SUB), and wherein the semiconductor layer (NEL) has the first main surface (top of NEL); forming a first switching element (Q1; [0056]) in the first region (EFR1) of the semiconductor substrate (comprising SUB and NEL), and forming a second switching element (Q2; [0056]) in the second region (EFR2) of the semiconductor substrate (comprising SUB and NEL), the first switching element (Q1) being configured to perform current conduction (inherent to the operation of the vertical transistor Q1) between the first main surface (top of NEL) and the second main surface (bottom of SUB), the second switching element (Q2) connected in anti-series (Fig. 1; the circuit diagram shows the same diagram as disclosed and identified as “anti-series” in the instant specification, therefore, the structure of Figs. 1 and 4 of Yanagigawa is in “anti-series; [0049]-[0050]) to the first switching element (Q1); the first thickness (ELT1; [0055]) being a thickness of a portion in the semiconductor layer (NEL) located in the first region (EFR1) and where the current conduction by the first switching element (Q1) is performed, and the second thickness (ELT2; [0055]) being a thickness of a portion in the semiconductor layer (NEL) located in the second region (EFR2) and where current conduction by the second switching element (Q2) is performed; forming an interlayer insulating film (Fig. 11; ZF; [0067]) so as to cover the first main surface (top of NEL in which SN and PP are formed) of the semiconductor substrate (comprising SUB and NEL); forming a first plug (Fig. 12; AH in openings in ZH in EFR1; [0068]) in the first region (EFR1) so as to penetrate the interlayer insulating film (ZF) and forming a second plug (AH in openings in ZH in EFR2; [0068]) in the second region (EFR2) so as to penetrate the interlayer insulating film (ZF); forming a first source electrode (Fig. 13; AH outside of openings in ZF in EFR1; [0068]) in the first region (EFR1) so as to cover the interlayer insulating film (ZF) and forming a second source electrode (Fig. 13; AH outside of openings in ZF in EFR2; [0068]) in the second region (EFR2) so as to cover the interlayer insulating film (ZF); and mounting the semiconductor substrate (comprising SUB and NEL) on a lead frame (Fig. 2; LEF; [0051]) or on a metal back surface such that the second main surface (bottom of SUB) is in contact with the lead frame (LEF) or the metal back surface, wherein forming the first switching element (Q1) comprises: forming a first electrode (Fig. 4; GE in EFR1; [0057]) in a first trench (TRC; [0057]) formed in the semiconductor layer (NEL) with a first insulating film (GZ; [0057]) interposed therebetween; forming a first impurity region's (PM; [0057]) first portion (in EFR1) of a P-type (P-type; [0057]) in the semiconductor layer (NEL) so as to be in contact with the first insulating film (GZ) and formed from the first main surface (top of NEL) to a position shallower than a bottom of the first electrode (GE); and forming a second impurity region's (SN; [0057]) first portion (in EFR1) of the N-type (N-type; [0057]) in the first impurity region's (PM) first portion (in EFR1) so as to be formed from the first main surface (top of NEL) to a position shallower than a bottom of the first impurity region's (PM) first portion (in EFR1), and wherein forming the second switching element (Q2) comprises: forming a second electrode (GE; [0058]) in a second trench (TRC; [0058]) formed in the semiconductor layer (NEL) with a second insulating film (GZ; [0058]) interposed therebetween; forming a first impurity region's (PM; [0059]) second portion (in EFR2) of the P-type (P-type; [0059]) in the semiconductor layer (NEL) so as to be in contact with the second insulating film (GZ) and formed from the first main surface (top surface of NEL) to a position shallower than a bottom of the second electrode (GE); and forming a second impurity region's (SN; [0059]) second portion (in EFR2) of the N-type (N-type; 0059]) in the first impurity region's (PM) second portion (in EFR2) so as to extend from the first main surface (top of NEL) to a position shallower than a bottom of the first impurity region's (PM) second portion (in EFR2); [claim 14] wherein, in preparing the semiconductor substrate (comprising SUB and NEL), a first main surface's (top surface of NEL) first portion (in EFR1) is defined in the first region (EFR1) of the first main surface (top surface of NEL), and a first main surface's (top surface of NEL) second portion (in EFR2) is defined in the second region (EFR2) of the first main surface (top surface of NEL).
Yanagigawa fails to expressly disclose [claim 13] making a first thickness less than a second thickness; [claim 14] wherein, in the step of making the first thickness less than the second thickness, the first main surface's first portion is subjected to an etching process such that the first main surface's first portion is made to be closer to the second main surface than the first main surface's second portion.
Yanigigawa discloses in [0089] that it is desirable to reduce the on-resistance of the transistor Q1 in region EFR1 from the embodiment described in Fig. 4. Yanigigawa discloses a means to reduce the on-resistance of Q1 in EFR1 by changing the depth of the body region PM of Q1 relative to Q2.
Tsukuda discloses a substrate with two semiconductor switches therein, see Fig. 56 and col. 25, lines 12-34 and col. 21, lines 59-65. Tsukuda discloses that for vertical MOSFETs, when the on-resistance is desired to be reduced of one transistor relative to another transistor, the thickness of the semiconductor layer 61 (equivalent to the semiconductor layer NEL of Yanagigawa) can be reduced of the one transistor relative to the thickness of the semiconductor layer 61 of the another transistor by etching from the top surface of the semiconductor layer 61 into the semiconductor layer 61 in the first region 60b of the first switching element.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to reduce the thickness of NEL in EFR1 for transistor Q1 relative to the thickness of NEL in EFR2 for transistor Q2 (instead of changing the thickness of the body region PM), thereby improving the embodiment of Fig. 4 of Yanagigawa because the technique for reducing the on-resistance of Q1 relative to Q2 by removing a thickness from the top surface of the semiconductor layer NEL (whereby the first main surface in EFR1 is closer to the second main surface than the first main surface in EFR2) was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of Tsukuda for improving the on-resistance of one vertical transistor relative to another vertical transistor by removing a thickness from a top surface of the semiconductor layer 61 and the application of which would have resulted in the desirable and predictable results of having the on-resistance of Q1 reduced while keeping the on-resistance of Q2 the same as before (or higher than the modified Q1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yanigigawa in view of Tsukuda as applied to claim 1 above, and further in view of Mojab et al (“Design and Characterization of High-Current Optical Darlington Transistor for Pulsed-Power Applications” and Mojab hereinafter).
Although the structure disclosed by Yanigigawa in view of Tsukuda shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
wherein the substrate body of the N-type has a higher impurity concentration than the semiconductor layer of the N-type.
Mojab discloses on page 2, section A that the substrate for a power transistor is a highly doped n+ type wafer and the drift layer (claimed semiconductor layer) is a lightly doped layer.
Given the teachings of Mojab, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Yanigigawa in view of Tsukuda by employing the well-known or conventional features of power transistor fabrication, such as displayed by Mojab, by employing the substrate body as highly doped and the semiconductor layer as lightly doped in order to provide layers that can form a blocking layer in high power applications with a desired resistivity and breakdown voltage (page 2, section A).
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that Yanagigawa in view of Tsukudad fail to disclose wherein the first thickness is less than the second thickness. Tsukuda teaches reducing the thickness of the semiconductor substrate in the MOSFET region while maintaining a greater thickness in the IGBT region. However, Yanigagawa does not disclose an IGBT and there is no motivation in Yanagigawa to selectively reduce the thickness in only one region as taught by Tsukuda.
Examiner respectfully traverses applicant’s remarks. Yanagigawa discloses a forming a substrate comprising two regions (EFR1 and EFR2) each with a vertical power transistor (Q1 and Q2, respectively), see the Abstract. Yanigigawa discloses in Fig. 20 a means to reduce the on-resistance of Q1 in EFR1 by changing the depth of the body region PM of Q1 relative to Q2. Tsukuda discloses a substrate with two vertical power transistors each in a different region (60a and 60b, respectively), see Fig. 56 and col. 25, lines 12-34 and col. 21, lines 59-65. Tsukuda discloses that for vertical MOSFETs, when the on-resistance is desired to be reduced of one transistor relative to another transistor, the thickness of the semiconductor layer 61 (equivalent to the semiconductor layer NEL of Yanagigawa) can be reduced of the one transistor relative to the thickness of the semiconductor layer 61 of the another transistor by etching from the top surface of the semiconductor layer 61 into the semiconductor layer 61 in the first region 60b of the first switching element. As stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the technique for improving a particular class of devices (in this case vertical power transistors with a trench gate structure where one region’s vertical transistor has a reduced on-resistance as in Yanigagawa where the on-resistance is decreased by reducing a thickness of the semiconductor layer in the reduced on-resistance region relative to the non-reduced thickness of the semiconductor layer in the other region as taught by Tsukuda instead of by modifying the depth of the p-type doped region as in Yanagigawa) was part of the ordinary capabilities of a person having ordinary skill in the art before the effective filing date of the claimed invention, in view of the teaching of the technique for improvement in other situations (a planar structure in Tsukuda having reduced on-resistance in a desired transistor area (compared to another transistor area) provided by reducing the thickness of the semiconductor layer in the area desired). Further, as the technique of reducing the thickness of the semiconductor layer in one vertical power transistor region compared to another vertical power transistor region to reduce the on-resistance in one transistor region of Tsukuda would be a simple substitution of the method of reducing the on-resistance in one vertical power transistor region compared to another by having different p-type doped region depths of Yanigagawa, KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007) provides a rationale for performing the substitution of one technique for another as they arrive at the same desired result (a difference in on-resistance between vertical power transistor regions).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/20/2026