Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to the applicants’ arguments filed on 09/29/2025, specifically on pages 2 and 3 regarding the usage of Ryu et al, the applicant correctly identifies the ohmic layers, elements 26a and 26b, as the bounds of the semiconductor sub-portion, element 22c, but does not disclose the semiconductor sub-layer extending beyond the conductor sub layers [elements 26a and 26b]. However, Ryu is still used in the rejection below, but in a different way to not teach such limitations of the semiconductor sublayer, but a separate reference teaches such limitations. However, the ohmic-layers as the conductor sublayer in Ryu et al is still used, and as the applicant does not address such usage, the amendment does overcome the prior art rejection by not letting Ryu et al read onto the limitations of the semiconductor sublayer specifically.
Additionally, the amendments to claims 1, 12, and 13 do overcome the previous prior art rejection, including the dependency of dependent claims upon such limitations explained in the amendments. However, though the references used to reject dependent claims, none of the arguments address the dependent references needing to overcome the amendments to the independent claims. Thus, such references are still used in the rejection below. Upon further consideration, a new rejection is formed upon a new base reference that addresses the amended limitations to the independent claims, claim 1, 12 and 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442) in view of Ryu et al (US 7923722).
Takechi et al teaches
[claim 1] A display panel, comprising a thin-film transistor, the thin-film transistor comprising an active portion, and a source electrode and a drain electrode that are contact-connected to the active portion (figure 14, col 16 lines 31-42, where the thin film transistor can be a part of a display panel, col 8 lines 37-45 where element 16 is the source and drain electrodes connected to an active portion [element 14]);
wherein the display panel further comprises: a substrate; a first metal layer disposed on the substrate and comprising the source electrode and the drain electrode (figure 14, col 8 lines 37-45 where element 16 is the source and drain electrodes connected to an active portion [element 14] and the substrate is element 10 and the source and drain electrodes are the first metal layer deposited on the substrate);
and an active layer disposed on a side of the first metal layer away from the substrate and comprising the active portion (figure 14, col 8 lines 37-45, where element 14 is deposited on the source and drain electrode [element 16] in a position away from the substrate [element 10]),
and the active portion comprising a semiconductor sublayer (figure 14, col 8 lines 37-45, element 14A and 14E is are the semiconductor sublayer which is apart of the active layer [element 14]);
the semiconductor sublayer comprises a first semiconductor subportion filled in the isolation groove and a second semiconductor subportion extending outside the isolation groove (col 8 lines 54-60, where element 14A is the first semiconductor subportion filled in an isolation groove [area between element 16], and the second semiconductor subportion extends outside the isolation groove [element 14E extends beyond the groove area and has an orthographic projection onto element 16]),
and an orthographic projection of the first semiconductor subportion on the substrate is within an orthographic projection of the second semiconductor subportion on the substrate (col 8 lines 54-60, where element 14A is the first semiconductor subportion filled in an isolation groove [area between element 16], and the second semiconductor subportion extends outside the isolation groove [element 14E extends beyond the groove area and has an orthographic projection onto element 16], thus the orthodgraphic projection of the element 14A onto the substrate [element 10] is within the orthographic projection of 14E [second semiconductor subsection] onto the substrate]).
However, Takechi et al does not specifically disclose
[claim 1] and the active portion comprising a conductor sublayer, wherein the conductor sublayer comprises a first conductor subsection and a second conductor subsection spaced apart from each other, and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection, wherein the conductor sublayer further comprises an isolation groove located between the first conductor subsection and the second conductor subsection, and the second subportion extends to a side of the first conductor sublayer and the second conductor sublayer away from the substrate respectively.
[claim 3] wherein the first conductor subsection extends to the source contact region, the second conductor subsection extends to the drain contact region, the source electrode is electrically connected to the first conductor subsection located in the source contact region, and the drain electrode is electrically connected to the second conductor subsection in the drain contact region.
However, Ryu et al does teach
[claim 1] and the active portion comprising a conductor sublayer, wherein the conductor sublayer comprises a first conductor subsection and a second conductor subsection spaced apart from each other (figure 2, col 5 line 60 – col 6 line 4, where element 26a and 26b comprise the first conductor sublayer attached to the active portion [element 22], and contains a first conductive subsection [element 26a] and a second conductor subsection [element 26b] spaced apart from each other),
and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection (figure 2, col 6 lines 18-37, where element 22c is the semiconductor sublayer and is connected between the first and second [element 26a and 26b respectively] conductive subsection),
wherein the conductor sublayer further comprises an isolation groove located between the first conductor subsection and the second conductor subsection (figure 2, where the groove between elements 26a and 26b is the isolation groove and maps onto the groove from the base reference of Takechi et al),
and the second subportion extends to a side of the first conductor sublayer and the second conductor sublayer away from the substrate respectively (figure 2, where the first and second semiconductor subsections from the base reference, Takechi et al, maps onto element 22c, thus element 14E of figure 14 in Takechi et al would extend beyond the first and second conductive subsections since the first and second conductor subsections are mapped onto the source and drain electrodes [elements 23a and 23b from Ryu et al map onto element 16 of figure 14 in Takechi et al, thus element 26a and 26b of Ryu et al also map onto the same dimensions of the source and drain electrodes]).
[claim 3] wherein the first conductor subsection extends to the source contact region, the second conductor subsection extends to the drain contact region, the source electrode is electrically connected to the first conductor subsection located in the source contact region, and the drain electrode is electrically connected to the second conductor subsection in the drain contact region (figure 2, col 5 lines 55 – col 6 line 4, figures 1 and 2 where elements 26a and 26b are the two conductor subsections and each is connected to the drain and source contact regions respectively [elements 23a and 23b respectively]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al to incorporate the teachings of Ryu et al in order to provide a conductor subsection attached to the active layer in order to minimize hole leakage from the channel layer (col 6 lines 1-4).
Regarding claim 2, Takechi et al further discloses
The display panel, wherein the active portion comprises a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region, wherein the isolation groove is located in the channel region (figure 14, col 8 lines 37-45, where element 16 is the source and drain contact region, element 14 is the channel region and is situated between element 16, of which the gap creates the isolation groove).
Regarding claims 12
Takechi et al teaches
[claim 12] A method of manufacturing a display panel, the display panel comprising a thin-film transistor, the thin-film transistor comprising an active portion, and a source electrode and a drain electrode that are contact-connected to the active portion (figure 14, abstract, col 16 lines 31-42, where a method making a thin-film-transistor is disclosed, where the thin film transistor can be a part of a display panel, col 8 lines 37-45 where element 16 is the source and drain electrodes connected to an active portion [element 14]);
and the method of manufacturing the display panel comprising: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer comprises a source electrode and a drain electrode (figures 9-14 [show the method], col 8 lines 37-45 where element 16 is the source and drain electrodes connected to an active portion [element 14] and the substrate is element 10 and the source and drain electrodes are the first metal layer deposited on the substrate);
forming an active layer disposed on a side of the first metal layer away from the substrate and comprising the active portion (figures 9-14, col 8 lines 37-45, where element 14 is deposited on the source and drain electrode [element 16] in a position away from the substrate [element 10]),
and the active portion comprising a semiconductor sublayer (figure 14, col 8 lines 37-45, element 14A and 14E is are the semiconductor sublayer which is apart of the active layer [element 14]);
the semiconductor sublayer comprises a first semiconductor subportion filled in the isolation groove and a second semiconductor subportion extending outside the isolation groove (col 8 lines 54-60, where element 14A is the first semiconductor subportion filled in an isolation groove [area between element 16], and the second semiconductor subportion extends outside the isolation groove [element 14E extends beyond the groove area and has an orthographic projection onto element 16]),
and an orthographic projection of the first semiconductor subportion on the substrate is within an orthographic projection of the second semiconductor subportion on the substrate (col 8 lines 54-60, where element 14A is the first semiconductor subportion filled in an isolation groove [area between element 16], and the second semiconductor subportion extends outside the isolation groove [element 14E extends beyond the groove area and has an orthographic projection onto element 16], thus the orthodgraphic projection of the element 14A onto the substrate [element 10] is within the orthographic projection of 14E [second semiconductor subsection] onto the substrate]).
However, Takechi et al does not specifically disclose
[claim 12] and the active portion comprising a conductor sublayer, wherein the conductor sublayer comprises a first conductor subsection and a second conductor subsection spaced apart from each other, and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection, wherein the conductor sublayer further comprises an isolation groove located between the first conductor subsection and the second conductor subsection, and the second subportion extends to a side of the first conductor sublayer and the second conductor sublayer away from the substrate respectively.
However, Ryu et al does teach
[claim 12] and the active portion comprising a conductor sublayer, wherein the conductor sublayer comprises a first conductor subsection and a second conductor subsection spaced apart from each other (figure 2, col 5 line 60 – col 6 line 4, where element 26a and 26b comprise the first conductor sublayer attached to the active portion [element 22], and contains a first conductive subsection [element 26a] and a second conductor subsection [element 26b] spaced apart from each other),
and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection (figure 2, col 6 lines 18-37, where element 22c is the semiconductor sublayer and is connected between the first and second [element 26a and 26b respectively] conductive subsection),
wherein the conductor sublayer further comprises an isolation groove located between the first conductor subsection and the second conductor subsection (figure 2, where the groove between elements 26a and 26b is the isolation groove and maps onto the groove from the base reference of Takechi et al),
and the second subportion extends to a side of the first conductor sublayer and the second conductor sublayer away from the substrate respectively (figure 2, where the first and second semiconductor subsections from the base reference, Takechi et al, maps onto element 22c, thus element 14E of figure 14 in Takechi et al would extend beyond the first and second conductive subsections since the first and second conductor subsections are mapped onto the source and drain electrodes [elements 23a and 23b from Ryu et al map onto element 16 of figure 14 in Takechi et al, thus element 26a and 26b of Ryu et al also map onto the same dimensions of the source and drain electrodes]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al to incorporate the teachings of Ryu et al in order to provide a conductor subsection attached to the active layer in order to minimize hole leakage from the channel layer (col 6 lines 1-4).
Claim(s) 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), and Ryu et al (US 7923722 B2) in view of Lee (US 20170294460 A1).
Regarding claims 4, Takechi et al as modified teaches all of the limitations of the parent claims, claim 2, but does not specifically disclose
[claim 4] The display panel of claim 2, wherein a length of the isolation groove in a first direction is less than a distance between the source contact region and the drain contact region, and the first direction is a direction in which the source contact region points to the drain contact region.
However, Lee does teach
[claim 4] wherein a length of the isolation groove in a first direction is less than a distance between the source contact region and the drain contact region, and the first direction is a direction in which the source contact region points to the drain contact region (paragraphs 0032 and 0065, where the isolation groove is the region between element 146 in TFT1 and when taken with an orthographic projection of the source and drain electrodes [elements 171 and 172] the isolation groove is smaller than the distance between the electrodes).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified with the teachings of Lee in order to maximize efficiency of isolating the conductive subsections by keeping the isolation trench large enough to not allow for any conduction between the source and drain but to lessen it to be shorten than the distance between the source and drain so as to maximize current flow through electrodes and minimize charge build up.
Regarding claim 5, Bae as modified lacks
[claim 5] The display device, wherein the length of the isolation groove in the first direction is less than or equal to 3 microns.
Per MPEP 2144.05 II under Routine Optimization, it would have been obvious to optimize the distance of the isolation trench to maximize efficiency of isolating the conductive subsections by keeping the isolation trench large enough to not allow for any conduction between the source and drain but to lessen it to be shorten than the distance between the source and drain so as to maximize current flow through electrodes and minimize charge build up. Since it is well known in the art that thin film transistors have layer thicknesses ranging from tenth of microns to single digit microns, to have a width of a trench proportional to such distances is reasonable for anyone skill in the art to try and start to optimize.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), and Ryu et al (US 7923722 B2) in further view of Xiao (US 20190221672 A1).
Takechi et al. as modified teaches all of the limitations of the parent claims, claims 2, additionally
Takechi et al as modified do not specifically disclose
[claim 6] wherein the thin-film transistor further comprises a gate electrode, and the display panel further comprises a second metal layer disposed on a side of the active layer away from the first metal layer, wherein the second metal layer comprises the gate electrode, and an orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the gate electrode on the substrate.
However, Ryu et al. further teaches:
[claim 6] wherein the thin-film transistor further comprises a gate electrode, and the display panel further comprises a second metal layer disposed on a side of the active layer away from the first metal layer, wherein the second metal layer comprises the gate electrode, and an orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the gate electrode on the substrate (col 5 lines 19-60, figures 1 and 2, element 20 is the gate electrode and a second metal layer on an opposite side of the active layers [elements 22 and 26] from the gate and source electrodes [elements 23a and 23b], where the orthographic projection of the gate electrode onto the channel layer covers the isolation groove [element 22c represents the semiconductor layer that fills the isolation groove and an orthographic projection of 20 onto the groove covers all of element 22c]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified with the teachings of Xiao in order to improve control of the transistor, and by implication the display device, by having a gate with corresponding dielectric material situated over the active region.
However, Takechi et al as modified still does not specifically disclose
[claim 6] [wherein the second metal layer comprises the gate electrode] located on a side of the active portion away from the substrate.
However, Xiao does teach,
[claim 6] [wherein the second metal layer comprises the gate electrode] located on a side of the active portion away from the substrate (paragraph 0041, figure 1, element 4 is the gate electrode on an opposite side of the active layer [element A in the dashed circle that is not the gate electrode] from the substrate [element 1]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi as modified to incorporate the teachings of Xiao in order to structure the transistor in such a way to minimize photo-induced leakage current in the active layer by placing the gate over the active layer instead of underneath.
Claim(s) 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), Ryu et al (US 7923722 B2), and Xiao (US 20190221672 A1) in further view of Kim et al (US 9842864 B2).
Takechi et al as modified teaches all of the limitations of the parent claim, claim 6, but does not specifically disclose
[claim 7] The display panel of claim 6, further comprising an interlayer dielectric layer and a third metal layer disposed on a side of the active layer away from the substrate, wherein the interlayer dielectric layer covers the active layer and the second metal layer, and the third metal layer is located on a side of the interlayer dielectric layer away from the second metal layer; wherein the third metal layer comprises a first electrode member, and the first electrode member is electrically connected to the thin-film transistor through the interlayer dielectric layer.
[claim 8] The display panel of claim 7, wherein the orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the first electrode member on the substrate.
However, Kim et al does teach
[claim 7], further comprising an interlayer dielectric layer and a third metal layer disposed on a side of the active layer away from the substrate, wherein the interlayer dielectric layer covers the active layer and the second metal layer, and the third metal layer is located on a side of the interlayer dielectric layer away from the second metal layer; wherein the third metal layer comprises a first electrode member, and the first electrode member is electrically connected to the thin-film transistor through the interlayer dielectric layer (col 7 lines 12-24, figure 5, where element 450 is the interdielectric layer, element 500 is the third metal layer and the first electrode portion of the third metal layer, and the interdielectric layer is situated between the second metal layer [element 400] and the third metal layer [element 500] and the third metal layer is situated away from the substrate [element 100] with reference to the active area [element 300], and element 500 acts as a gate electrode thus being electrically connected through the interdielectric layer to the thin film transistor).
[claim 8] wherein the orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the first electrode member on the substrate (figure 5, where the isolation groove imported from Bae et al as modified is situated in the active region, in Kim et al the active region is element 300, and the first electrode member of the substrate, element 500, is in an orthographic projection of the isolation groove [active region, element 300]).
It would have been obvious for one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified to incorporate the teachings of Kim et al in order to improve control of the transistor, and by implication the display device, by having a second gate with corresponding dielectric material.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), Ryu et al (US 7923722 B2), Xiao (US 20190221672 A1), and Kim et al (US 9842864 B2) in further view of Ka et al (US 10923547 B2).
Takechi et al as modified teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 9] The display panel of claim 7, further comprising a moisture-oxygen barrier layer disposed between the interlayer dielectric layer and the third metal layer, wherein the orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the moisture-oxygen barrier layer on the substrate.
However, Ka et al does teach
[claim 9] further comprising a moisture-oxygen barrier layer disposed between the interlayer dielectric layer and the third metal layer, wherein the orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the moisture-oxygen barrier layer on the substrate (col 5 lines 52-56, col 8 lines 30-42, figure 9 where element 352 is a moisture blocking layer and is situated between an interdielectric layer [element 351] and the gate electrode which here is defined as the third metal layer [element 431], and having read the isolation groove into the active region from Bae et al as modified, element 352’s orthographic projection covers the isolation groove in element 30 [considering that element 352 covers the entire TFT, it would cover any orthographic projection of any structure in the TFT).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified to incorporate the teachings of Ka et al in order to limit oxidization of the metal layer by incorporating a oxygen and moisture barrier, so as to not degrade the performance of the third metal layer but to improve overall quality and longevity of the device.
Claim(s) 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), and Ryu et al (US 7923722 B2) in view of Luo (CN 114141881 A where US 12119356 B2 is used as a translation for the patent).
Takechi et al as modified teaches all of the limitations of the parent claim, claim 1, but do not specifically disclose
[claim 10] The display panel of claim 1, wherein the first metal layer further comprises a light shielding portion located between the active portion and the substrate.
[claim 11] The display panel of claim 10, wherein one end of the source electrode is connected to the active portion, the other end is connected to the light shielding portion, and the source electrode is made of a material same as a material of the light shielding portion.
However, Luo does teach
[claim 10] wherein the first metal layer further comprises a light shielding portion located between the active portion and the substrate (col 5 line 55 – col 6 line 6, figure 1, element 110 is the light-shielding layer located between the substrate [element 100] and the active layer [elements 131, 132, 140 and 150]).
[claim 11] wherein one end of the source electrode is connected to the active portion, the other end is connected to the light shielding portion, and the source electrode is made of a material same as a material of the light shielding portion (col 5 line 55 – col 6 line 6, figure 1 where element 171 is the source electrode and is connected to both the source [element 131] and the light shielding layer [element 110] and is made of the same material as the light shielding layer [one of many metal alloys listed]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified to incorporate the teachings of Luo in order to limited backlight exposure to the active layer by creating a light blocking layer underneath the active layer so as to limit any photo-induced leakage in the active layer.
Claim(s) 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442) in view of Ryu et al (US 7923722) and in further view of Bae et al (US 8558225).
Takechi et al teaches
[claim 13], the thin-film transistor comprising an active portion, and a source electrode and a drain electrode that are contact-connected to the active portion (figure 14, col 16 lines 31-42, where the thin film transistor can be a part of a display panel, col 8 lines 37-45 where element 16 is the source and drain electrodes connected to an active portion [element 14]);
a substrate; a first metal layer disposed on the substrate and comprising the source electrode and the drain electrode (figure 14, col 8 lines 37-45 where element 16 is the source and drain electrodes connected to an active portion [element 14] and the substrate is element 10 and the source and drain electrodes are the first metal layer deposited on the substrate);
and an active layer disposed on a side of the first metal layer away from the substrate and comprising the active portion (figure 14, col 8 lines 37-45, where element 14 is deposited on the source and drain electrode [element 16] in a position away from the substrate [element 10]),
and the active portion comprising a semiconductor sublayer (figure 14, col 8 lines 37-45, element 14A and 14E is are the semiconductor sublayer which is apart of the active layer [element 14]);
the semiconductor sublayer comprises a first semiconductor subportion filled in the isolation groove and a second semiconductor subportion extending outside the isolation groove (col 8 lines 54-60, where element 14A is the first semiconductor subportion filled in an isolation groove [area between element 16], and the second semiconductor subportion extends outside the isolation groove [element 14E extends beyond the groove area and has an orthographic projection onto element 16]),
and an orthographic projection of the first semiconductor subportion on the substrate is within an orthographic projection of the second semiconductor subportion on the substrate (col 8 lines 54-60, where element 14A is the first semiconductor subportion filled in an isolation groove [area between element 16], and the second semiconductor subportion extends outside the isolation groove [element 14E extends beyond the groove area and has an orthographic projection onto element 16], thus the orthodgraphic projection of the element 14A onto the substrate [element 10] is within the orthographic projection of 14E [second semiconductor subsection] onto the substrate]).
However, Takechi et al does not specifically disclose
[claim 13] A display device, comprising a display panel and a device body, and the display panel and the device body combined into one body wherein the display panel comprises a thin-film transistor, and the active portion comprising a conductor sublayer, wherein the conductor sublayer comprises a first conductor subsection and a second conductor subsection spaced apart from each other, and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection, wherein the conductor sublayer further comprises an isolation groove located between the first conductor subsection and the second conductor subsection, and the second subportion extends to a side of the first conductor sublayer and the second conductor sublayer away from the substrate respectively.
[claim 15] wherein the first conductor subsection extends to the source contact region, the second conductor subsection extends to the drain contact region, the source electrode is electrically connected to the first conductor subsection located in the source contact region, and the drain electrode is electrically connected to the second conductor subsection in the drain contact region.
However, Ryu et al does teach
[claim 13] and the active portion comprising a conductor sublayer, wherein the conductor sublayer comprises a first conductor subsection and a second conductor subsection spaced apart from each other (figure 2, col 5 line 60 – col 6 line 4, where element 26a and 26b comprise the first conductor sublayer attached to the active portion [element 22], and contains a first conductive subsection [element 26a] and a second conductor subsection [element 26b] spaced apart from each other),
and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection (figure 2, col 6 lines 18-37, where element 22c is the semiconductor sublayer and is connected between the first and second [element 26a and 26b respectively] conductive subsection),
wherein the conductor sublayer further comprises an isolation groove located between the first conductor subsection and the second conductor subsection (figure 2, where the groove between elements 26a and 26b is the isolation groove and maps onto the groove from the base reference of Takechi et al),
and the second subportion extends to a side of the first conductor sublayer and the second conductor sublayer away from the substrate respectively (figure 2, where the first and second semiconductor subsections from the base reference, Takechi et al, maps onto element 22c, thus element 14E of figure 14 in Takechi et al would extend beyond the first and second conductive subsections since the first and second conductor subsections are mapped onto the source and drain electrodes [elements 23a and 23b from Ryu et al map onto element 16 of figure 14 in Takechi et al, thus element 26a and 26b of Ryu et al also map onto the same dimensions of the source and drain electrodes]).
[claim 15] wherein the first conductor subsection extends to the source contact region, the second conductor subsection extends to the drain contact region, the source electrode is electrically connected to the first conductor subsection located in the source contact region, and the drain electrode is electrically connected to the second conductor subsection in the drain contact region (figure 2, col 5 lines 55 – col 6 line 4, figures 1 and 2 where elements 26a and 26b are the two conductor subsections and each is connected to the drain and source contact regions respectively [elements 23a and 23b respectively]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al to incorporate the teachings of Ryu et al in order to provide a conductor subsection attached to the active layer in order to minimize hole leakage from the channel layer (col 6 lines 1-4).
However, Takechi et al as modified does not specifically disclose
[claim 13] A display device, comprising a display panel and a device body, and the display panel and the device body combined into one body wherein the display panel comprises a thin-film transistor.
However, Bae et al does teach
[claim 13] A display device, comprising a display panel and a device body, and the display panel and the device body combined into one body wherein the display panel comprises a thin-film transistor (abstract, where the thin film transistor is part of an Liquid Crystal Display and contains a drain electrode, source electrode and active region);
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified to incorporate the teachings of Bae et al in order to apply the thin-film-transistor to a specific display device such that the display device can be controlled and functional.
Regarding claim 14, Takechi et al further discloses
The display device, wherein the active portion comprises a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region, wherein the isolation groove is in the channel region (figure 14, col 8 lines 37-45, where element 16 is the source and drain contact region, element 14 is the channel region and is situated between element 16, of which the gap creates the isolation groove).
Claim(s) 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), and Ryu et al (US 7923722 B2) and Bae et al (US 8558225 B2) in further view of Lee (US 20170294460 A1).
Regarding claim 16, Takechi et al as modified teaches all of the limitations of the parent claims, claim 14, but does not specifically disclose
[claim 16] The display device of claim 14, wherein a length of the isolation groove in a first direction is less than a distance between the source contact region and the drain contact region, and the first direction is a direction in which the source contact region points to the drain contact region.
However, Lee does teach
[claim 16] wherein a length of the isolation groove in a first direction is less than a distance between the source contact region and the drain contact region, and the first direction is a direction in which the source contact region points to the drain contact region (paragraphs 0032 and 0065, where the isolation groove is the region between element 146 in TFT1 and when taken with an orthographic projection of the source and drain electrodes [elements 171 and 172] the isolation groove is smaller than the distance between the electrodes).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified with the teachings of Lee in order to maximize efficiency of isolating the conductive subsections by keeping the isolation trench large enough to not allow for any conduction between the source and drain but to lessen it to be shorten than the distance between the source and drain so as to maximize current flow through electrodes and minimize charge build up.
Regarding claim 17, Bae as modified lacks
[claim 17] The display device, wherein the length of the isolation groove in the first direction is less than or equal to 3 microns.
Per MPEP 2144.05 II under Routine Optimization, it would have been obvious to optimize the distance of the isolation trench to maximize efficiency of isolating the conductive subsections by keeping the isolation trench large enough to not allow for any conduction between the source and drain but to lessen it to be shorten than the distance between the source and drain so as to maximize current flow through electrodes and minimize charge build up. Since it is well known in the art that thin film transistors have layer thicknesses ranging from tenth of microns to single digit microns, to have a width of a trench proportional to such distances is reasonable for anyone skill in the art to try and start to optimize.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 84200442 B2), Ryu et al (US 7923722 B2) and Bae et al (US 8558225 B2) in further view of Xiao (US 20190221672 A1).
Takechi et al. as modified teach all of the limitations of the parent claim, claim 14, additionally
Takechi et al as modified do not specifically disclose
[claim 18] wherein the thin-film transistor further comprises a gate electrode, and the display panel further comprises a second metal layer disposed on a side of the active layer away from the first metal layer, wherein the second metal layer comprises the gate electrode, and an orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the gate electrode on the substrate
However, Ryu et al. further teaches:
[claim 18] wherein the thin-film transistor further comprises a gate electrode, and the display panel further comprises a second metal layer disposed on a side of the active layer away from the first metal layer, wherein the second metal layer comprises the gate electrode, and an orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the gate electrode on the substrate (col 5 lines 19-60, figures 1 and 2, element 20 is the gate electrode and a second metal layer on an opposite side of the active layers [elements 22 and 26] from the gate and source electrodes [elements 23a and 23b], where the orthographic projection of the gate electrode onto the channel layer covers the isolation groove [element 22c represents the semiconductor layer that fills the isolation groove and an orthographic projection of 20 onto the groove covers all of element 22c]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified with the teachings of Xiao in order to improve control of the transistor, and by implication the display device, by having a gate with corresponding dielectric material situated over the active region.
However, Takechi et al as modified still does not specifically disclose
[claim 18] [wherein the second metal layer comprises the gate electrode] located on a side of the active portion away from the substrate.
However, Xiao does teach,
[claim 18] [wherein the second metal layer comprises the gate electrode] located on a side of the active portion away from the substrate (paragraph 0041, figure 1, element 4 is the gate electrode on an opposite side of the active layer [element A in the dashed circle that is not the gate electrode] from the substrate [element 1]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified to incorporate the teachings of Xiao in order to structure the transistor in such a way to minimize photo-induced leakage current in the active layer by placing the gate over the active layer instead of underneath.
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takechi et al (US 8420442 B2), Ryu et al (US 7923722 B2) and Bae et al (US 8558225 B2) in further view of Luo (CN 114141881 A where US 12119356 B2 is used as a translation for the patent).
Takechi et al as modified teaches all of the limitations of the parent claim, claim 13, but do not specifically disclose
[claim 19] The display device of claim 13, wherein the first metal layer further comprises a light shielding portion located between the active portion and the substrate.
[claim 20] The display device of claim 19, wherein one end of the source electrode is connected to the active portion, the other end is connected to the light shielding portion, and the source electrode is made of a material same as a material of the light shielding portion.
However, Luo does teach
[claim 19] wherein the first metal layer further comprises a light shielding portion located between the active portion and the substrate (col 5 line 55 – col 6 line 6, figure 1, element 110 is the light-shielding layer located between the substrate [element 100] and the active layer [elements 131, 132, 140 and 150]).
[claim 20] wherein one end of the source electrode is connected to the active portion, the other end is connected to the light shielding portion, and the source electrode is made of a material same as a material of the light shielding portion (col 5 line 55 – col 6 line 6, figure 1 where element 171 is the source electrode and is connected to both the source [element 131] and the light shielding layer [element 110] and is made of the same material as the light shielding layer [one of many metal alloys listed]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Takechi et al as modified to incorporate the teachings of Luo in order to limited backlight exposure to the active layer by creating a light blocking layer underneath the active layer so as to limit any photo-induced leakage in the active layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818