DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/30/2025 has been entered.
Response to Amendment
The Amendment filed on 09/30/2025 has been entered. Claims 1 and 4-8, remain pending in the application. Claims 2 and 3 have been cancelled.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/08/2025 and 10/03/2025 have been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over disclosed prior art Fuchigami et al., (Japanese Patent Publication Number, JP-H10223835-A) hereinafter referenced as Fuchigami, in view of Mark Pavier (United States Patent Application Publication Number, US 2002/0096748 A1) hereinafter referenced as Pavier, and in view of Ken Lam (United States Patent Application Publication Number, US 2008/0044947 A1) hereinafter referenced as Lam.
Regarding claim 1, Fuchigami teaches a semiconductor device comprising: a first semiconductor chip (Fig.1) including a first MOSFET of n-type (Fig.1, element #72 is an n-type MOSFET) and a first parasitic diode formed in the first MOSFET (Fig.1, the diode formed by the regions p and layers n- and n+ above top layer #10); and a second semiconductor chip including a second MOSFET of n-type (Fig.1, element #71 is an n-type MOSFET) and a second parasitic diode formed in the second MOSFET (Fig.1, the diode formed by the regions p and layers n- and n+ below bottom layer #10), wherein a first source electrode (Fig.1, element #3 of element #72, paragraph [0002], row 4) and a first gate wiring (Fig.1, element #2 of element #72, paragraph [0025], rows 1-2) are formed on a front surface of the first semiconductor chip (Fig.1, front surface if top surface of element #72), wherein a first drain electrode is formed on a back surface of the first semiconductor chip (Fig.1, top element #10, paragraph [0016], rows 1-3, and paragraph [0013], rows 2-4) wherein a first anode of the first parasitic diode (Fig.1, region p of element #72) is coupled to the first source electrode (Fig.1, region p and the source electrode of element #72 are coupled) and a first cathode of the first parasitic diode is coupled to the first drain electrode (Fig.1, region n+ and top element #10 of element #72 are coupled), wherein a second source electrode (Fig.1, element #3 of element #71) and a second gate wiring (Fig.1, element #2 of element #71) are formed on a front surface of the second semiconductor chip (Fig.1, front surface if bottom surface of element #71), wherein a second drain electrode is formed on a back surface of the second semiconductor chip (Fig.1, bottom element #10, paragraph [0016], rows 1-3, and paragraph [0013], rows 2-4), wherein a second anode of the second parasitic diode (Fig.1, region p of element #71) is coupled to the second source electrode (Fig.1, region p and the source electrode of element #71 are coupled) and a second cathode of the second parasitic diode is coupled to the second drain electrode (Fig.1, region n+ and bottom element #10 of element #71 are coupled).
Fuchigami further teaches wherein the first semiconductor chip and the second semiconductor chip are stacked such that the back surface of the first semiconductor chip and the back surface of the second semiconductor chip face each other (Fig.1, paragraph [0013], rows 2-4). Fuchigami does not teach wherein a planar area of the first semiconductor chip is substantially equal to a planar area of the second semiconductor chip and wherein the chips are attacked without exposing the second semiconductor chip from the first semiconductor chip in plan view. Pavier teaches wherein a planar area of a first semiconductor chip is substantially equal to a planar area of a second semiconductor chip (Fig.2, elements #30 and #31, paragraph [0026], rows 2-3, paragraph [0006], rows 5-7) and wherein the chips are attacked without exposing the second semiconductor chip from the first semiconductor chip in plan view (Fig.2, elements #30 and #31, are identical and vertically aligned, paragraph [0006], rows 3-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Pavier and disclose the two semiconductor chips having an equal planar area and stacked back-to-back, such that in plan view the second semiconductor is not exposed. As disclosed by Pavier, arranging the dies in this geometry, allows the implementation of semiconductor packages having reduce dimensions (paragraph [0005], rows 1-6 and paragraph [0031], rows 1-3).
Fuchigami further teaches wherein the back surface of the first semiconductor chip is in contact with only the back surface of the second semiconductor chip via a conductive member (Fig1, element #19, paragraph [0016], rows 1-6). Fuchigami does not teach wherein the conductive member extends over an entire back surface of the first semiconductor chip and an entire back surface of the second semiconductor chip. Pavier teaches wherein the back surface of the first semiconductor chip is in contact with only the back surface of the second semiconductor chip via a conductive member (Fig.2, elements #21, #32 and #33 are interposed between the back surfaces of the two semiconductors dies, elements #30 and #31, paragraph [0026], rows 10-12), such that the conductive member extends over an entire back surface of the first semiconductor chip and an entire back surface of the second semiconductor chip (Fig. 1, shows a plan view where element #21 is wider than the die, element #30 and in Fig.2 it extends over the entire back surface of the die, which is vertically aligned and identical with element #31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Pavier and disclose wherein the conductive member extends over an entire back surface of the first semiconductor chip and an entire back surface of the second semiconductor chip. Extending the conductive member over the entire back surfaces of the two chips increases the contact area between them and therefore makes the contact more reliable from the mechanical and electrical point of view.
The combination of Fuchigami and Pavier does not teach wherein the conductive member is only a conductive tape. Lam teaches two semiconductor devices connected using only conductive tape (Fig.2, elements #205 and #207 are connected only by conductive tape, element #211, paragraph [0022], rows 2-5 and 8-10). Thus, both Fuchigami and Lam each disclose an electrical connection between two semiconductor devices. A person of ordinary skilled in the art, before the effective filling date of the claimed invention, would have recognized that the conductive adhesive used by Fuchigami could have been substituted by the conductive tape disclosed by Lam, because they both serve the same purpose of providing an electrical connection between the two semiconductor chips. Furthermore, a person of ordinary skill in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of allowing an electrical connection between the two semiconductor devices.
Claims 1, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshiba et al., (United States Patent Publication Number, US 7,030,501 B2) hereinafter referenced as Yoshiba, in view of Pavier and in view of Lam.
Regarding claim 1, Yoshiba teaches a semiconductor device comprising: a first semiconductor chip (Fig.1A, element #23) including a first MOSFET of n-type (Fig.1A, element #23a is an n-type MOSFET, column 5, row 4) and a first parasitic diode formed in the first MOSFET (Fig.1C, the diode is formed by P layer, element #3, N- layer, element #2 and N+ layer element #1); and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode formed in the second MOSFET (Fig.1A, element #23b has same pattern as element #23a, column 4, rows 55-56), wherein a first source electrode (Fig.1A, top element #11, column 4, rows 42-43) and a first gate wiring (Fig.1A, top element #12, column 4, row 43) are formed on a front surface of the first semiconductor chip (Fig.1A, top elements #11 and #12 are formed on the front surface of element #23a), wherein a first drain electrode is formed on a back surface of the first semiconductor chip (Fig.1A, top element #19, column 4, row 46), wherein a first anode of the first parasitic diode (Fig.1C, region P) is coupled to the first source electrode (Fig.1C, region P is coupled to element #11 through elements #8) and a first cathode of the first parasitic diode (Fig.1C, region N+) is coupled to the first drain electrode (Fig.1C, region N+ is coupled to element #19), wherein a second source electrode and a second gate wiring are formed on a front surface of the second semiconductor chip (Fig.1A, elements #11 and #12 on the bottom surface of element #23b), wherein a second drain electrode is formed on a back surface of the second semiconductor chip (Fig.1A, bottom elements #19), wherein a second anode of the second parasitic diode is coupled to the second source electrode and a second cathode of the second parasitic diode is coupled to the second drain electrode (Fig.1C, element #23b has same pattern as element #23a, column 4, rows 55-56).
Yoshiba teaches wherein the first semiconductor chip and the second semiconductor chip are stacked such that the back surface of the first semiconductor chip and the back surface of the second semiconductor chip face each other (Fig.1A). Yoshiba does not teach wherein a planar area of the first semiconductor chip is substantially equal to a planar area of the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are stacked such that the back surface of the first semiconductor chip and the back surface of the second semiconductor chip face each other without exposing the second semiconductor chip from the first semiconductor chip in plan view. Pavier teaches wherein a planar area of a first semiconductor chip is substantially equal to a planar area of a second semiconductor chip (Fig.2, elements #30 and #31, paragraph [0026], rows 2-3, paragraph [0006], rows 5-7) and wherein the chips are attacked without exposing the second semiconductor chip from the first semiconductor chip in plan view (Fig.2, elements #30 and #31, are identical and vertically aligned, paragraph [0006], rows 3-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Pavier and disclose the two semiconductor chips having an equal planar area and stacked back-to-back, such that in plan view the second semiconductor is not exposed. As disclosed by Pavier, arranging the dies in this geometry, allows the implementation of semiconductor packages having reduce dimensions (paragraph [0005], rows 1-6 and paragraph [0031], rows 1-3).
Yoshiba further teaches wherein the back surface of the first semiconductor chip is in contact with only the back surface of the second semiconductor chip (Fig.1C, the back surfaces of the element #23a and #23b are in contact with each other) via solder (column 5, rows 45-47). Yoshiba does not teach wherein the conductive member extends over an entire back surface of the first semiconductor chip and an entire back surface of the second semiconductor chip. Pavier teaches wherein the back surface of the first semiconductor chip is in contact with only the back surface of the second semiconductor chip via a conductive member (Fig.2, elements #21, #32 and #33 are interposed between the back surfaces of the two semiconductors dies, elements #30 and #31, paragraph [0026], rows 10-12), such that the conductive member extends over an entire back surface of the first semiconductor chip and an entire back surface of the second semiconductor chip (Fig. 1, shows a plan view where element #21 is wider than the die, element #30 and in Fig.2 it extends over the entire back surface of the die, which is vertically aligned and identical with element #31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Pavier and disclose wherein the conductive member extends over an entire back surface of the first semiconductor chip and an entire back surface of the second semiconductor chip. Extending the conductive member over the entire back surfaces of the two chips increases the contact area between them and therefore makes the contact more reliable from the mechanical and electrical point of view.
The combination of Yoshiba and Pavier does not teach wherein the conductive member is only a conductive tape. Lam teaches two semiconductor devices connected using only conductive tape (Fig.2, elements #205 and #207 are connected only by conductive tape, element #211, paragraph [0022], rows 2-5 and 8-10). Thus, both Yoshiba and Lam each disclose an electrical connection between two semiconductor devices. A person of ordinary skilled in the art, before the effective filling date of the claimed invention, would have recognized that the solder used by Yoshiba could have been substituted by the conductive tape disclosed by Lam, because they both serve the same purpose of providing an electrical connection between the two semiconductor chips. Furthermore, a person of ordinary skill in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of allowing an electrical connection between the two semiconductor devices.
Regarding claim 4, the combination of Yoshiba, Pavier, and Lam teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Yoshiba further teaches the semiconductor device according to claim 1 further comprising: a third semiconductor chip including a control circuit electrically connected to the first gate wiring and the second gate wiring (Fig.5, control IC circuit, is an integrated circuit, therefore is part of a semiconductor chip, is connected to the gates electrodes G of MOSFETS Q1 and Q2, column 1, rows 37-38), wherein the control circuit has a function of supplying a gate potential to the first gate wiring and the second gate wiring in order to switch an ON state and an OFF state of each of the first MOSFET and the second MOSFET (column 1, rows 30-33).
Regarding claim 6, the combination of Yoshiba, Pavier, and Lam teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Yoshiba further teaches the semiconductor device according to claim 1 wherein the first semiconductor chip (Fig.1A, element #23a) includes: an n-type first semiconductor substrate having a front surface and a back surface (Fig.1C, N- substrate, element #2); a p-type first body region formed in the first semiconductor substrate on a side of the front surface of the first semiconductor substrate (Fig.1C, P region, element #3, column 5, row 7); an n-type first source region formed in the first body region (Fig.1C, n-type regions, element #8, column 5, rows 11-12); a first trench formed in the first semiconductor substrate on the side of the front surface of the first semiconductor substrate such that a bottom portion thereof is located below the first body region (Fig.1C, element #4, column 5, rows 8-9); a first gate insulating film formed inside the first trench (Fig.1C, element #5, column 5, rows 9-10); a first gate electrode formed on the first gate insulating film so as to fill the inside of the first trench (Fig.1C, element #6, column 5, row 11); a first interlayer insulating film formed on the front surface of the first semiconductor substrate (Fig.1C, element #10, column 5, row 17); the first source electrode formed on the first interlayer insulating film and electrically connected to the first body region and the first source region (Fig.1C, element #1, column 5, row 17-20); the first gate wiring formed on the first interlayer insulating film and electrically connected to the first gate electrode (Fig.1C, element #12, column 5 rows 22-25); an n-type first drain region formed in the first semiconductor substrate on a side of the back surface of the first semiconductor substrate (Fig.1C, N+ region, element #1); and the first drain electrode formed on the back surface of the first semiconductor substrate and electrically connected to the first drain region (Fig.1C, N+ region, element #19, column 5, row 37).
Yoshiba teaches that the second semiconductor chip has the same structure as the first semiconductor to chip (column 4, rows 55-58). Therefore, Fig.1C will also be used to point out the elements of the second semiconductor chip. Yoshiba teaches wherein the second semiconductor chip (Fig.1A, element #23b) includes: an n-type second semiconductor substrate having a front surface and a back surface (Fig.1C, N- substrate, element #2); a p-type second body region formed in the second semiconductor substrate on a side of the front surface of the second semiconductor substrate (Fig.1C, P region, element #3, column 5, row 7); an n-type second source region formed in the second body region (Fig.1C, n-type regions, element #8, column 5, rows 11-12); a second trench formed in the second semiconductor substrate on the side of the front surface of the second semiconductor substrate such that a bottom portion thereof is located below the second body region (Fig.1C, element #4, column 5, rows 8-9); a second gate insulating film formed inside the second trench (Fig.1C, element #5, column 5, rows 9-10); a second gate electrode formed on the second gate insulating film so as to fill the inside of the second trench (Fig.1C, element #6, column 5, row 11); a second interlayer insulating film formed on the front surface of the second semiconductor substrate (Fig.1C, element #10, column 5, row 17); the second source electrode formed on the second interlayer insulating film and electrically connected to the second body region and the second source region (Fig.1C, element #1, column 5, row 17-20); the second gate wiring formed on the second interlayer insulating film and electrically connected to the second gate electrode (Fig.1C, element #12, column 5 rows 22-25); an n-type second drain region formed in the second semiconductor substrate on a side of the back surface of the second semiconductor substrate (Fig.1C, N+ region, element #1); and the second drain electrode formed on the back surface of the second semiconductor substrate and electrically connected to the second drain region (Fig.1C, N+ region, element #19, column 5, row 37), wherein the first parasitic diode is composed of the first body region and the first semiconductor substrate and the first drain region located below the first body region (Fig.1C, the diode is composed of P region, element #3, N substrate, element #2 and N+ region, element #1) and wherein the second parasitic diode is composed of the second body region and the second semiconductor substrate and the second drain region located below the second body region (Fig.1C, the diode is composed of P region, element #3, N substrate, element #2 and N+ region, element #1).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshiba, in view of Pavier, Lam and Tomoaki Uno et al., (United States Patent Application Publication Number, US 2005/0156204 A1), hereinafter referenced as Uno.
Regarding claim 5, the combination of Yoshiba, Pavier, and Lam teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Yoshiba further teaches the semiconductor device according to claim 1 further comprising: a third semiconductor chip (Fig.5, control circuit IC is an integrated circuit, therefore is part of a semiconductor chip) including a control circuit electrically connected to the first gate wiring and the second gate wiring (Fig.5, control IC circuit, is connected to the gates electrodes G of MOSFETS Q1 and Q2, column 1, rows 37-38), wherein the control circuit has a function of supplying a gate potential to the first gate wiring and the second gate wiring in order to switch an ON state and an OFF state of each of the first MOSFET and the second MOSFET (column 1, rows 30-33).
The combination of Yoshiba, Pavier and Lam does not teach wherein the second semiconductor chip further includes: a control circuit electrically connected to the first gate wiring and the second gate wiring, and wherein the control circuit has a function of supplying a gate potential to the first gate wiring and the second gate wiring in order to switch an ON state and an OFF state of each of the first MOSFET and the second MOSFET. Uno teaches wherein the second semiconductor chip (Fig.8, element #5a, paragraph [0060], rows 3-4) further includes: a control circuit (Fig.8, circuit formed by elements #3a and #3b, paragraph [0048], rows 5-6) electrically connected to the first gate wiring and the second gate wiring (Fig.8, elements #3a and #3b are connected to the gates of transistors Q1 and Q2, paragraph [0048], rows 5-8), and wherein the control circuit has a function of supplying a gate potential to the first gate wiring and the second gate wiring (Fig.8, the control circuit is connected to the two gates, so voltage is applied to the gates through the circuit) in order to switch an ON state and an OFF state of each of the first MOSFET and the second MOSFET (Fig.8, MOSFET Q1 and Q2 form a switch turning ON and OFF, paragraph [0053], rows 1-3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Uno and disclose a semiconductor chip including a control circuit connected to the gates of the first and second transistor in order to switch an ON and OFF state of each one of them. As disclosed by Uno, this reduces the parasitic inductance of the circuit and the switching loss can be reduced. Furthermore, this increases the overall circuit operation stability (Uno, paragraph [0060], rows 21-25).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshiba, in view of Pavier, Lam and disclosed prior art, Hiroshi Yanagigawa, (United States Patent Number, US 10,250,255 B2), hereinafter referenced as Yanagigawa.
Regarding claim 7, the combination of Yoshiba, Pavier and Lam teaches the semiconductor device of claims 1 and 6 as set forth in the obviousness rejection. The combination of Yoshiba, Pavier and Lam does not teach, wherein the second semiconductor chip further includes: a p-type column region formed in the second semiconductor substrate located below the second body region. Yanagigawa teaches a semiconductor chip (Fig.4, element Q2, column 4, row 22) further includes a p-type column region (Fig.4, element #CLM, column 5, row 55) formed in the second semiconductor substrate (Fig.4, element #NEL, column 4, row 45) located below the second body region (Fig.4, element #PM, column 4, row 63). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yanagigawa and disclose a p-type column located below the second body region. As disclosed by Yanagigawa, this facilitates the passage of an increased amount of current, and prevents the backflow of current (column 10, rows 49-55).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshiba, in view of Pavier, Lam and Morio Iwamizu et al., (United States Patent Number US 10,978,446 B2), hereinafter referenced as Iwamizu.
Regarding claim 8, the combination of Yoshiba, Pavier and Lam teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Yoshiba teaches a circuit device using the semiconductor device according to claim 1 as a switch (title). The combination of Yoshiba, Pavier and Lam does not teach the circuit comprising a battery having a positive electrode and a negative electrode; and a load, wherein the first source electrode is electrically connected to the positive electrode, and wherein the second source electrode is electrically connected to the negative electrode via the load. Iwamizu teaches the circuit (Fig.1) comprising a battery having a positive electrode and a negative electrode (Fig.1, element #BT, column 4, row 12); and a load (Fig.1, element LCT, column 4, row 12), wherein the first source electrode is electrically connected to the positive electrode (Fig.1, first source electrode, source of transistor Tr1, column 4, row 27, is connected to the positive electrode, column 4, rows 53-55), and wherein the second source electrode is electrically connected to the negative electrode via the load (Fig.1, second source electrode, source of transistor Tr2, column 4, row 27 is connected to the negative electrode, column 4, rows 57-58). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Iwamizu and disclose the circuit of claim 8. As disclosed by Iwamizu, using the device in this circuit configuration can effectively prevent a breakdown in an electronic control unit when a reverse battery connection is sometimes made (column 4, rows 10-14).
Response to Arguments
Applicant’s arguments filed on 09/30/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899