DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 February 2026 has been entered.
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 12, 15 and 19 in the Applicant’s response dated 26 February 2026. The claim amendments and the Applicant’s accompanying comments have been addressed below.
The Examiner acknowledges the amendments to claims 12 and 19 in the Applicant’s response dated 26 February 2026 in lieu of the U.S.C. 112(a) rejection presented in the previous office action. The previously presented U.S.C. 112(a) rejection is therefore withdrawn.
The Examiner acknowledges the cancellation of claim 15 in the Applicant’s response dated 26 February 2026 in lieu of the U.S.C. 112(a) rejection and U.S.C. 112(b) rejection presented in the previous office action. The previously presented U.S.C. 112(a) rejection and U.S.C. 112(b) rejection are therefore withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 23 February 2026 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kayvan Sadra et al. (US 2006/0134889 A1; hereinafter “Sadra”) in view of Yoshiki Yamamoto (US 2018/0342537 A1; hereinafter “Yamamoto”) and in further view of Ahmad Ghaemmaghami et al. (US 7192836 B1; hereinafter “Ghaemmaghami”).
Regarding Claim 1, Sadra teaches a manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a photoresist pattern to a first thickness on a semiconductor substrate on which a device isolation film and a gate electrode have been formed (28, Fig. 1A, para [0027] describes a resist layer which can be seen on a semiconductor substrate 22 wherein isolation regions 451 as seen in Fig. 4C, and gate structure 21 have been formed);
forming a lightly doped drain (LDD) region, by implanting low-concentration second conductivity-type impurity ions in the well region (para [0058] describes wherein the LDD dopant is of a first dopant species according to an N-type or P-type) using both the photoresist pattern and the gate electrode as a mask (15 and 24, Fig. 1A, para [0027] describes an LDD implant process 15 which form the LDD regions 24 through implantation of appropriate dopant species atoms through openings in the resist layer wherein the gate electrode can be seen masking the implant from reaching areas under the gate electrode with respect to the angle of the implant);
reducing the photoresist pattern to a second thickness, by removing a portion of the photoresist pattern (730, Fig. 7 and Fig. 10 – Fig. 12, para [0052] describes wherein an etch or trim process to reduce the thickness of the resist layer and round the corners) wherein the first thickness and the second thickness are in a direction perpendicular to the front surface of the semiconductor substrate (1010y and 1020y, Fig. 10-Fig. 12, para [0061] describes wherein the partially reduced resist layer has a reduced resist thickness 1020y after a portion of the original photoresist thickness 1010y which is perpendicular to a front surface of the semiconductor substrate has been removed);
forming a halo region below the LDD region (32, Fig. 1B, para [0028] describes an angled pocket implant forming halo region 32), by implanting the first conductivity-type impurity ions in the well region (para [0058] describes wherein the pocket implant is of a second dopant species different than the LDD implant according to an N-type or P-type) at an oblique angle with respect to the front surface of the semiconductor substrate (20, Fig. 1B, para [0034] describes angled pocket implants formed by introducing dopants under edges of the gate, thus forming halo regions) using the photoresist pattern that has been reduced to the second thickness and the gate electrode as a mask (730 and 740, Fig. 7, para [0052] describes using a reduced photoresist pattern as a mask to form the pocket implant wherein the gate electrode can be seen masking the implant from reaching areas under the gate electrode with respect to the angle of the implant); and
wherein the photoresist pattern that has been reduced to the second thickness has an inclined side surface (STA, annotated Fig. 12 depicts wherein rounded corner 1030r of the reduced photoresist pattern 1030 will result in at least a portion of a side surface of the photoresist to have an inclined angle as shown in annotated Fig. 12 below) and has a smaller inclined angle relative to the front surface of the semiconductor substrate than a side surface of the photoresist pattern that has the first thickness (FTA, annotated Fig. 12 depicts wherein a side surface of the first photoresist represented by the dashed line is substantially perpendicular to the front surface of the semiconductor substrate having approximately a 90 degree angle FTA wherein a rounded corner of a side surface shown by second thickness angle STA will have an angle less than 90 degrees as it approaches a 45 degree rounding).
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Sadra fails to explicitly disclose forming a well region by implanting first conductivity-type impurity ions into a front surface of the semiconductor substrate; and removing the photoresist pattern that has been reduced to the second thickness; and wherein forming the halo region comprises implanting the low-concentration first conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the front surface of the semiconductor substrate.
However, Yamamoto teaches a similar manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a well region by implanting first conductivity-type impurity ions into a front surface of the semiconductor substrate (PW1 and NW1, Fig. 1, para [0042] describes forming a p-type well and an n-type well in the semiconductor substrate through an ion implantation process); and
removing the photoresist pattern that has been reduced to the second thickness (RP3, Fig. 9, para [0064] and para [0070] and para [0112] describes wherein resist pattern RP3 is removed by ashing wherein resist pattern RP3 is utilized during the extension region and halo region implantation wherein upon combining Sadra with Yamamoto the resulting resist pattern RP3 would be a reduced second thickness photoresist pattern); and
wherein forming the halo region comprises implanting the low-concentration first conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the front surface of the semiconductor substrate (para [0063] describes an oblique ion implantation process being performed at an angle inclined by more 15 degrees or more and 45 degrees or less with respect to the perpendicular semiconductor substrate wherein said oblique ion implantation is described as being used for a p-type halo region implantation in para [0112] wherein an angle of approximately 45 degrees falls with the range of 25 degrees to 50 degrees)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra with Yamamoto to further disclose a manufacturing method of a semiconductor device comprising forming a well region in the semiconductor substrate to provide the advantage of enabling a region to be used for controlling a threshold value of the semiconductor device providing the device with advanced functionality and flexibility (Yamamoto, para [0042]), and to disclose removing the photoresist pattern that has been reduced to the second thickness in order to provide the well-known advantage of removing unnecessary device components that may cause unwanted effects and to further disclose an angle of the halo region ion implantation in order to provide the advantage of enabling an ion implant which may reach a region under the gate electrode (Yamamoto, para [0063]).
The combination of Sadra and Yamamoto fail to explicitly disclose wherein an inclined side surface extends towards the semiconductor substrate to a top surface of the device isolation film.
However, Ghaemmaghami teaches a similar manufacturing method of a semiconductor device wherein a photoresist pattern has an inclined side surface that extends towards the semiconductor substrate to a top surface of the device isolation film (402, Fig. 4, column 3, lines 31-37 describe a photoresist pattern 402 of a shorter height than a thick photoresist pattern used in processing step 302 such as shown by photoresist pattern 213 wherein second photoresist pattern 402 has an inclined side surface as shown in Fig. 4 that extends towards a semiconductor substrate to a top surface of a device isolation film, described herein as an oxide trench further wherein upon combining Sadra with Ghaemmaghami the second photoresist pattern 402 of Ghaemmaghami may be formed by reducing a height of a first photoresist pattern instead of replacing the first photoresist pattern).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra and Yamamoto with Ghaemmaghami to further disclose a manufacturing method of a semiconductor device comprising a photoresist pattern that has an inclined side surface that extends towards a semiconductor substrate to a top surface of a device isolation film in order to provide the well-known advantage of matching a side surface of a photoresist pattern with an implantation angle of an angled implant resulting in a more effective halo implant process.
Regarding Claim 2, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 1, wherein the reducing the photoresist pattern to the second thickness comprises ashing the photoresist pattern (Sadra, para [0048] describes using an oxygen plasma etching process, thus comprising the same conditions as an ashing process, on the resist layer to achieve the desired thickness and width loss of the photoresist layer).
Regarding Claim 3, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 2 wherein, when ashing the photoresist pattern, the photoresist pattern is subjected to oxygen (02) plasma treatment or ozone (03) treatment (Sadra, para [0048] describes using an oxygen plasma etching process on the resist layer).
Regarding Claim 4, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 1, wherein the second thickness is 30% to 95% of the first thickness (Sadra, 1010y, 1020y and 1030y, Fig. 10-Fig. 12, 1010y, 1020y and 1030y, para [0050] describes wherein the resist trim process may be adjusted to reduce the thickness of the resist to any arbitrary value for optimal reduction in pocket shadowing while maintaining good blocking in other areas wherein said resulting reduced thicknesses are shown in Fig. 11 and Fig. 12 wherein a dashed height 1010y represents a first thickness and said arbitrary values appear to be roughly 75% 1020y and 50% 1030y used in reducing the first thickness in order to implement an ion implant with optimal reduction in pocket shadowing wherein said ranges fall within the 30% to 95% thickness range).
Regarding Claim 5, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 4, wherein the first thickness and the second thickness are greater than a thickness of the gate electrode (Sadra, Fig. 5, para [0045] describes wherein the resist layer 502a and 502b are overlying the gate structures 504 before 502a and after 502b the thickness of the resist layer is reduced).
Regarding Claim 11, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 1, further comprising:
after the removing the photoresist pattern that has been reduced to the second thickness, forming a source region and a drain region by implanting the low-concentration second conductivity-type impurity ions into the front surface of the semiconductor substrate (Yamamoto, SD3 and SD4, Fig. 14, para [0078] describes forming p-type and n-type diffusion layers after removing the photoresist pattern used in the halo implantation process wherein said diffusion layers become part of a source or drain region).
Regarding Claim 12, Sadra teaches a manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a photoresist pattern to a first thickness on a semiconductor substrate on which a gate electrode has been formed (28, Fig. 1A, para [0027] describes a resist layer which can be seen on a semiconductor substrate 22 wherein a gate structure 21 has been formed),
forming a lightly doped drain (LDD) region in the well region, using both the photoresist pattern and the gate electrode as the mask (15 and 24, Fig. 1A, para [0027] describes an LDD implant process 15 which form the LDD regions 24 through implantation of appropriate dopant species atoms through openings in the resist layer wherein the gate electrode can be seen masking the implant from reaching areas under the gate electrode with respect to the angle of the implant);
reducing a thickness of the photoresist pattern to a second thickness, by removing a portion of the photoresist pattern (730, Fig. 7 and Fig. 10 – Fig. 12, para [0052] describes wherein an etch or trim process to reduce the thickness of the resist layer and round the corners) wherein the thickness of the photoresist pattern is in a direction perpendicular to a top surface of the semiconductor substrate (1010y and 1020y, Fig. 10-Fig. 12, para [0061] describes wherein the partially reduced resist layer has a reduced resist thickness 1020y after a portion of the original photoresist thickness 1010y which is perpendicular to a top surface of the semiconductor substrate has been removed);
forming a halo region below the LDD region (32, Fig. 1B, para [0028] describes an angled pocket implant forming halo region 32), using both the photoresist pattern and the gate electrode as the mask (730 and 740, Fig. 7, para [0052] describes using a reduced photoresist pattern as a mask to form the pocket implant wherein the gate electrode can be seen masking the implant from reaching areas under the gate electrode with respect to the angle of the implant); and
wherein the photoresist pattern that has been reduced to the second thickness has an inclined side surface (STA, annotated Fig. 12 depicts wherein rounded corner 1030r of the reduced photoresist pattern 1030 will result in at least a portion of a side surface of the photoresist to have an inclined angle as shown in annotated Fig. 12 below) and has a smaller inclined angle relative to the front surface of the semiconductor substrate than a side surface of the photoresist pattern that has the first thickness (FTA, annotated Fig. 12 depicts wherein a side surface of the first photoresist represented by the dashed line is substantially perpendicular to the front surface of the semiconductor substrate having approximately a 90 degree angle FTA wherein a rounded corner of a side surface shown by second thickness angle STA will have an angle less than 90 degrees as it approaches a 45 degree rounding).
Sadra fails to explicitly disclose forming a well region using both the photoresist pattern and the gate electrode as a mask; and removing the photoresist pattern; and wherein forming the halo region comprises implanting the low-concentration second conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the front surface of the semiconductor substrate
Sadra fails to explicitly disclose forming a well region using both the photoresist pattern and the gate electrode as a mask; and removing the photoresist pattern that has been reduced to the second thickness; and wherein forming the halo region comprises implanting the low-concentration second conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the front surface of the semiconductor substrate.
However, Yamamoto teaches a similar manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a well region using both the photoresist pattern and the gate electrode as a mask (PW1 and NW1, Fig. 1, para [0042] describes forming a p-type well and an n-type well in the semiconductor substrate through an ion implantation process wherein upon combining the well region implantation with the substrate of Sadra the photoresist pattern and gate electrode would be present functioning as a mask for the implant process); and
removing the photoresist pattern (RP3, Fig. 9, para [0064] and para [0070] and para [0112] describes wherein resist pattern RP3 is removed by ashing wherein resist pattern RP3 is utilized during the extension region and halo region implantation wherein upon combining Sadra with Yamamoto the resulting resist pattern RP3 would be a reduced second thickness photoresist pattern); and
wherein forming the halo region comprises implanting the low-concentration first conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the front surface of the semiconductor substrate (para [0063] describes an oblique ion implantation process being performed at an angle inclined by more 15 degrees or more and 45 degrees or less with respect to the perpendicular semiconductor substrate wherein said oblique ion implantation is described as being used for a p-type halo region implantation in para [0112] wherein an angle of approximately 45 degrees falls with the range of 25 degrees to 50 degrees)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra and Yamamoto to further disclose a manufacturing method of a semiconductor device comprising forming a well region in the semiconductor substrate to provide the advantage of enabling a region to be used for controlling a threshold value of the semiconductor device providing the device with advanced functionality and flexibility (Yamamoto, para [0042]), and to disclose removing the photoresist pattern in order to provide the well-known advantage of removing unnecessary device components that may cause unwanted effects and to further disclose an angle of the halo region ion implantation in order to provide the advantage of enabling an ion implant which may reach a region under the gate electrode (Yamamoto, para [0063]).
The combination of Sadra and Yamamoto fail to explicitly disclose wherein an inclined side surface extends towards the semiconductor substrate.
However, Ghaemmaghami teaches a similar manufacturing method of a semiconductor device wherein a photoresist pattern has an inclined side surface that extends towards the semiconductor substrate (402, Fig. 4, column 3, lines 31-37 describe a photoresist pattern 402 of a shorter height than a thick photoresist pattern used in processing step 302 such as shown by photoresist pattern 213 wherein second photoresist pattern 402 has an inclined side surface as shown in Fig. 4 that extends towards a semiconductor substrate further wherein upon combining Sadra with Ghaemmaghami the second photoresist pattern 402 of Ghaemmaghami may be formed by reducing a height of a first photoresist pattern instead of replacing the first photoresist pattern).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra and Yamamoto with Ghaemmaghami to further disclose a manufacturing method of a semiconductor device comprising a photoresist pattern that has an inclined side surface that extends towards a semiconductor substrate in order to provide the well-known advantage of matching a side surface of a photoresist pattern with an implantation angle of an angled implant resulting in a more effective halo implant process.
Regarding Claim 13, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 12,
wherein the forming the LDD region is performed before reducing the thickness of the photoresist pattern (Sadra, 720, Fig. 7, para [0052] describes wherein an LDD implant is performed before trimming the resist layer to reduce the thickness).
Regarding Claim 14, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 12,
wherein a portion of the LDD region overlaps the gate electrode (Yamamoto, LDD1 and LDD2, Fig. 12, para [0063] describes wherein forming LDD1 region using an angled ion implant results in an LDD region that reaches just under the gate wherein upon combining the angled implant of Yamamoto with Sadra would result in an LDD region that overlaps the gate electrode).
Regarding Claim 15, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 12,
wherein forming the well region comprises implanting first conductivity-type impurity ions in the semiconductor substrate (Yamamoto, PW1 and NW1, Fig. 1, para [0042] and para [0043] describes forming a p-type well PW1 and an n-type well NW1 through an ion implantation process), and
wherein forming the LDD region comprises implanting second conductivity-type impurity ions in the semiconductor substrate (Sadra, 15 and 24, Fig. 1A, para [0058] describes wherein the LDD dopant is of a first dopant species according to an N-type or P-type forming LDD regions 24 through an ion implantation process 15).
Regarding Claim 17, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 15, further comprising:
after removing the photoresist pattern, forming a source region and a drain region by implanting the second conductivity-type impurity ions in the well region (Yamamoto, SD3 and SD4, Fig. 14, para [0078] describes forming p-type and n-type diffusion layers after removing the photoresist pattern used in the halo implantation process wherein said diffusion layers become part of a source or drain region and are comprised in a portion of well regions PW2 and NW2).
Regarding Claim 18, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 12, wherein reducing the thickness of the photoresist pattern comprises ashing the photoresist pattern (Sadra, para [0048] describes using an oxygen plasma etching process, thus comprising the same conditions as an ashing process, on the resist layer to achieve the desired thickness and width loss of the photoresist layer).
Regarding Claim 19, Sadra teaches a manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a photoresist pattern to a first thickness on a semiconductor substrate on which a gate electrode has been formed (28, Fig. 1A, para [0027] describes a resist layer which can be seen on a semiconductor substrate 22 wherein a gate structure 21 has been formed);
forming a lightly doped drain (LDD) region, by implanting low-concentration second conductivity-type impurity ions in the well region (para [0058] describes wherein the LDD dopant is of a first dopant species according to an N-type or P-type) using both the photoresist pattern and the gate electrode as a mask (15 and 24, Fig. 1A, para [0027] describes an LDD implant process 15 which form the LDD regions 24 through implantation of appropriate dopant species atoms through openings in the resist layer wherein the gate electrode can be seen masking the implant from reaching areas under the gate electrode with respect to the angle of the implant);
reducing the photoresist pattern to a second thickness, by removing a portion of the photoresist pattern (730, Fig. 7 and Fig. 10 – Fig. 12, para [0052] describes an etch or trim process to reduce the thickness of the resist layer and round the corners), wherein the thickness of the photoresist pattern is in a direction perpendicular to a top surface of the semiconductor substrate (1010y and 1020y, Fig. 10-Fig. 12, para [0061] describes wherein the partially reduced resist layer has a reduced resist thickness 1020y after a portion of the original photoresist thickness 1010y which is perpendicular to a top surface of the semiconductor substrate has been removed);
forming a halo region below the LDD region (32, Fig. 1B, para [0028] describes an angled pocket implant forming halo region 32), by implanting the first conductivity-type impurity ions (para [0058] describes wherein the pocket implant is of a second dopant species different than the LDD implant according to an N-type or P-type) using both the photoresist pattern that has been reduced to the second thickness and the gate electrode as a mask (730 and 740, Fig. 7, para [0052] describes using a reduced photoresist pattern as a mask to form the pocket implant wherein the gate electrode can be seen masking the implant from reaching areas under the gate electrode with respect to the angle of the implant);
wherein the second thickness is 30% to 95% of the first thickness (, 1010y, 1020y and 1030y, Fig. 10-Fig. 12, 1010y, 1020y and 1030y, para [0050] describes wherein the resist trim process may be adjusted to reduce the thickness of the resist to any arbitrary value for optimal reduction in pocket shadowing while maintaining good blocking in other areas wherein said resulting reduced thicknesses are shown in Fig. 11 and Fig. 12 wherein a dashed height 1010y represents a first thickness and said arbitrary values appear to be roughly 75% 1020y and 50% 1030y used in reducing the first thickness in order to implement an ion implant with optimal reduction in pocket shadowing wherein said ranges fall within the 30% to 95% thickness range),
wherein the photoresist pattern that has been reduced to the second thickness has an inclined side surface (STA, annotated Fig. 12 depicts wherein rounded corner 1030r of the reduced photoresist pattern 1030 will result in at least a portion of a side surface of the photoresist to have an inclined angle as shown in annotated Fig. 12 below) and has a smaller inclined angle relative to the top surface of the semiconductor substrate than a side surface of the photoresist pattern that has the first thickness (FTA, annotated Fig. 12 depicts wherein a side surface of the first photoresist represented by the dashed line is substantially perpendicular to the front surface of the semiconductor substrate having approximately a 90 degree angle FTA wherein a rounded corner of a side surface shown by second thickness angle STA will have an angle less than 90 degrees as it approaches a 45 degree rounding).
Sadra fails to explicitly disclose forming a well region by implanting first conductivity-type impurity ions using both the photoresist pattern and the gate electrode as a mask; and removing the photoresist pattern; and wherein forming the halo region comprises implanting the low-concentration second conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the top surface of the semiconductor substrate.
However, Yamamoto teaches a similar manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a well region using both the photoresist pattern and the gate electrode as a mask (PW1 and NW1, Fig. 1, para [0042] describes forming a p-type well and an n-type well in the semiconductor substrate through an ion implantation process wherein upon combining the well region implantation with the substrate of Sadra the photoresist pattern and gate electrode would be present functioning as a mask for the implant process); and
removing the photoresist pattern (RP3, Fig. 9, para [0064] and para [0070] and para [0112] describes wherein resist pattern RP3 is removed by ashing wherein resist pattern RP3 is utilized during the extension region and halo region implantation wherein upon combining Sadra with Yamamoto the resulting resist pattern RP3 would be a reduced second thickness photoresist pattern); and
wherein forming the halo region comprises implanting the low-concentration first conductivity-type impurity ions at an angle of 25 to 50 with respect to the direction that is perpendicular to the front surface of the semiconductor substrate (para [0063] describes an oblique ion implantation process being performed at an angle inclined by more 15 degrees or more and 45 degrees or less with respect to the perpendicular semiconductor substrate wherein said oblique ion implantation is described as being used for a p-type halo region implantation in para [0112] wherein an angle of approximately 45 degrees falls with the range of 25 degrees to 50 degrees)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra and Yamamoto to further disclose a manufacturing method of a semiconductor device comprising forming a well region in the semiconductor substrate to provide the advantage of enabling a region to be used for controlling a threshold value of the semiconductor device providing the device with advanced functionality and flexibility (Yamamoto, para [0042]), and to disclose removing the photoresist pattern in order to provide the well-known advantage of removing unnecessary device components that may cause unwanted effects and to further disclose an angle of the halo region ion implantation in order to provide the advantage of enabling an ion implant which may reach a region under the gate electrode (Yamamoto, para [0063]).
The combination of Sadra and Yamamoto fail to explicitly disclose wherein an inclined side surface extends towards the semiconductor substrate.
However, Ghaemmaghami teaches a similar manufacturing method of a semiconductor device wherein a photoresist pattern has an inclined side surface that extends towards the semiconductor substrate (402, Fig. 4, column 3, lines 31-37 describe a photoresist pattern 402 of a shorter height than a thick photoresist pattern used in processing step 302 such as shown by photoresist pattern 213 wherein second photoresist pattern 402 has an inclined side surface as shown in Fig. 4 that extends towards a semiconductor substrate further wherein upon combining Sadra with Ghaemmaghami the second photoresist pattern 402 of Ghaemmaghami may be formed by reducing a height of a first photoresist pattern instead of replacing the first photoresist pattern).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra and Yamamoto with Ghaemmaghami to further disclose a manufacturing method of a semiconductor device comprising a photoresist pattern that has an inclined side surface that extends towards a semiconductor substrate in order to provide the well-known advantage of matching a side surface of a photoresist pattern with an implantation angle of an angled implant resulting in a more effective halo implant process.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kayvan Sadra et al. (US 2006/0134889 A1; hereinafter “Sadra”) in view of Yoshiki Yamamoto (US 2018/0342537 A1; hereinafter “Yamamoto”) and in view of Ahmad Ghaemmaghami et al. (US 7192836 B1; hereinafter “Ghaemmaghami”) and in further view of Edward E. Ehrichs (US 7144782 B1; hereinafter “Ehrichs”).
Regarding Claim 6, the combination of Sadra, Yamamoto and Ghaemmaghami teach the manufacturing method of the semiconductor device of claim 1, wherein the removing the photoresist pattern that has been reduced to the second thickness (Yamamoto, RP3, Fig. 9, para [0064] and para [0070] and para [0112] describes wherein resist pattern RP3 is removed wherein resist pattern RP3 is utilized during the extension region and halo region implantation wherein upon combining Sadra with Yamamoto the resulting resist pattern RP3 would be a reduced second thickness photoresist pattern) comprises:
ashing the photoresist pattern (Yamamoto, RP3, Fig. 9, para [0064] and para [0070] and para [0112] describes wherein resist pattern RP3 is removed by ashing);
The combination of Sadra, Yamamoto and Ghaemmaghami fail to explicitly disclose stripping the photoresist pattern.
However, Ehrichs teaches a similar manufacturing method of a semiconductor device, wherein the removing the photoresist pattern that has been reduced to the second thickness comprises:
stripping the photoresist pattern (80, Fig. 7, column 7, lines 52-54 describe wherein the mask is stripped wherein the stripping may be accomplished by ashing and solvent stripping).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra, Yamamoto and Ghaemmaghami with Ehrichs to further disclose a manufacturing method of a semiconductor device wherein removing the photoresist pattern comprises an ashing and stripping process to provide the well-known advantage of ensuring the organic masking material is fully removed preventing unwanted effects such as shorting between device components.
Claim 7, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kayvan Sadra et al. (US 2006/0134889 A1; hereinafter “Sadra”) in view of Yoshiki Yamamoto (US 2018/0342537 A1; hereinafter “Yamamoto”) and in view of Ahmad Ghaemmaghami et al. (US 7192836 B1; hereinafter “Ghaemmaghami”) and in further view of Guowel Zhang (US 2015/0069522 A1; hereinafter “Zhang”).
Regarding Claim 7, the combination of Sadra, Yamamoto and Ghaemmaghami disclose all the limitations of claim 1.
Sadra, Yamamoto and Ghaemmaghami fail to explicitly disclose the manufacturing method of the semiconductor device of claim 1, wherein forming the well region comprises implanting the first conductivity-type impurity ions at an angle of 100 or less with respect to the direction that is perpendicular to the front surface of the semiconductor substrate.
However, Zhang teaches a similar method of manufacturing a semiconductor device, wherein forming the well region comprises implanting the first conductivity-type impurity ions at an angle of 100 or less with respect to the direction that is perpendicular to the front surface of the semiconductor substrate (Zhang, 117, Fig. 2f, para [0045] describes wherein the well implant is performed at a tilt angle of 0-7 degrees with respect to a vertical direction, which is perpendicular to the substrate surface).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra, Yamamoto and Ghaemmaghami with Zhang to further disclose a manufacturing method of a semiconductor device wherein an angle of the well region implant occurs at an angle of 100 or less with respect to a direction that is perpendicular to the front surface of the semiconductor substrate in order to provide an implant process which may only require a single implant compared to a tilted implant which may occur at an angle greater than 0 degrees, further lowering the cost of the semiconductor manufacturing process (Zhang, para [0045]).
Regarding Claim 9, the combination of Sadra, Yamamoto and Ghaemmaghami disclose all the limitations of claim 1.
Sadra, Yamamoto and Ghaemmaghami fail to explicitly disclose the manufacturing method of the semiconductor device of claim 1, wherein the forming the photoresist pattern to the first thickness comprises: depositing a photoresist layer to a thickness of 1.0 pm to 4 pm; and patterning the photoresist layer.
However, Zhang teaches a similar method of manufacturing a semiconductor device, wherein the forming the photoresist pattern to the first thickness comprises:
depositing a photoresist layer to a thickness of 1.0 µm to 4 µm (272, Fig. 2f, para [0044] describes wherein the height or thickness of the mask layer may be 2-3 µm above the gates, wherein the gate electrodes are described in para [0020] as being 500-5000 angstroms thick, or 0.05-0.5 µm, and the gate dielectric is described as being 10-500 angstroms thick, or 0.001-0.05 µm, thus making the first thickness of the mask layer between 2.051 – 3.55 µm thick); and
patterning the photoresist layer (para [0044] describes wherein the mask layer may be patterned by photolithographic techniques).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra, Yamamoto and Ghaemmaghami with Zhang to further disclose a manufacturing method of a semiconductor device wherein a height of a photoresist layer is 1µm to 4µm and said photoresist layer is patterned to provide the further advantage of enabling a mask layer to have a height sufficient to prevent a subsequent well implant from penetrating the masked areas and only penetrate the desired patterned areas of the photoresist (Zhang, para [0044]).
Regarding Claim 20, the combination of Sadra, Yamamoto and Ghaemmaghami disclose all the limitations of claim 19.
Sadra, Yamamoto and Ghaemmaghami fail to explicitly disclose the manufacturing method of the semiconductor device of claim 19, wherein the first thickness is 1.0 µm to 4.0 µm.
However, Zhang teaches a similar method of manufacturing a semiconductor device, wherein the first thickness is 1.0 µm to 4.0 µm (Zhang, 272, Fig. 2f, para [0044] describes wherein the height or thickness of the mask layer may be 2-3 µm above the gates, wherein the gate electrodes are describes in para [0020] as being 500-5000 angstroms thick, or 0.05-0.5 µm, and the gate dielectric is described as being 10-500 angstroms thick, or 0.001-0.05 µm, thus making the first thickness of the mask layer between 2.051 – 3.55 µm thick).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Sadra, Yamamoto and Ghaemmaghami with Zhang to further disclose a manufacturing method of a semiconductor device wherein a height of a photoresist layer is 1µm to 4µm to provide the further advantage of enabling a mask layer to have a height sufficient to prevent a subsequent well implant from penetrating the masked areas (Zhang, para [0044]).
Response to Arguments
Applicant’s arguments with respect to claims 1-7, 9, 11-15 and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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