IMAGE SENSOR SUBSTRATE AND IMAGE SENSOR INCLUDING THE SAME

DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on 09/16/2025 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner. Response to Amendment The amendment with respect to claims 1-9, 12, and 16-18 filed on 09/16/2025 have been fully considered for examination based on their merits. Response to Arguments Applicant’s arguments, see Remarks, pages 7-10, filed 09/16/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of TSAI and CHA. Regarding Independent Claim 1. The Applicant argues that the cited art fails to disclose or suggest the amended independent claim 1 recites: “a semiconductor layer on the semiconductor substrate…from 1x1016 cm-3 go 6x1016 cm-3.” The Applicant further argues that LU does not disclose “a semiconductor layer…having an epitaxial region having a boron (B)… from 1x1016 cm-3 go 6x1016 cm-3” as recited in amended independent claim 1. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, TSAI teaches an image sensor comprising: a semiconductor substate layer having boron (B) concentration therein in the range from 1x1018 atom/cm3 to 3x1020 atom/cm-3. TSAI as modified by CHA teaches an image sensor comprising: a semiconductor epitaxial layer on the semiconductor substrate layer, said semiconductor epitaxial layer having an epitaxial region having a boron (B) concentration therein in a range from 1x1014 cm-3 to 1x1018 cm-3. Regarding Claim(s) 2-20. The independent Claim(s) 6 and 16, and dependent claims 2-5, 7-15 and 17-20 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min-Ying Tsai et al, (hereinafter TSAI), US 20170194194 A1, in view of Han-Seob Cha, (hereinafter CHA), US 20090042334 A1. Regarding Claim 1, TSAI teaches an image sensor substrate (CMOS image sensor, [0024]), comprising: a semiconductor substrate layer (Fig. 10, 10, primary substrate also called a temporary substrate, [0020]) having a boron (B) concentration therein in a range from 3x1018 cm-3 to 1x1019 cm-3 (P+ wafer, having a boron concentration of between 1E18 and 5E20 boron atom/cm3, preferably between about 1E18 and about 3E20 boron atom/cm3, [0020]). TSAI does not explicitly disclose an image sensor substrate comprising: a semiconductor epitaxial layer on the semiconductor substrate layer, said semiconductor epitaxial layer having an epitaxial region having a boron (B) concentration therein in a range from 1x1016 cm-3 to 6x1016 cm-3. CHA teaches an image sensor substrate (Fig. 2, CMOS image sensor, [0023]) comprising: a semiconductor epitaxial layer (Fig. 2, 100, SiGe epitaxial layer, [0023]) on the semiconductor substrate layer (Fig. 2, 21), said semiconductor epitaxial layer (Fig. 2, 100, SiGe epitaxial layer, [0023]) having an epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) having a boron (B) concentration therein in a range from 1x1016 cm-3 to 6x1016 cm-3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TSAI to incorporate the teachings of CHA, such that an image sensor substrate comprising: a semiconductor epitaxial layer on the semiconductor substrate layer, said semiconductor epitaxial layer having an epitaxial region having a boron (B) concentration therein in a range from 1x1016 cm-3 to 6x1016 cm-3, so that the high doping concentration level can improve light characteristics of wavelengths corresponding to a range of blue colors as well as wavelengths corresponding to a range of green colors (CHA, [0043]). Regarding Claim 2, TSAI as modified by CHA teaches the image sensor substrate of Claim 1. CHA further teaches the image sensor substrate (Fig. 2, CMOS image sensor, [0023]), wherein the epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) has a boron (B) concentration therein in a range from 4x1016 cm-3 to 5.5x1016 cm-3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Regarding Claim 3, TSAI as modified by CHA teaches the image sensor substrate of Claim 1. CHA further teaches the image sensor substrate (Fig. 2, CMOS image sensor, [0023]), wherein the epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) has a boron (B) concentration therein of 5x1016 cm-3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Regarding Claim 4, TSAI and CHA combined teaches the image sensor substrate of Claim 1, wherein the concentration of boron (B) in the substrate layer (TSAI: P+ wafer, having a boron concentration of between 1E18 and 5E20 boron atom/cm3, preferably between about 1E18 and about 3E20 boron atom/cm3, [0020]) is fifty (50) or more times greater (see the NOTE for calculation based on the art chosen) than the concentration of boron (B) in the epitaxial region (CHA: a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). [NOTE: Ratio = Concentration of Boron (lower limit) in substrate/Concentration of Boron (lower limit) in the epitaxial layer = 1018/1015 = 103 = 1000 or >50 times; similarly, Ratio = Concentration of Boron (upper limit) in substrate/Concentration of Boron (upper limit) in the epitaxial layer = 1020/1018 = 102 = 100 or >50 times]. Regarding Claim 5, TSAI as modified by CHA teaches the image sensor substrate of Claim 1. CHA further teaches the image sensor substrate (Fig. 2, CMOS image sensor, [0023]), wherein the epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) has a thickness of at least 10 µm (the second SiGe epitaxial layer, 23 is in a thickness ranging from approximately 1µm to approximately 5µm and the third SiGe epitaxial layer, 24 is in a thickness ranging from approximately 3µm to approximately 8µm, [0030], [0033]). [NOTE: based on the above data, the total thickness of 23/24 epitaxial layers ranging approximately from 1µm to 13µm]. Claim(s) 6-8, 10-11 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takumi Oka et al, (hereinafter OKA), US 20210112213 A1, in view of CHA. Regarding Claim 6, OKA teaches in Figures 31/43, an image sensor (Fig. 43, 801, imaging device), comprising: a first substrate (Figs. 31/43, 433/941) having first (Fig. 31, 433a) and second opposing surfaces (annotated Figure 31) thereon and a plurality of unit pixels (Figs. 31/43, 442/864, effective pixel array/ pixel array unit) therein, with each unit pixel including a photoelectric conversion layer (Figs. 23/43, PD), a floating diffusion region (Fig. 16, 213/FD, [0542]), and a transfer transistor (Fig. 16, 211, [0542]) electrically connecting the photoelectric conversion layer to the floating diffusion region (Fig. 5, [0128-0129]; Fig. 43, 946, connection wiring lines); a pixel isolation pattern (Figs. 31, 430, semiconductor well region, annotated Figure 31, [0401]), which at least partially penetrates the first substrate to thereby define each of the plurality of unit pixels; a microlens (Figs. 31/43, lens array/chip lenses) extending on the second surface (annotated Figure 31) of the first substrate; a second substrate (Figs. 31/43, (437/459)/(942/922), multilevel wiring layer) on the first surface of the first substrate, said second substrate having a fourth surface (annotated Figure 31) that faces the first surface, and a third surface (annotated Figure 31) extending opposite the fourth surface; and a source follower transistor (Fig. 18, 252, DSF transistor/Dummy Source Follower circuit transistor, [0275]), a select transistor (Fig. 18, 251, switch transistor [0275]), and a reset transistor (Fig. 18, 232, [0269]) having respective terminals electrically connected to the floating diffusion region, adjacent the fourth surface of the second substrate (Fig. 18, 221, [0269]). OKA does not explicitly disclose an image sensor comprising: wherein a concentration of boron (B) in an epitaxial region in the first substrate is in a range from 1x1016 atoms/cm3 to 6x1016 atoms/cm3. CHA teaches an image sensor (Fig. 2, CMOS image sensor, [0023]) comprising: wherein a concentration of boron (B) in an epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) in the first substrate (Fig. 2, 21/23/24, substrate/second and third epitaxial layers, [0021-0022]) is in a range from 1x1016 atoms/cm3 to 6x1016 atoms/cm3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OKA to incorporate the teachings of CHA, such that an image sensor substrate comprising: wherein a concentration of boron (B) in an epitaxial region in the first substrate is in a range from 1x1016 atoms/cm3 to 6x1016 atoms/cm3, so that the high doping concentration level can improve light characteristics of wavelengths corresponding to a range of blue colors as well as wavelengths corresponding to a range of green colors (CHA, [0043]). PNG media_image1.png 1042 875 media_image1.png Greyscale Regarding Claim 7, OKA as modified by CHA teaches the image sensor of Claim 6. CHA further teaches the image sensor (Fig. 2, CMOS image sensor, [0023]), wherein the concentration of boron (B) in the epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) in the first substrate (Fig. 2, 21/23/24, substrate/second and third epitaxial layers, [0021-0022]) is in a range from 4x1016 cm-3 to 5.5x1016 cm-3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Regarding Claim 8, OKA as modified by CHA teaches the image sensor of Claim 7. CHA further teaches the image sensor substrate (Fig. 2, CMOS image sensor, [0023]), wherein the concentration of boron (B) in an epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) in the first substrate (Fig. 2, 21/23/24, substrate/second and third epitaxial layers, [0021-0022]) is 5x1016 atoms/cm3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Regarding Claim 10, OKA as modified by CHA teaches the image sensor of Claim 6. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising: a first wiring structure (437; Fig. 44, 942, multi-level wiring layer), which extends on the first surface (433a) of the first substrate (433; Fig. 44, 941) and comprises a first inter-wiring insulating layer (453, inter insulating film), and a first wiring pattern (435 a through d, wiring lines, [0401]) in the first inter- wiring insulating layer; and a second wiring structure (459; Fig. 44, 922, multi-level wiring layer), which extends on the fourth surface of the second substrate (Figs. 31/43, (437/459)/(942/922) and comprises a second inter-wiring insulating layer (456, inter insulating film), and a second wiring pattern (457 a through d, wiring lines, [0403]) in the second inter-wiring insulating layer; and wherein the first inter-wiring insulating layer and the second inter-wiring insulating layer are bonded to each other (annotated Figure 31). PNG media_image2.png 1042 990 media_image2.png Greyscale Regarding Claim 11, OKA as modified by CHA teaches the image sensor of Claim 10. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising a through-via (452/464, conductive vias; Fig. 45, 945, chip through vias), which at least partially penetrates the second substrate (Figs. 31/43, (437/459)/(942/922). Regarding Claim 13, OKA as modified by LU teaches the image sensor of Claim 6. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising: a third substrate (Figs. 31/43, 454, second semiconductor substrate) extending on the third surface (annotated Figure 31) of the second substrate (Figs. 31/43, (437/459)/(942/922); and a plurality of logic circuits (Figs. 31, 455) configured to control the source follower transistor, the select transistor, and the reset transistor (Fig. 31, Tr11, Tr12, Tr13, Tr14), on the third substrate. Regarding Claim 14, OKA as modified by LU teaches the image sensor of Claim 13. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising a memory device (Fig. 35, 543, SRAM memory) and a logic device (Figs. 31, 455) disposed under the third substrate (Figs. 31/43, 454, second semiconductor substrate; Fig. 35, third layer chip, 503). Regarding Claim 15, OKA as modified by CHA teaches the substrate of Claim 13. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising: a second wiring structure (459; Fig. 44, 922, multi-level wiring layer) extending on the third surface (annotated Figure 31) of the second substrate (Figs. 31/43, (437/459)/(942/922) and comprising a second inter-wiring insulating layer (456, inter insulating film) and a second wiring pattern (457 a through d, wiring lines, [0403]) in the second inter-wiring insulating layer; and a third wiring structure (Fig. 31, 455, logic circuit; Fig. 44, 930, rewiring line; 927, connection conductor) extending on the third substrate (Fig. 31, 455, second semiconductor substrate; Fig. 44, 921) and comprising a third inter-wiring insulating layer and a third wiring pattern in the third inter-wiring insulating layer (Fig. 31, logic circuit, wiring insulating layer and wiring pattern not shown); and wherein the second inter-wiring insulating layer and the third inter-wiring insulating layer are bonded to each other (annotated Figure 31). Claim(s) 9, 12 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over OKA, in view CHA, and further in view of Cheng-Hsien Chou et al, (hereinafter CHOU), US 20140264719 A1. Regarding Claim 9, OKA as modified by CHA teaches the image sensor of Claim 6. OKA as modified by CHA does not explicitly disclose an image sensor: wherein the concentration of boron (B) in an epitaxial region in the first substrate is substantially uniform in a region between a sidewall of the pixel isolation pattern and the photoelectric conversion layer. CHOU teaches the image sensor (Fig. 1, 100): wherein the concentration of boron (B) in an epitaxial region in the first substrate (Fig. 1, 106, the substrate includes an epitaxial layer overlying a bulk semiconductor, [0013]) is substantially uniform in a region between a sidewall of the pixel isolation pattern and the photoelectric conversion layer (annotated Figure 1, [0039]). PNG media_image3.png 792 978 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have OKA as modified by CHA to incorporate the teachings of CHOU, such that the image sensor, wherein the concentration of boron (B) in an epitaxial region in the first substrate is substantially uniform in a region between a sidewall of the pixel isolation pattern and the photoelectric conversion layer, so that the more uniform implantation and greater doping concentration results in greater isolation between sensor elements (102) thereby reducing dark current and crosstalk [CHOU, [0039]). Regarding Claim 12, OKA as modified by CHA teaches the image sensor of Claim 6. OKA as modified by LU does not explicitly disclose an image sensor: wherein the concentration of boron (B) in an epitaxial region in the first substrate is substantially uniform in a region between the second surface of the first substrate and the photoelectric conversion layer. CHOU teaches the image sensor (Fig. 1, 100): wherein the concentration of boron (B) in an epitaxial region in the first substrate (Fig. 1, 106, the substrate includes an epitaxial layer overlying a bulk semiconductor, [0013]) is substantially uniform in a region between the second surface of the first substrate and the photoelectric conversion layer (annotated Figure 1, [0039]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have OKA as modified by LU to incorporate the teachings of CHOU, such that the image sensor, wherein the concentration of boron (B) in an epitaxial region in the first substrate is substantially uniform in a region between the second surface of the first substrate and the photoelectric conversion layer, so that the more uniform implantation and greater doping concentration results in greater isolation between sensor elements (102) thereby reducing dark current and crosstalk [CHOU, [0039]). PNG media_image3.png 792 978 media_image3.png Greyscale Regarding Claim 16, OKA teaches in Figures 31/43, an image sensor (Fig. 43, 801, imaging device), comprising: a first substrate (Figs. 31/43, 433/941) having first (Fig. 31, 433a) and second opposing surfaces (annotated Figure 31) thereon; a plurality of unit pixels (Figs. 31/43, 442/864, effective pixel array/ pixel array unit), which are each configured to include, in the first substrate, a photoelectric conversion layer (Figs. 23/43, PD), a floating diffusion region (Fig. 16, 213/FD, [0542]), and a transfer transistor (Fig. 16, 211, [0542]) electrically connecting the photoelectric conversion layer to the floating diffusion region (Fig. 5, [0128-0129]; Fig. 43, 946, connection wiring lines); a pixel isolation pattern (Figs. 31, 430, semiconductor well region, annotated Figure 31, [0401]), which at least partially penetrates the first substrate and defines lateral dimensions of each of the plurality of the unit pixels; a microlens (Figs. 31/43, lens array/chip lenses) extending on the second surface (annotated Figure 31) of the first substrate; a second substrate (Figs. 31/43, (437/459)/(942/922), multilevel wiring layer) having a fourth surface (annotated Figure 31) on the first surface of the first substrate, and a third surface (annotated Figure 31 extending opposite the fourth surface; and a source follower transistor (Fig. 18, 252, DSF transistor/Dummy Source Follower circuit transistor, [0275]), a select transistor (Fig. 18, 251, switch transistor [0275]), and a reset transistor (Fig. 18, 232, [0269]), having respective terminals electrically connected to the floating diffusion region, on the fourth surface of the second substrate (Fig. 18, 221, [0269]); a third substrate (Figs. 31/43, 454, second semiconductor substrate) extending on the third surface of the second substrate; and a plurality of logic circuits (Figs. 31, 455) within the third substrate, which are configured to control ([0403]) the source follower transistor, the select transistor, and the reset transistor (Fig. 31, Tr11, Tr12, Tr13, Tr14); OKA does not explicitly disclose an image sensor comprising: wherein a concentration of boron (B) in an epitaxial region in the first substrate is in a range from 4x1016 atoms/cm3 to 5.5x1016 atoms/cm3. PNG media_image4.png 1042 977 media_image4.png Greyscale CHA teaches an image sensor (Fig. 2, CMOS image sensor, [0023]) comprising: wherein a concentration of boron (B) in an epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) in the first substrate (Fig. 2, 21/23/24, substrate/second and third epitaxial layers, [0021-0022]) is in a range from 4x1016 atoms/cm3 to 5.5x1016 atoms/cm3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified OKA to incorporate the teachings of CHA, such that an image sensor substrate comprising: wherein a concentration of boron (B) in an epitaxial region in the first substrate is in a range from 4x1016 atoms/cm3 to 5.5x1016 atoms/cm3, so that the high doping concentration level can improve light characteristics of wavelengths corresponding to a range of blue colors as well as wavelengths corresponding to a range of green colors (CHA, [0043]). OKA as modified by CHA does not explicitly disclose an image sensor comprising: wherein the concentration of boron (B) in an epitaxial region in the first substrate is substantially uniform in a region extending from a sidewall of the pixel isolation pattern toward the photoelectric conversion layer. CHOU teaches disclose an image sensor (Fig. 1, 100) comprising: wherein the concentration of boron (B) in an epitaxial region in the first substrate (Fig. 1, 106, the substrate includes an epitaxial layer overlying a bulk semiconductor, [0013]) is substantially uniform in a region extending from a sidewall of the pixel isolation pattern toward the photoelectric conversion layer (annotated Figure 1, [0039]). PNG media_image3.png 792 978 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have OKA as modified by CHA to incorporate the teachings of CHOU, such that an image sensor, wherein the concentration of boron (B) in an epitaxial region in the first substrate is substantially uniform in a region extending from a sidewall of the pixel isolation pattern toward the photoelectric conversion layer, so that the more uniform implantation and greater doping concentration results in greater isolation between sensor elements (102) thereby reducing dark current and crosstalk [CHOU, [0039]). Regarding Claim 17, OKA as modified by CHA and CHOU teaches the image sensor of Claim 16. CHOU further teaches the image sensor (Fig. 1, 100), wherein the concentration of boron (B) in an epitaxial region in the first substrate (Fig. 1, 106, the substrate includes an epitaxial layer overlying a bulk semiconductor, [0013]) is substantially uniform in a region extending from the second surface (Fig. 1, 110, back surface) of the first substrate (Fig. 1, 106, the substrate includes an epitaxial layer overlying a bulk semiconductor, [0013]) toward the photoelectric conversion layer (annotated Figure 1, [0039]). PNG media_image5.png 823 976 media_image5.png Greyscale Regarding Claim 18, OKA as modified by CHA and CHOU teaches the image sensor of Claim 16. CHA further teaches the image sensor (Fig. 2, CMOS image sensor, [0023]) of Claim 7, wherein the concentration of boron (B) in an epitaxial region (Fig. 2, 23/24, second and third epitaxial layers, [0021]) in the first substrate (Fig. 2, 21/23/24, substrate/second and third epitaxial layers, [0021-0022]) is 5x1016 atoms/cm3 (a concentration level of boron doped epitaxial layer, 23, ranges from approximately 1x1015 cm-3 to approximately 1x1018 cm-3; a concentration level of boron doped epitaxial layer, 24, ranges from approximately 1x1014 cm-3 to approximately 1x1017 cm-3, [0021]). Regarding Claim 19, OKA as modified by CHA and CHOU teaches the image sensor of Claim 16. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising a memory device (Fig. 35, 543, SRAM memory) extending adjacent the third substrate (Figs. 31/43, 454, second semiconductor substrate; Fig. 35, third layer chip, 503). Regarding Claim 20, OKA as modified by CHA and CHOU teaches the substrate of Claim 16. OKA further teaches in Figures 31/43, the image sensor (Fig. 43, 801, imaging device), further comprising: a first wiring structure (437; Fig. 44, 942, multi-level wiring layer), which extends on the first surface (433a) of the first substrate (433; Fig. 44, 941) and comprises a first inter-wiring insulating layer (453, inter insulating film), and a first wiring pattern (435 a through d, wiring lines, [0401]) in the first inter- wiring insulating layer; and a second wiring structure (459; Fig. 44, 922, multi-level wiring layer), which extends on the fourth surface of the second substrate (Figs. 31/43, (437/459)/(942/922) and comprises a second inter-wiring insulating layer (456, inter insulating film), and a second wiring pattern (457 a through d, wiring lines, [0403]) in the second inter-wiring insulating layer; and wherein the first inter-wiring insulating layer and the second inter-wiring insulating layer are bonded to each other (annotated Figure 31). PNG media_image6.png 1042 977 media_image6.png Greyscale Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20150054111 A1 – Figure 1, [0032] STATEMENT OF RELEVANCE – Cross-sectional view illustrating a structure of the SPAD, wherein the substrate, 201 is the same type as the epitaxial layer, 202. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812