Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of the first and second wordline in the reply filed on 11/09/25 is acknowledged. Furthermore, note that applicant’s amendments to claims 13 and 14 renders the restriction between different memory cells moot and therefore the restriction requirement between the 1T-1F memory cell and 1T-1C memory cell embodiments is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 recites the limitation "the second storage node" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryan et al., US 2019/0212919.
Ryan et al. shows the invention as claimed including a semiconductor device, comprising:
A first memory (for example, 105b in fig. 4) including first capacitors that are vertically stacked in a first direction (note in paragraph 0068 that the memories can be vertically stacked); and
A second memory (for example, 105b) that is laterally spaced apart from the first memory in a second direction and that includes second capacitors that are vertically stacked in the first direction (note in paragraph 0068 that the memories can be vertically stacked, and additionally see paragraphs 0026-0038 and 0052).
Concerning claim 2, note that the first capacitors can include ferroelectric capacitors (see paragraphs 0019-0022).
With respect to dependent claim 3, note that the second capacitors can include paraelectric capacitors (see, for example, paragraphs 0019-0022).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12, 15-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al., US 2019/0212919 in view of Mathuriya et al., US 2023/0251828 and Lee et al., US 2021/0013210.
With respect to independent claim 12, Ryan et al. shows the invention substantially as claimed including a semiconductor device, comprising:
A first memory (for example, 105b in fig. 4) including ferroelectric capacitors (see paragraphs 0019-0022) that are vertically stacked in a first direction (note in paragraph 0068 that the memories can be vertically stacked); and a second memory (for example, 105b) laterally spaced apart from the first memory cell and including paraelectric capacitors (see paragraphs 0019-0022) that are vertically stacked in the first direction, wherein each of the ferroelectric capacitors includes a first storage node.
Ryan et al. does not expressly disclose wherein each of the paraelectric capacitors includes a cylindrical shaped storage node. Mathuriya et al. discloses a paraelectric capacitor comprising a cylindrically shaped storage node (see paragraph 0215). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Ryan et al. so as to comprise a paraelectric capacitor having a cylindrically shaped storage node because Mathuriya et al. shows such a configuration to be a suitable paraelectric capacitor configuration.
Ryan et al. and Mathuriya et al. are applied as above but do not expressly disclose that the first storage node of the ferroelectric capacitor has a vertical flat plate shape. Lee et al. discloses ferroelectric capacitors whereby a first storage node 114 can have a vertical flat plate shape (see, for example, paragraph 0058 and fig. 2A). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Ryan et al. so as to form the first ferroelectric capacitors with a vertical flat plate shape because this is shown to be a suitable configuration for a ferroelectric capacitor.
Concerning dependent claim 15, Ryan et al. and Mathhuriya et al. do not expressly disclose note that the first plate nodes of the first capacitors extend vertically to couple to each other. However, Lee et al. discloses wherein the first plate nodes of the first capacitors can extend vertically to couple to each other (note that in Lee et al. the plate node may be coupled to the plate lines that are coupled to each other---see paragraphs 0057-0058). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Ryan et al. and Mathuriya et al. so as to comprise the vertical coupling structure of Lee et al. because in such a way effective communication between devices can be attained.
Regarding dependent claim 16, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form a storage node/plate node configuration in the paraelectric capacitor as in the ferroelectric capacitor in the device of Ryan et al. modified by Mathhuriya et al. and Lee et al. since this is shown by Lee et al. to be a suitable configuration for a capacitor.
With respect to dependent claims 17-18, note that Lee et al. also discloses a memory further including: a bit line 120 extending in the first direction; a channel layer 118 extending from the bit line in the second direction; and a single word line 128 (see claim 18) extending in a third direction crossing the channel layer and over the channel layer.
With respect to dependent claim 20, note that Ryan et al., Mathuriya et al., and Lee et al. are applied as above but do not expressly disclose peripheral circuits vertically positioned at a lower or higher level than the first and second memories. However, official notice is taken that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form peripheral circuits at a lower or higher level than the memories since they are an integral part of a memory containing semiconductor chip and having the peripheral circuits at a higher or lower level because in such a way the space used on the semiconductor chip can be minimized.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al., US 2019/0212919 in view of Mathuriya et al., US 2023/0251828.
Concerning dependent claim 6, Ryan et al. is applied as above but does not expressly disclose the second capacitors including a storage node having a cylindrical shape. However, Mathuriya et al. discloses a paraelectric capacitor comprising a cylindrically shaped storage node (see paragraph 0215). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Ryan et al. so as to comprise a paraelectric capacitor having a cylindrically shaped storage node because Mathuriya et al. shows such a configuration to be a suitable paraelectric capacitor configuration.
Claim(s) 4-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al., US 2019/0212919 in view of Lee et al., US 2021/0013210.
Ryan et al. is applied as above but does not expressly disclose wherein each of the first capacitors includes a first storage node having a vertical flat plate shape. Lee et al. discloses ferroelectric capacitors whereby a first storage node can have a vertical flat plate shape (see, for example, paragraph 0058 and fig. 2A). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Ryan et al. so as to form the first ferroelectric capacitors with a vertical flat plate shape because this is shown to be a suitable configuration for a ferroelectric capacitor.
Regarding dependent claim 5, Ryan et al. does not expressly disclose note that the first plate nodes of the first capacitors extend vertically to couple to each other. However, Lee et al. discloses wherein the first plate nodes of the first capacitors can extend vertically to couple to each other (note that in Lee et al. the plate node may be coupled to the plate lines that are coupled to each other---see paragraphs 0057-0058). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Ryan et al. so as to comprise the vertical coupling structure of Lee et al. because in such a way effective communication between devices can be attained.
Concerning dependent claim 7, note that Lee et al. additionally discloses a memory further including: a bit line 120 extending in the first direction; a channel layer 118 extending from the bit line in the second direction; and a word line 128 extending in a third direction crossing the channel layer and over the channel layer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al., US 2019/0212919.
Ryan et al. is applied as above but does not expressly disclose peripheral circuits positioned in the first direction at a lower or higher level than the first and second memories. However, official notice is taken that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form peripheral circuits at a lower or higher level than the memories since they are an integral part of a memory containing semiconductor chip and having the peripheral circuits at a higher or lower level because in such a way the space used on the semiconductor chip can be minimized.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al., US 2019/0212919 in view of Mathuriya et al., US 2023/0251828 as applied to claims 12, 15-18, and 20 above, and further in view of Gong et al., US 2022/0189546.
Ryan et al. and Mathuriya et al. are applied as above but do not expressly disclose wherein the first memory comprises a 1T-1F configuration. Gong et al. discloses the use of a 1T-1F memory configuration (see paragraph 0082). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was made to utilize a 1T-1F memory configuration for the first memory because such a memory configuration is shown by Gong et al. to be a suitable memory configuration.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al., US 2019/0212919 in view of Mathuriya et al., US 2023/0251828 and Gong et al., US 2022/0189546 as applied to claim 13 above, and further in view of Thareja et al., US 11,430,861.
Ryan et al., Mathuriya et al., and Gong et al. are applied as above but do not expressly disclose wherein the second memory has a 1T-1C configuration. Thareja et al. discloses a paraelectric memory capacitor whereby the memory is in a 1T-1C configuration (see, for example, fig. 6 and col. 1-lines 53-55 and col. 7-lines 38-52). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Ryan et al. modified by Mathuriya et al. and Gong et al. so as to construct the second memory of a 1T-1C configuration because Thareja et al. shows this to be a suitable memory configuration.
Allowable Subject Matter
Claims 8, 10, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, fails to anticipate or render obvious, the limitations of, in combination with the other claimed elements: a first word line and a second word line disposed on an upper surface and a lower surface of the channel layer, respectively, as required by dependent claim 8. Furthermore, the prior art also fails to disclose: wherein the channel layer includes a double channel layer, and the word line is embedded in the double channel layer, as required by dependent claims 10 and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
March 3, 2026
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