DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11 March 2026 has been entered.
Response to Arguments
Applicant’s arguments, see Remarks, filed on 16 February 2026, with respect to claims 6 and 8 have been fully considered and are persuasive. The 35 U.S.C. § 112 (b) rejections of claims 6 and 8 have been withdrawn.
Applicant’s arguments, see Remarks, filed on 16 February 2026, with respect to the rejection of claims 1-13 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Yu (US 2010/0148221 A1) and Cheng (US 2022/0302144 A1).
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 9-10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1) in view of Yu (US 2010/0148221 A1) and Cheng (US 2022/0302144 A1).
Regarding claim 1, Peng teaches a semiconductor device (Figs. 1A-1D), comprising:
an integrated circuit (100a) that is supported by substrates (300, see method Figs. 2A-25C, wherein 300 supports structural components of 100a during stages of the method steps; this is analogous to the definition of substrates in ¶ [0057] of the instant application), wherein the integrated circuit includes an electronic components layer (104 & 145 & 130 & 140 & 160 & 176, 150a & 150b & 185a & 185b & 155 & 172 & 174 & 158), wherein the electronic components layer includes a plurality of active component structures (¶ [0020]: a transistor, analogous to the definition of an active component in ¶ [0055] of the instant application; the transistor comprising of gate structures 130 & 104, source/drains 150a & 150b, and dielectric layers 160 & 158 );
a power rail (115) positioned on a back side (bottom side of Figs. 1B-1D) of the electronic components layer;
a buried oxide layer (114; ¶ [0022]: made of silicon oxide) positioned between the electronic components layer and the power rail (see Figs. 1C and 1D), wherein a top surface (top surface of 114) of the buried oxide layer is in direct contact with multiple structures (114 in direct contact with 130 & 160 & 158 & 185b) of the plurality of active component structures of the electronic component layer and a bottom surface (bottom surface of 114) of the buried oxide layer is in direct contact with the power rail (see Figs. 1C and 1D); and
a back side metal contact (185a-2, see Fig. 1D) buried in the buried oxide layer, wherein the back side metal contact bridges one of the active components (150a) in the electronic components layer to the power rail (see Fig. 1D).
Peng further teaches the integrated circuit to be comprised of transistors (¶ [0020], ¶ [0134]). However, Peng does not teach the transistor to be part of a logic device and does not teach the semiconductor device to further be comprised of a passive device located on the substrate, wherein the substrate located beneath the passive device includes a first well and a second well, wherein the first well is located on top of the second well, wherein the first well and the second well are different types of wells.
Yu, in the same field of invention, teaches a semiconductor device (Fig. 13) having a transistor (reset and select transistors) to be part of a logic device (¶ [0036], [0178]: these are logic gates used to reset and/or select switching ) and;
a passive device (Fig. 13 shows nanowire; ¶ [0119]: this nanowire is a capacitor; a capacitor is a passive device) located on the substrate, wherein the substrate (P-substrate) located beneath the passive device includes a first well (P+ well) and a second well (N- well), wherein the first well is located on top of the second well (Fig. 13 shows the P+ well on top of the N- well), wherein the first well and the second well are different types of wells (see table above ¶ [0030] which shows different dopants to form these wells ) .
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yu into the device of Peng to make the transistor to be part of a logic device and to further add a passive device to the semiconductor device, such that the substrate located beneath the passive device includes a first well and a second well, with the first well located below the second well and with both wells having different doping types. The ordinary artisan would have been motivated to modify Peng in the manner set forth above for at least the purpose of designing a pixel structure (see Yu’s Title and Abstract) of a light-detecting device (¶ [0002] ) that requires a photodiode (the wells on the substrate is a photodiode) for the further purpose of improving the device density (¶ [0010] ).
However, Peng in view of Yu does not teach: the passive device includes an interlayer dielectric layer, wherein the interlayer dielectric layer extends from the passive device to the logic device.
Cheng, in the same field of invention, teaches a device (1800, see Fig. 18) comprising of a passive device (¶ [0026]: Device Region 1 is a capacitor) having an interlayer dielectric layer (133, see Fig. 9), wherein the interlayer dielectric layer extends from the passive device to the logic device (¶ [0026]: Device Region 2 is a transistor; Figs. 9 & 13 show 133 in both Device Regions 1 & 2).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the device of Peng in view of Yu to add an interlayer dielectric layer that extends from the passive device to the logic device. The ordinary artisan would have been motivated to modify Peng in view of Yu in the manner set forth above for at least the purpose of electrically insulating the components, i.e., channels (1822), source region (1827), drain region (1825), gate region (1823), electrodes (1835, 1815, 1813, 1811) of the passive device and logic device from each other, thereby preventing short circuits of these components (Cheng ¶ [0054]: interlayer dielectric layer is made of dielectric materials).
Regarding claim 2, the semiconductor device of claim 1, further comprising a plurality of nanosheet stacks (104, see Peng ¶ [0020]) of semiconductor channels in the electronic components layer.
Regarding claim 3, the semiconductor device of claim 1, wherein the plurality of active components includes one or more transistor structures (Peng ¶ [0020]).
Regarding claim 4, the semiconductor device of claim 1, further comprising a back side interconnect layer (210, see Peng Fig. 1D and ¶ [0047]) coupled to a back side (bottom side of 115) of the power rail.
Regarding claim 5, the semiconductor device of claim 1, further comprising a back end of line layer (192&195, see Peng Figs. 1D and 25A-25C and ¶ [0077]; 192 & 195 are a back end of line layer since these structures are formed after the electronic components layer are formed) coupled to a front side (top side of 104 & 145 & 130 & 140 & 160 & 176, 150a & 150b & 185a & 185b & 155 & 172 & 174 & 158; see Peng Figs. 1A-1D) of the electronic components layer.
Regarding claim 6, Peng et al. teach the semiconductor device of claim 5, but does not teach the device wherein the passive device is connected to the back end of line layer.
Cheng further teaches the passive device (Device Region 1, see Fig. 18) connected to a back end of line layer (135 & 137).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the further teachings of Cheng into the device of Peng et al. to connect the passive device to a back end of line layer. The ordinary artisan would have been motivated to modify Peng et al. in the manner set forth above for at least the purpose of using the back end of line layer to connect the passive device to the logic device (as shown in Cheng Fig. 18, both Device Regions 1 and 2 are connected through 185-3; see also ¶ [0090] ).
Regarding claim 7 Peng teaches a semiconductor device (Figs. 1A-1D, 45A-45B), comprising:
a transistor (TS1 or TS2; see ¶ [0020] and ¶ [0134]; transistors are made of elements such as 150a & 150b & 130 & 104 & 160 & 158) supported by a substrate (300, see method Figs. 2A-25C, wherein 300 supports structural components of 100a during stages of the method steps; this is analogous to the definition of substrates in ¶ [0057] of the instant application), including:
a source and drain region (150a & 150b);
a gate region (130); and
one or more semiconductor channels (104) connected between the source and drain region (see Figs. 1A-1D and 45B);
a buried oxide layer (114; ¶ 0022: made of silicon oxide) positioned on a back side (bottom side of gate 130, channel 104, and source/drain 150a & 150b) of the transistor, wherein a top surface (top surface of 114) of the buried oxide layer is in direct contact with multiple elements (130 & 104, see also Fig. 17B and ¶ 0069; also in direct contact with 160 & 158) of the transistor;
a buried metal contact (185a-2, see Fig. 1D) positioned in the buried oxide layer, wherein the buried metal contact is in electrical contact with the source and drain region of the transistor (Fig. 1D shows 185a-2 in contact with 150a); and
a power rail (115) positioned on a back side (bottom side of 114) of the buried oxide layer and in electrical contact with the buried metal contact (¶ 0048), wherein a bottom surface of the buried oxide layer (bottom surface of 114) is in direct contact with the power rail.
However, Peng does not teach the semiconductor device to further be comprised of a passive device located on the substrate, wherein the substrate located beneath the passive device includes a first well and a second well, wherein the first well is located on top of the second well, wherein the first well and the second well are different types of wells.
Yu, in the same field of invention, teaches a semiconductor device (Fig. 13) comprising:
a passive device (Fig. 13 shows nanowire; ¶ [0119]: this nanowire is a capacitor) located on the substrate, wherein the substrate located beneath the passive device includes a first well (P+ well) and a second well (N- well), wherein the first well is located on top of the second well (Fig. 13 shows the P+ well on top of the N- well), wherein the first well and the second well are different types of wells (see table above ¶ [0030] which shows different dopants to form these wells ) .
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yu into the device of Peng to add a passive device to the semiconductor device, such that the substrate located beneath the passive device includes a first well and a second well, with the first well located below the second well and with both wells having different doping types. The ordinary artisan would have been motivated to modify Peng in the manner set forth above for at least the purpose of designing a pixel structure (see Yu’s Title) of a light-detecting device (¶ [0002] ) that requires a photodiode (the wells in the substrate is a photodiode) for the further purpose of improving the device density (¶ [0010] ).
However, Peng in view of Yu does not teach: the passive device includes an interlayer dielectric layer, wherein the interlayer dielectric layer extends from the passive device to the transistor.
Cheng, in the same field of invention, teaches a device (1800, see Fig. 18) comprising of a passive device (¶ [0026]: Device Region 1 is a capacitor) having an interlayer dielectric layer (133, see Fig. 9), wherein the interlayer dielectric layer extends from the passive device to the transistor (¶ [0026]: Device Region 2 is a transistor; Figs. 9 & 13 show 133 in both Device Regions 1 & 2).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the device of Peng in view of Yu to add an interlayer dielectric layer that extends from the passive device to the transistor. The ordinary artisan would have been motivated to modify Peng in view of Yu in the manner set forth above for at least the purpose of electrically insulating the components, i.e., channels (1822), source region (1827), drain region (1825), gate region (1823), electrodes (1835, 1815, 1813, 1811) of the passive device and transistor from each other, thereby preventing short circuits of these components (Cheng ¶ [0054]: interlayer dielectric layer is made of dielectric materials) .
Regarding claim 9, the semiconductor device of claim 7, further comprising a back end of line layer (192&195, see Peng Figs. 1D and 25A-25C and ¶ [0077]; 192 & 195 are a back end of line layer since these structures are formed after the electronic components layer are formed) coupled to a front side (top side) of the transistor.
Regarding claim 10, the semiconductor device of claim 7, further comprising a back side interconnect layer (210; see Peng Fig. 1D and ¶ [0047]) coupled to a back side (bottom side of 115) of the power rail.
Regarding claim 12, the semiconductor device of claim 7, further comprising a plurality of stacked nanosheet semiconductor channels (104, see Peng ¶ [0020]) in the transistor.
Regarding claim 13, the semiconductor device of claim 7, further comprising a gate all around structure in the transistor (Peng ¶ [0020]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1) in view of Yu (US 2010/0148221 A1) as applied to claim 7 above, and further in view of Yamamoto (US 2013/0187230 A1) .
Regarding claim 11, Peng in view of Chang teaches the semiconductor device of claim 7. However, Peng in view of Chang does not teach: wherein a thickness of the buried oxide layer is between 30 nm to 60 nm.
Yamamoto, in the same field of invention, teaches a semiconductor device (Fig. 5) wherein a thickness of the buried oxide layer (2) is between 30 nm to 60 nm (¶ [0051]: Box film 2 is about 10 to 50 nm).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamamoto into the device of Peng in view of Chang to provide the buried oxide layer with a thickness of between 30 nm to 60 nm. The ordinary artisan would have been motivated to modify Peng in view of Chang in the manner set forth above for at least the purpose of routinely optimizing (Yamamoto ¶ [0051]) a thickness of the buried oxide layer relative to a thickness of a silicon layer (3) in a transistor design (abstract) in order to create a halo region (11) that reduces the short channel effect (Yamamoto ¶ [0049], ¶ [0068]), thereby improving the performance of the transistor (¶ [0007]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chen (US 2022/0278093 A1) and Cheng ‘046 (US 2018/0083046 A1) both teaches passive devices (nanowire capacitors) and transistors on the same substrate.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights