Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1 - 17) in the reply filed on 3/31/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 9, 12 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 6841466), in view of Dorgan (US 20190304894).
Regarding claim 1, Yu discloses a method comprising:
forming a plurality of openings (26, Fig. 7) extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass (glass substrate 23), and wherein each of the openings comprises a sidewall;
forming a first layer (layer 27) at least on the sidewall of the openings;
forming a second layer (layer 28) on the first layer; and
depositing metal (copper 29) on the second layer to at least partially fill the openings.
Yu does not explicitly disclose the second layer comprises titanium.
Dorgan teaches the second layer (225, Fig. 2C) comprises titanium (paragraph 45).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common material such as Titanium in order to form the lining of a through hole via to conduct signal and power between layers of the circuit board.
Regarding claim 2, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests depositing the metal comprises plating copper on the second layer.
Regarding claim 3, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 2.
Yu does not explicitly disclose plating copper comprises electrolessly plating copper.
Yu suggests using a plating technology for the copper (title).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common method such as electroless plating copper, in order to form a layer on a circuit substrate.
Regarding claim 4, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Dorgan further suggests the substrate comprises borosilicate glass (borophosphosilicate glass, see Yu’s claim 2).
Regarding claim 5, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests the openings are through holes extending from the first surface to the second surface (a through hole 26 through the substrate 23, Fig. 7).
Regarding claim 6, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests the openings are vias (the opening 26 is a via hole; column 5, line 26).
Regarding claim 7, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests depositing the metal (29) substantially fills the openings respectively (Fig. 7).
Regarding claim 8, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests the first layer comprises a planarization layer (layer 24, Fig. 6), wherein the planarization layer is further formed on at least one of the first surface and the second surface, and wherein the method further comprises removing the planarization layer from the respective one of the first surface and the second surface (remove layer 24, Fig. 7; column 7, lines 35 - 41).
Regarding claim 9, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests the method further comprises removing the planarization layer (remove layer 24 from the top surface of the substrate 23; Figures 6 & 7) from the respective one of the first surface and the second surface before forming the second layer.
Regarding claim 12, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1. Yu further suggests the openings are formed using a laser assisted etching process (paragraph 107).
Regarding claim 13, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1.
Yu does not explicitly disclose the first layer is formed from hydrogen silsesquioxane.
Yu suggests using HSQ (column 5, line 2) as one of the dielectric material. Since layer 28 is modified by Dorgan teaching into an Titanium layer, layer 27 maybe a dielectric layer made of HSQ (hydrogen silsesquiloxane).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common material such as HSQ to for a dielectric layer in order to prevent short circuit between electronic components.
Regarding claim 14, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1.
Yu does not explicitly disclose forming the first layer comprises a thermal annealing process.
Yu suggests using annealing process (column 5, line 5) for the dielectric layer.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common method such as annealing to for a dielectric layer in order to prevent short circuit between electronic components on the circuit board.
Regarding claim 15, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 1.
Yu does not explicitly disclose the thermal annealing process comprises a temperature at or above a glass transition temperature of the material of the first layer.
Yu suggests using annealing process (column 5, line 5) for the dielectric layer. It is obviously that in order for this process to work, the temperature has to be at or above the glass transition temperature.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common method such as annealing to for a dielectric layer in order to prevent short circuit between electronic components on the circuit board.
Regarding claim 16, Yu discloses a means for manufacturing, comprising:
a means for forming a plurality of openings (openings 26, Fig. 7) extending from a first surface (top surface) of a substrate towards a second surface (bottom surface) of the substrate (23), wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass (glass substrate 23), and wherein each of the openings comprises a sidewall (sidewall of 26);
a means for forming a first layer (27) at least on the sidewall of the openings;
a means for forming a second layer (28) on the first layer; and
a means for depositing a metal (copper 29) on the second layer to at least partially fill the openings.
Yu does not explicitly disclose the second layer comprises titanium.
Dorgan teaches the second layer (225, Fig. 2C) comprises titanium (paragraph 45).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common material such as Titanium in order to form the lining of a through hole via to conduct signal and power between layers of the circuit board.
Regarding claim 17, Yu, in view of Dorgan, discloses the claimed invention as set forth in claim 16. Yu further suggests the first layer is further formed on at least one of the first surface and the second surface (Fig. 6), and the means further comprises means for removing the first layer from the respective one of the first surface and the second surface (remove layer 24 and a portion of layer 27 and 28).
Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 6841466), in view of Dorgan (US 20190304894), in further view Sugiyama (US 20180213642).
Regarding claim 10, Yu discloses the claimed invention as set forth in claim 1.
Yu does not explicitly disclose the substrate further comprises a solder resist layer, wherein the surface of the solder resist layer forms at least one of the surfaces of the first surface and the second surface.
Sugiyama teaches the substrate further comprises a solder resist layer (solder resist layer 14, 24, 34), wherein the surface of the solder resist layer forms at least one of the surfaces of the first surface and the second surface (top or bottom of the substrate).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include the solder resist layer in order to prevent solder from shortening the circuit components on the surface of the circuit board.
Regarding claim 11, Yu discloses the claimed invention as set forth in claim 1.
Yu does not explicitly disclose the openings have a length of at least 50 μm and a width of at least 50 μm, respectively.
Sugiyama suggests the thickness of layer 311, Fig. 6, paragraph 137, is greater than 60 μm. The opening in Fig. 6 is around this value.
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size of the openings and the component in order the fit all components into the limited space of the circuit substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US 20200044095) discloses a substrate having via hole with a titanium layer.
Furuya (US 8222142) discloses a substrate having a via hole and a titanium layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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