Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The requirement for Election/Restriction dated April 21, 2025 was withdrawn in the Office Action dated July 16, 2025. Claims 1-19 are examined.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. EP21211895.4, filed on December 2, 2021.
Drawings
The drawings were received on October 16, 2025. These drawings are acceptable.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed October 16, 2025. Claims 1, 8, and 17 are amended. The Examiner notes that claims 1-19 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1).
With respect to claim 1, Nikitin teaches in Figs. 9A-9D:
A method of packaging a semiconductor die (chip 706), the method comprising the steps of:
providing a semiconductor die (706) onto a substrate (carrier 702),
wherein the substrate comprises a carrier layer (702) that comprises a release tape (para. 88 “carrier 702 is not a copper sheet element but a tape or foil that later is removed from semiconductor device 700”),
wherein the semiconductor die (706) has a bottom side that is placed on the release tape (702, se Fig. 9A),
so that placement of the semiconductor die (706) forms a first raised surface (top surface of 706) and a second surface (top surface of 702 not covered by die);
applying an insulating layer (insulating layer 708) on both the semiconductor die (706) and the release tape (702);
forming openings (openings 10a and 10b, “The openings 10a, 10b, 10c, 10d may be produced in various known ways, e.g. by laser irradiation, by etching the insulating layer 8 selectively to a mask, etc.”) in the photoresist layer (708) to expose the semiconductor die (706) above the first surface (top of 706) and to partially expose, adjacent to the semiconductor die, the release tape (702) above the second surface (top of 702);
forming a metallization layer (first metal layer 714) so that the metallization layer contacts the exposed semiconductor die above the first surface and the partially exposed thermal release tape adjacent to the semiconductor die (see Fig. 9A, metal layer 714 contacts through both 10a and 10b);
encapsulating the semiconductor die (706) and the release tape (702) with an insulating layer (moulding material 724);
removing the release tape (702) to reveal the metallization layer (714) adjacent to the semiconductor die (para. 91 “FIG. 9C illustrates the process of removing the carrier 702 from semiconductor device”),
and the bottom side of the semiconductor die (See Fig. 9C-9D, 702 is removed from bottom side of 706);
and metallization of the bottom side of the semiconductor die (706) to form the packaged semiconductor die (external contact element 20b is formed on the bottom side of die 706) para. 91 “Afterwards, external contact elements 20a, 20b may be applied to the exposed first metal layer 714 and second metal layer elements.”)
wherein the packaged semiconductor die is formed without epoxy or epoxy solder (the embodiment of Fig. 9A-9D that includes galvanically grown surface layer elements rather than solder balls contains no epoxy solder. Nikitin teaches that the embodiment of Figs. 9A-9D is the same as that of Figs. 8A-8D except that a carrier is replaced by a tape or foil. The solder and glue used in the embodiment of Fig. 8A-8D is used to attach the chip to the carrier, which is not present in Fig. 9A-9D.)
The Examiner notes that although Nikitin does not recite a metallization of the bottom side of the semiconductor die outside of the application of contact element 20b, it would be obvious to one of ordinary skill in the art to apply the method of depositing a conducting layer taught in Fig. 5A-5E of Nikitin to apply contact element 20b, in which case the metallization of the bottom side refers to the formation of first metal layer 314. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the embodiment of Fig. 5A-5E into the embodiment of Fig. 9A-9D of Nikitin to apply the external contacts with two layers. The ordinary artisan would have been motivated to modify Nikitin in the manner set forth above for the purpose of controlling the horizontal grown to the metal layer (para. 64 of Nikitin).
The Examiner notes that the insulating layer 708 is not referred to as a “photoresist” layer in Nikitin. Nikitin teaches that insulating layer 8 which is the equivalent to insulating layer 708 may be “a layer made of an anorganic material, e.g., silicon oxide, silicon nitride, amorphous Si--O--H carbon, of ceramic compounds like silicone carbide, or of aluminum nitride. Alternatively, insulating layer may be made of an organic material, e.g., polymer like polyimide, epoxy resin, acrylate, Parylene, BCB.”
Nikitin fails to teach:
Exposing the photoresist layer to UV light to form openings in the photoresist layer to expose the semiconductor die above the first surface and to partially expose, adjacent to the semiconductor die, the release tape above the second surface;
that the carrier is made up of both a substrate and thermal release tape, or whether the tape is a thermal release tape.
Huang teaches in para. 20:
“The polyimide layer 120 undergoes a property change when being exposed to radiation energy, such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light. This property change can be used to selectively remove exposed portions or alternatively unexposed portions of the polyimide layer by a developing process. This procedure to form a patterned material layer is also referred to as lithography process.”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Nikitin with the teachings of Huang such that the polyimide used in the insulating layer is configured to act as a positive photoresist. The claim would have been obvious because the technique of using polyimide that is a positive photoresist that can be etched by UV lithography to pattern an insulating layer is known in the art, in view of the teaching of the technique for improvement as taught by Huang. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Amrine teaches in Fig. 7 a method of manufacturing an encapsulated die that uses a sacrificial carrier substrate (carrier substrate 30) and thermal release tape (thermal release tape 36).
Nikitin/Huang modified by Amrine to replace the tape 702 of Nikita with the carrier substrate 30 and thermal release tape 36 of Amrine teaches:
wherein the substrate (carrier substrate 30 and thermal release tape 36) comprises a carrier layer (30) with a thermal release tape (36) situated thereon,
removing the substrate (30) along with the thermal release tape (36) (para. 37 “Referring to FIG. 13, the polymeric tape 42 and the thermal release tape 36 are then peeled from the encapsulated structure 58.”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the carrier substrate and thermal release tape of Amrine for the tape of Nikitin/Huang because they are known equivalents and it would have yielded the predictable result of providing a removable structure to create a buildup package on. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 3, Nikitin further teaches in the embodiment of Figs. 3A-3F:
forming an initial metallization layer by seed layer deposition (para. 36 “first metal layer 114 and second metal layer 118 are produced by producing consecutively a first seed layer structure 112 (first structure) and a second seed layer structure 116 (second structure) by a laser beam 103”) and forming a further metallization layer by electroplating (para. 41 “electrochemically growing first metal layer 114.”)
Nikitin does not teach that a seed layer is used in the embodiment of Fig. 9 relied upon in the rejection of claim 1 above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Nikitin into the device of Nikitin/Huang/Amrine to make the metallization layer with a process involving a seed layer. The ordinary artisan would have been motivated to modify Nikitin/Huang/Amrine in the manner set forth above for the purpose of creating a structure to perform electroplating on.
With respect to claim 4, Nikitin further teaches:
wherein the metallization of the bottom side of the semiconductor die (deposition of 20b) is performed by electroplating (para. 91 “The external contact elements may be solder balls, galvanically grown surface layer elements”)
With respect to claim 5, Nikitin teaches in the plan view shown in Fig. 1:
wherein the first surface of the semiconductor die (top surface of 6, which is equivalent to 706 in the embodiment of Fig. 9A-9D relied upon above) comprises two separate regions (see annotated Fig. 1B below),
wherein the step of formation of openings forms separate openings (10d and 10b) corresponding to each of the two separate regions above the semiconductor die (10d and 10b in separate regions above the semiconductor die) and adjacent to the semiconductor die (10a and 10c are formed adjacent to the semiconductor die),
and wherein during the step of forming a metallization layer,
two separate metallization layers are formed (metal layers 14 and 18), wherein each of the two separate metallization layers contacts corresponding openings above the semiconductor die and adjacent to the semiconductor die (14 contacts 10b and 10a, 18 contacts 10c and 10d).
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With respect to claim 6, Nikitin further teaches in para. 1B:
wherein the photoresist layer is applied by spray coating. (insulating layer 8 may be deposited out of a gas phase via sputtering, spray coating)
With respect to claim 7, Nikitin further teaches in para. 87:
further comprising the step of cutting the packaged semiconductor die to form individual packaged semiconductor components. (para. 87 of Nikitin, “the array of chips is singulated to obtain multiple single devices”)
With respect to claim 13, Nikitin further teaches:
wherein the seed layer deposition is implemented by laser induced metallization (para. 70, “First seed layer structure 412 is produced by a laser beam”).
With respect to claim 15, Nikitin further teaches:
wherein the method forms a packaged semiconductor die with three terminals. (para. 86, “For example, if chip 606 is a vertical power transistor with a source and gate contact on the front side of chip 602 and a drain contact on the backside of chip 602, external connection pad 20a may connect the outside world to the source contact via first metal layer element 614 while external connection pad 20b may connect the outside world to the drain contact via the backside of chip 602. Further external connection pads may be involved, at least one of them to connect the outside world to the gate contact on the chip front side.” The Examiner notes that while para. 86 refers to Fig. 8, para. 88 notes that the embodiments of Figs. 8A-8D share this feature with the embodiment of Figs. 9A-9D as relied upon above.)
Claims 2 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1) as applied to independent claim 1 above and further in view of Shirai (Polymer International, 2016).
With respect to claim 2, Nikitin/Huang/Amrine teaches all limitations of claim 1 upon which claim 2 depends. Nikitin/Huang/Amrine fails to teach:
providing a further photoresist layer on the metallized bottom side and the revealed metallization layer adjacent to the semiconductor die.
Shirai teaches a method of depositing conducting material that involved the use of the UV-curable positive photoresist
Nikitin/Huang/Amrine modified by Shirai to us a photoresist to pattern the metal plating to the desired shape teaches:
providing a further photoresist layer (UV-curable positive photoresist shown in Fig. 4 of Shirai) on the metallized bottom side (first metal layer on bottom side of 706, as described in rejection of claim 1 above) and the revealed metallization layer adjacent to the semiconductor die (bottom side of 704 revealed at 10a).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of using a UV-curable positive photoresist to pattern metal plating of Shirai for the method of depositing backside metal contacts of Nikitin/Huang/Amrine because they are known equivalents and it would have yielded the predictable result of providing patterned metal contacts on the backside of the semiconductor device. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 8, Shirai further teaches:
further comprising the steps of:
exposing the semiconductor die covered with photoresist to ultraviolet (UV) light to form window pads (see Fig. 4 of Shirai, UV light forms windows in the positive photoresist where pads can be deposited);
and electroplating a further metallic layer to the metallized bottom side and the revealed metallization layer adjacent to the semiconductor die (forming 20a and 20b, para. 91 “The external contact elements may be solder balls, galvanically grown surface layer elements.“ Using the modification made with respect to claim 1 to use the method of Fig. 5 in which multiple conductive layers are deposited, the electroplating refers to the deposition of second metal layer 318 )
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Nikitin in view of Huang, Amrine, and Shirai as explained above.
With respect to claim 9, Nikitin further teaches in the embodiment of Figs. 3A-3F:
forming an initial metallization layer by seed layer deposition (para. 36 “first metal layer 114 and second metal layer 118 are produced by producing consecutively a first seed layer structure 112 (first structure) and a second seed layer structure 116 (second structure) by a laser beam 103”) and forming a further metallization layer by electroplating (para. 41 “electrochemically growing first metal layer 114.”)
Nikitin does not teach that a seed layer is used in the embodiment of Fig. 9 relied upon in the rejection of claim 1 above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Nikitin into the device of Nikitin/Huang/Amrine to make the metallization layer with a process involving a seed layer. The ordinary artisan would have been motivated to modify Nikitin/Huang/Amrine in the manner set forth above for the purpose of creating a structure to perform electroplating on.
With respect to claim 10, Nikitin further teaches:
wherein the metallization of the bottom side (metallization of bottom side of 706 as described in modification of the embodiment of Fig. 9 of Nikitin with Fig. 5 of Nikitin to form a first metal layer 314) of the semiconductor die is performed by electroplating (electrochemically grown first metal layer 314).
With respect to claim 11, Nikitin further teaches in para. 1B:
wherein the photoresist layer is applied by spray coating. (insulating layer 8 may be deposited out of a gas phase via sputtering, spray coating)
With respect to claim 12, Nikitin further teaches in para. 87n:
further comprising the step of cutting the packaged semiconductor die to form individual packaged semiconductor components. (para. 87 of Nikitin, “the array of chips is singulated to obtain multiple single devices”)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1) as applied to claim 3 above and further in view of Rinne (US 2007/0182004 A1).
With respect to claim 14, Nikitin/Huang/Amrine teaches all limitations of claim 3 upon which claim 14 depends. Nikitin/Huang/Amrine does not teach:
wherein the seed layer deposition is implemented by shadow mask sputtering.
Rinne teaches:
wherein the seed layer deposition is implemented by shadow mask sputtering. (para. 61 “the seed layer 607 may be formed by aligning a shadow mask over the protective layer 606 so that the shadow mask exposes portions of the protective layer 606 corresponding to the RDL and bump pad. The seed layer may then be deposited on the exposed portions of the protective layer 606 and on the shadow mask, for example, using evaporation, sputtering, and/or chemical vapor deposition”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of depositing a seed layer by shadow mask sputtering taught by Rinne for the various methods listed in Nikitin because they are known equivalents and it would have yielded the predictable result of providing a seed layer on the semiconductor device. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1) and Shirai (Polymer International, 2016) as applied to claim 8 above and further in view of Agarwala (US 5,376,584).
With respect to claim 16, Nikitin/Huang/Amrine/Shirai teaches all limitations of claim 8 upon which claim 16 depends. Nikitin/Huang/Amrine/Shirai fails to teach:
wherein the step of metallization uses copper, and wherein the step of electroplating a further metallic layer uses tin.
Agarwala teaches a method of forming contacts that includes electroplating solder over a metallization layer similar to the method taught in Nikitin:
wherein the step of metallization uses copper (col 2, ln 17-19 “a blanket layer of Cr/phased Cr-Cu film is deposited”), and wherein the step of electroplating a further metallic layer uses tin (col. 2, ln 14-17 “the solder deposition is made by electroplating the Pb-Sn solder on top of the blanket BLM metalization”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Agrawala into the device of Nikitin/Huang/Amrine/Shirai to use copper in the metallization layer and tin in the electroplating layer. The ordinary artisan would have been motivated to modify Nikitin/Huang/Amrine/Shirai in the manner set forth above for the purpose of creating a connection pad and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Lin (WO 2014/070764 A1).
With respect to claim 17, Nikitin teaches:
A packaged semiconductor die (chip 706) comprising:
a top surface (top of 706),
a bottom surface (bottom of 706),
and a plurality of sides (left and right sides of 706);
an insulating layer (insulating layer 708) on the top surface, the sides and extending adjacent to the semiconductor die co-planar to the bottom surface (see Fig. 9D);
openings (openings 10a and 10b) in insulating layer (708) arranged above the top surface (10b is above the top surface) and adjacent to the semiconductor die co-planar to the bottom surface (10a is adjacent to the semiconductor die and co-planar to the bottom surface);
a stepped interconnect metallization layer (first metal layer 714) connecting the semiconductor die (708) at the opening in insulating layer (10b) and arranged above the top surface with a metallic contact (external connection pad 20a) via the opening adjacent to the semiconductor die co-planar to the bottom surface (10a);
and a further metallic contact (external connection pad 20b) on the bottom surface of the semiconductor die (706) that contacts the semiconductor die.
wherein the packaged semiconductor die is formed without epoxy or epoxy solder (the embodiment of Fig. 9A-9D that includes galvanically grown surface layer elements rather than solder balls contains no epoxy solder. Nikitin teaches that the embodiment of Figs. 9A-9D is the same as that of Figs. 8A-8D except that a carrier is replaced by a tape or foil. The solder and glue used in the embodiment of Fig. 8A-8D is used to attach the chip to the carrier, which is not present in Fig. 9A-9D.)
The Examiner notes that the insulating layer 708 is not referred to as a “photoresist” layer in Nikitin. Nikitin teaches that insulating layer 8 which is the equivalent to insulating layer 708 may be “a layer made of an anorganic material, e.g., silicon oxide, silicon nitride, amorphous Si--O--H carbon, of ceramic compounds like silicone carbide, or of aluminum nitride. Alternatively, insulating layer may be made of an organic material, e.g., polymer like polyimide, epoxy resin, acrylate, Parylene, BCB.”
Lin teaches on page 13, lns. 8-10:
“Some examples of liquid photo-patternable polymers that may be used include epoxy-based liquid polymers, polyimide-based liquid polymers and benzocyclobutene (BCB) based liquid polymers”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Nikitin with the teachings of Lin such that the polyimide or BCB used in the insulating layer is configured to act as a photoresist in order to pattern the insulating layer. The claim would have been obvious because the technique of using polyimide-based liquid polymers or benzocyclobutene (BCB) based liquid polymers as an insulating photoresist was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 19, Nikiti/Lin further teaches:
wherein the packaged semiconductor die is a Multiple Input Multiple Output (MIMO) device. (para. 17 “embodiments may include semiconductor chips that have power transistors for switching high electronic currents and/or high voltages. For example, chip 6 (equivalent to die 706 of the cited embodiment) may include one or several Insulated Gate Bipolar Transistors (IGBT) that each have a source on one face of the chip and a drain on the opposite face of the chip.”, a chip that includes several IGBT will have multiple inputs and multiple outputs and therefore qualifies as a MIMO device)
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nikiti (US 2009/0191665 A1) in view of Lin (WO 2014/070764 A1) as applied to claim 17 above and further in view of Wilson (ElectronicDesign.com, 2014).
With respect to claim 18, Nikitin/Lin teaches:
wherein the packaged semiconductor die is an insulated gate bipolar transistor (IGBT) device (para. 6).
Wilson teaches that IGBTs and MOSFETS are used in similar applications, and that “at lower switching frequencies, the MOSFET has the lower overall loss and lower operating junction temperature.”
Therefore, it would be obvious to modify the package of Nikitin/Lin with the teaching of Wilson to use a die that comprises a MOSFET such that Nikitin/Lin/Wilson teaches:
wherein the packaged semiconductor die is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.
Response to Arguments
Applicant's arguments filed October 16, 2025 have been fully considered but they are not persuasive.
With respect to the argument on page 12 that Nikitin does not teach packaging without epoxy or epoxy solder, the Examiner notes that Nikitin teaches multiple embodiments with different configurations. Applicant quotes paragraphs [0018], [0068], and [0084] as evidence, however each of those paragraphs refer to embodiments in which the chip is soldered to carrier 602. The embodiment relied upon in this Action is the embodiment of Fig. 9A-9D in which the carrier is replaced by a removable tape or foil that does not require soldering. The only solder mentioned in the discussion of Fig. 9A-9C are external contact elements that may be solder balls. However, these solder balls are one of several alternatives which also includes “galvanically grown surface layer elements.”
The steps of the method used to manufacture the embodiment of Fig. 9A-9D of Nikitin are substantially the same as the steps of the instant invention as claimed that eliminate the need for epoxy or epoxy solder, therefore the Examiner determines that Nikitin teaches the limitation and the argument is therefore unpersuasive.
Applicant’s arguments with respect to claims 1-16 regarding the arguments related to the photoresist on pages 14 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claims 17-19 regarding the argument on pages 14 and 15 that the ordinary artisan would not be motivated to use a photoresist as taught by Lin as the insulating layer in Nikitin, the Applicant cites page 13 of Lin, which states “and a developer is used 633 to remove undesired portions of the polymer that were not exposed through the mask, thereby producing the protrusions” however prior to using the developer, Lin teaches that “an ultra-violet light exposure system is used 632 to expose the photo-patternable polymer.” Lin therefore teaches that the benefit of a photo-patternable polymer such as polyimide is to create protrusions of a desired shape through the use of a negative photoresist. The ordinary artisan would understand that this process can be used to make the insulating layers of Nikitin which may be formed from polyimide through “traditional ways” (para. 19). The Examiner considers Lin to teach a “traditional way” of applying polyimide. The argument is therefore not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897