Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 12, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed April 1, 2026 and entered with the request for continued examination filed May 12, 2026. Claim 11 is amended. Claim 20 is newly added. The Examiner notes that claims 1-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1).
With respect to claim 1, Nikitin teaches in Figs. 9A-9D:
A method of packaging a semiconductor die (chip 706), the method comprising the steps of:
providing a semiconductor die (706) onto a substrate (carrier 702),
wherein the substrate comprises a carrier layer (702) that comprises a release tape (para. 88 “carrier 702 is not a copper sheet element but a tape or foil that later is removed from semiconductor device 700”),
wherein the semiconductor die (706) has a bottom side that is placed on the release tape (702, se Fig. 9A),
so that placement of the semiconductor die (706) forms a first raised surface (top surface of 706) and a second surface (top surface of 702 not covered by die);
applying an insulating layer (insulating layer 708) on both the semiconductor die (706) and the release tape (702);
forming openings (openings 10a and 10b, “The openings 10a, 10b, 10c, 10d may be produced in various known ways, e.g. by laser irradiation, by etching the insulating layer 8 selectively to a mask, etc.”) in the photoresist layer (708) to expose the semiconductor die (706) above the first surface (top of 706) and to partially expose, adjacent to the semiconductor die, the release tape (702) above the second surface (top of 702);
forming a metallization layer (first metal layer 714) so that the metallization layer contacts the exposed semiconductor die above the first surface and the partially exposed thermal release tape adjacent to the semiconductor die (see Fig. 9A, metal layer 714 contacts through both 10a and 10b);
encapsulating the semiconductor die (706) and the release tape (702) with an insulating layer (moulding material 724);
removing the release tape (702) to reveal the metallization layer (714) adjacent to the semiconductor die (para. 91 “FIG. 9C illustrates the process of removing the carrier 702 from semiconductor device”),
and the bottom side of the semiconductor die (See Fig. 9C-9D, 702 is removed from bottom side of 706);
and metallization of the bottom side of the semiconductor die (706) to form the packaged semiconductor die (external contact element 20b is formed on the bottom side of die 706) para. 91 “Afterwards, external contact elements 20a, 20b may be applied to the exposed first metal layer 714 and second metal layer elements.”)
wherein the packaged semiconductor die is formed without epoxy or epoxy solder (the embodiment of Fig. 9A-9D that includes galvanically grown surface layer elements rather than solder balls contains no epoxy solder. Nikitin teaches that the embodiment of Figs. 9A-9D is the same as that of Figs. 8A-8D except that a carrier is replaced by a tape or foil. The solder and glue used in the embodiment of Fig. 8A-8D is used to attach the chip to the carrier, which is not present in Fig. 9A-9D.)
The Examiner notes that although Nikitin does not recite a metallization of the bottom side of the semiconductor die outside of the application of contact element 20b, it would be obvious to one of ordinary skill in the art to apply the method of depositing a conducting layer taught in Fig. 5A-5E of Nikitin to apply contact element 20b, in which case the metallization of the bottom side refers to the formation of first metal layer 314. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the embodiment of Fig. 5A-5E into the embodiment of Fig. 9A-9D of Nikitin to apply the external contacts with two layers. The ordinary artisan would have been motivated to modify Nikitin in the manner set forth above for the purpose of controlling the horizontal grown to the metal layer (para. 64 of Nikitin).
The Examiner notes that the insulating layer 708 is not referred to as a “photoresist” layer in Nikitin. Nikitin teaches that insulating layer 8 which is the equivalent to insulating layer 708 may be “a layer made of an anorganic material, e.g., silicon oxide, silicon nitride, amorphous Si--O--H carbon, of ceramic compounds like silicone carbide, or of aluminum nitride. Alternatively, insulating layer may be made of an organic material, e.g., polymer like polyimide, epoxy resin, acrylate, Parylene, BCB.”
Nikitin fails to teach:
Exposing the photoresist layer to UV light to form openings in the photoresist layer to expose the semiconductor die above the first surface and to partially expose, adjacent to the semiconductor die, the release tape above the second surface;
that the carrier is made up of both a substrate and thermal release tape, or whether the tape is a thermal release tape.
Huang teaches in para. 20:
“The polyimide layer 120 undergoes a property change when being exposed to radiation energy, such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light. This property change can be used to selectively remove exposed portions or alternatively unexposed portions of the polyimide layer by a developing process. This procedure to form a patterned material layer is also referred to as lithography process.”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Nikitin with the teachings of Huang such that the polyimide used in the insulating layer is configured to act as a positive photoresist. The claim would have been obvious because the technique of using polyimide that is a positive photoresist that can be etched by UV lithography to pattern an insulating layer is known in the art, in view of the teaching of the technique for improvement as taught by Huang. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
The Graham factual inquiries required to support a rejection under the basis of “Use of Known Technique To Improve Similar Devices (Methods, or Products) in the Same Way” (MPEP 2143(I)(C) are:
(1) a finding that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an “improvement;”
(2) a finding that the prior art contained a “comparable” device (method, or product that is not the same as the base device) that has been improved in the same way as the claimed invention;
(3) a finding that one of ordinary skill in the art could have applied the known “improvement” technique in the same way to the “base” device (method, or product) and the results would have been predictable to one of ordinary skill in the art; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
In this case, Nikitin teaches that openings are formed in an insulating layer 708 using “in various known ways, e.g. by laser irradiation, by etching the insulating layer 8 selectively to a mask” (the “base method” of Graham inquiry 1). The ordinary artisan would not consider the exemplary list of methods of patterning a resistive layer taught by Nikitin to be exhaustive or to exclude other methods known in the art.
Huang teaches that forming openings in an insulating layer with photolithography is a method known in the art to pattern a resistive layer and that polyimide is a common photosensitive material (“comparable method” of Graham inquiry 2). In the previous Office Action, the Examiner noted polyimide as an exemplary material listed by Nikitin to highlight that it is acceptable for the purposes of the insulative layer of Nikitin to provide evidence that the method of Huang could easily be modified by a person of ordinary skill in the art into the method of making the device of Nikitin in order to form the insulative pattern (Graham inquiry 3). The Examiner takes the position that the Graham factual inquires support the rejection and the argument is therefore found unpersuasive.
Amrine teaches in Fig. 7 a method of manufacturing an encapsulated die that uses a sacrificial carrier substrate (carrier substrate 30) and thermal release tape (thermal release tape 36).
Nikitin/Huang modified by Amrine to replace the tape 702 of Nikita with the carrier substrate 30 and thermal release tape 36 of Amrine teaches:
wherein the substrate (carrier substrate 30 and thermal release tape 36) comprises a carrier layer (30) with a thermal release tape (36) situated thereon,
removing the substrate (30) along with the thermal release tape (36) (para. 37 “Referring to FIG. 13, the polymeric tape 42 and the thermal release tape 36 are then peeled from the encapsulated structure 58.”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the carrier substrate and thermal release tape of Amrine for the tape of Nikitin/Huang because they are known equivalents and it would have yielded the predictable result of providing a removable structure to create a buildup package on. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
The Graham factual inquiries for a rejection based on “Simple Substitution of One Known Element for Another To Obtain Predictable Results” are:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Nikitin teaches that the method includes using a flexible carrier to build a semiconductor device on that is later removed which differs from the instant invention as claimed because the instant invention uses a carrier substrate including thermal release tape so that the carrier substrate may be removed. (Graham inquiry 1). Amrine teaches that the use of a carrier substrate with thermal release tape is known in the art (Graham inquiry 2). The Examiner finds that one of ordinary skill in the art could have substituted the carrier substrate with thermal release tape of Amrine for the flexible carrier of Nikitin with predictable results (Graham inquiry 3).
With respect to claim 3, Nikitin further teaches in the embodiment of Figs. 3A-3F:
forming an initial metallization layer by seed layer deposition (para. 36 “first metal layer 114 and second metal layer 118 are produced by producing consecutively a first seed layer structure 112 (first structure) and a second seed layer structure 116 (second structure) by a laser beam 103”) and forming a further metallization layer by electroplating (para. 41 “electrochemically growing first metal layer 114.”)
Nikitin does not teach that a seed layer is used in the embodiment of Fig. 9 relied upon in the rejection of claim 1 above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Nikitin into the device of Nikitin/Huang/Amrine to make the metallization layer with a process involving a seed layer. The ordinary artisan would have been motivated to modify Nikitin/Huang/Amrine in the manner set forth above for the purpose of creating a structure to perform electroplating on.
With respect to claim 4, Nikitin further teaches:
wherein the metallization of the bottom side of the semiconductor die (deposition of 20b) is performed by electroplating (para. 91 “The external contact elements may be solder balls, galvanically grown surface layer elements”)
With respect to claim 5, Nikitin teaches in the plan view shown in Fig. 1:
wherein the first surface of the semiconductor die (top surface of 6, which is equivalent to 706 in the embodiment of Fig. 9A-9D relied upon above) comprises two separate regions (see annotated Fig. 1B below),
wherein the step of formation of openings forms separate openings (10d and 10b) corresponding to each of the two separate regions above the semiconductor die (10d and 10b in separate regions above the semiconductor die) and adjacent to the semiconductor die (10a and 10c are formed adjacent to the semiconductor die),
and wherein during the step of forming a metallization layer,
two separate metallization layers are formed (metal layers 14 and 18), wherein each of the two separate metallization layers contacts corresponding openings above the semiconductor die and adjacent to the semiconductor die (14 contacts 10b and 10a, 18 contacts 10c and 10d).
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With respect to claim 6, Nikitin further teaches in para. [0019]:
wherein the photoresist layer is applied by spray coating. (insulating layer 8 may be deposited out of a gas phase via sputtering, spray coating)
With respect to claim 7, Nikitin further teaches in para. 87:
further comprising the step of cutting the packaged semiconductor die to form individual packaged semiconductor components. (para. 87 of Nikitin, “the array of chips is singulated to obtain multiple single devices”)
With respect to claim 13, Nikitin further teaches:
wherein the seed layer deposition is implemented by laser induced metallization (para. 70, “First seed layer structure 412 is produced by a laser beam”).
With respect to claim 15, Nikitin further teaches:
wherein the method forms a packaged semiconductor die with three terminals. (para. 86, “For example, if chip 606 is a vertical power transistor with a source and gate contact on the front side of chip 602 and a drain contact on the backside of chip 602, external connection pad 20a may connect the outside world to the source contact via first metal layer element 614 while external connection pad 20b may connect the outside world to the drain contact via the backside of chip 602. Further external connection pads may be involved, at least one of them to connect the outside world to the gate contact on the chip front side.” The Examiner notes that while para. 86 refers to Fig. 8, para. 88 notes that the embodiments of Figs. 8A-8D share this feature with the embodiment of Figs. 9A-9D as relied upon above.)
Claims 2 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1) as applied to independent claim 1 above and further in view of Shirai (Polymer International, 2016).
With respect to claim 2, Nikitin/Huang/Amrine teaches all limitations of claim 1 upon which claim 2 depends. Nikitin/Huang/Amrine fails to teach:
providing a further photoresist layer on the metallized bottom side and the revealed metallization layer adjacent to the semiconductor die.
Shirai teaches a method of depositing conducting material that involved the use of the UV-curable positive photoresist
Nikitin/Huang/Amrine modified by Shirai to us a photoresist to pattern the metal plating to the desired shape teaches:
providing a further photoresist layer (UV-curable positive photoresist shown in Fig. 4 of Shirai) on the metallized bottom side (first metal layer on bottom side of 706, as described in rejection of claim 1 above) and the revealed metallization layer adjacent to the semiconductor die (bottom side of 704 revealed at 10a).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of using a UV-curable positive photoresist to pattern metal plating of Shirai for the method of depositing backside metal contacts of Nikitin/Huang/Amrine because they are known equivalents and it would have yielded the predictable result of providing patterned metal contacts on the backside of the semiconductor device. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 8, Shirai further teaches:
further comprising the steps of:
exposing the semiconductor die covered with photoresist to ultraviolet (UV) light to form window pads (see Fig. 4 of Shirai, UV light forms windows in the positive photoresist where pads can be deposited);
and electroplating a further metallic layer to the metallized bottom side and the revealed metallization layer adjacent to the semiconductor die (forming 20a and 20b, para. 91 “The external contact elements may be solder balls, galvanically grown surface layer elements.“ Using the modification made with respect to claim 1 to use the method of Fig. 5 in which multiple conductive layers are deposited, the electroplating refers to the deposition of second metal layer 318 )
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Nikitin in view of Huang, Amrine, and Shirai as explained above.
With respect to claim 9, Nikitin further teaches in the embodiment of Figs. 3A-3F:
forming an initial metallization layer by seed layer deposition (para. 36 “first metal layer 114 and second metal layer 118 are produced by producing consecutively a first seed layer structure 112 (first structure) and a second seed layer structure 116 (second structure) by a laser beam 103”) and forming a further metallization layer by electroplating (para. 41 “electrochemically growing first metal layer 114.”)
Nikitin does not teach that a seed layer is used in the embodiment of Fig. 9 relied upon in the rejection of claim 1 above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Nikitin into the device of Nikitin/Huang/Amrine to make the metallization layer with a process involving a seed layer. The ordinary artisan would have been motivated to modify Nikitin/Huang/Amrine in the manner set forth above for the purpose of creating a structure to perform electroplating on.
With respect to claim 10, Nikitin further teaches:
wherein the metallization of the bottom side (metallization of bottom side of 706 as described in modification of the embodiment of Fig. 9 of Nikitin with Fig. 5 of Nikitin to form a first metal layer 314) of the semiconductor die is performed by electroplating (electrochemically grown first metal layer 314).
With respect to claim 11, Nikitin further teaches in Fig. 9D:
wherein the metallization layer (718) follows a contour of the semiconductor die (706) in a stepped manner to enable electrical contact between a top part of the semiconductor die (para [0021] “securely accessing the contact elements from above through openings 10b”) and a contact pad (connection pad 20a) that sits flush with a bottom part of the semiconductor die (706)
With respect to claim 12, Nikitin further teaches in para. 87:
further comprising the step of cutting the packaged semiconductor die to form individual packaged semiconductor components. (para. 87 of Nikitin, “the array of chips is singulated to obtain multiple single devices”)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1) as applied to claim 3 above and further in view of Rinne (US 2007/0182004 A1).
With respect to claim 14, Nikitin/Huang/Amrine teaches all limitations of claim 3 upon which claim 14 depends. Nikitin/Huang/Amrine does not teach:
wherein the seed layer deposition is implemented by shadow mask sputtering.
Rinne teaches:
wherein the seed layer deposition is implemented by shadow mask sputtering. (para. 61 “the seed layer 607 may be formed by aligning a shadow mask over the protective layer 606 so that the shadow mask exposes portions of the protective layer 606 corresponding to the RDL and bump pad. The seed layer may then be deposited on the exposed portions of the protective layer 606 and on the shadow mask, for example, using evaporation, sputtering, and/or chemical vapor deposition”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of depositing a seed layer by shadow mask sputtering taught by Rinne for the various methods listed in Nikitin because they are known equivalents and it would have yielded the predictable result of providing a seed layer on the semiconductor device. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Huang (US 2020/0105634 A1) and Amrine (US 2008/0182363 A1) and Shirai (Polymer International, 2016) as applied to claim 8 above and further in view of Agarwala (US 5,376,584).
With respect to claim 16, Nikitin/Huang/Amrine/Shirai teaches all limitations of claim 8 upon which claim 16 depends. Nikitin/Huang/Amrine/Shirai fails to teach:
wherein the step of metallization uses copper, and wherein the step of electroplating a further metallic layer uses tin.
Agarwala teaches a method of forming contacts that includes electroplating solder over a metallization layer similar to the method taught in Nikitin:
wherein the step of metallization uses copper (col 2, ln 17-19 “a blanket layer of Cr/phased Cr-Cu film is deposited”), and wherein the step of electroplating a further metallic layer uses tin (col. 2, ln 14-17 “the solder deposition is made by electroplating the Pb-Sn solder on top of the blanket BLM metalization”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Agrawala into the device of Nikitin/Huang/Amrine/Shirai to use copper in the metallization layer and tin in the electroplating layer. The ordinary artisan would have been motivated to modify Nikitin/Huang/Amrine/Shirai in the manner set forth above for the purpose of creating a connection pad and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nikitin (US 2009/0191665 A1) in view of Lin (WO 2014/070764 A1).
With respect to claim 17, Nikitin teaches:
A packaged semiconductor die (chip 706) comprising:
a top surface (top of 706),
a bottom surface (bottom of 706),
and a plurality of sides (left and right sides of 706);
an insulating layer (insulating layer 708) on the top surface, the sides and extending adjacent to the semiconductor die co-planar to the bottom surface (see Fig. 9D);
openings (openings 10a and 10b) in insulating layer (708) arranged above the top surface (10b is above the top surface) and adjacent to the semiconductor die co-planar to the bottom surface (10a is adjacent to the semiconductor die and co-planar to the bottom surface);
a stepped interconnect metallization layer (first metal layer 714) connecting the semiconductor die (708) at the opening in insulating layer (10b) and arranged above the top surface with a metallic contact (external connection pad 20a) via the opening adjacent to the semiconductor die co-planar to the bottom surface (10a);
and a further metallic contact (external connection pad 20b) on the bottom surface of the semiconductor die (706) that contacts the semiconductor die.
wherein the packaged semiconductor die is formed without epoxy or epoxy solder (the embodiment of Fig. 9A-9D that includes galvanically grown surface layer elements rather than solder balls contains no epoxy solder. Nikitin teaches that the embodiment of Figs. 9A-9D is the same as that of Figs. 8A-8D except that a carrier is replaced by a tape or foil. The solder and glue used in the embodiment of Fig. 8A-8D is used to attach the chip to the carrier, which is not present in Fig. 9A-9D.)
The Examiner notes that the insulating layer 708 is not referred to as a “photoresist” layer in Nikitin. Nikitin teaches that insulating layer 8 which is the equivalent to insulating layer 708 may be “a layer made of an anorganic material, e.g., silicon oxide, silicon nitride, amorphous Si--O--H carbon, of ceramic compounds like silicone carbide, or of aluminum nitride. Alternatively, insulating layer may be made of an organic material, e.g., polymer like polyimide, epoxy resin, acrylate, Parylene, BCB.”
Lin teaches on page 13, lns. 8-10:
“Some examples of liquid photo-patternable polymers that may be used include epoxy-based liquid polymers, polyimide-based liquid polymers and benzocyclobutene (BCB) based liquid polymers”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Nikitin with the teachings of Lin such that the polyimide or BCB used in the insulating layer is configured to act as a photoresist in order to pattern the insulating layer. The claim would have been obvious because the technique of using polyimide-based liquid polymers or benzocyclobutene (BCB) based liquid polymers as an insulating photoresist was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 19, Nikiti/Lin further teaches:
wherein the packaged semiconductor die is a Multiple Input Multiple Output (MIMO) device. (para. 17 “embodiments may include semiconductor chips that have power transistors for switching high electronic currents and/or high voltages. For example, chip 6 (equivalent to die 706 of the cited embodiment) may include one or several Insulated Gate Bipolar Transistors (IGBT) that each have a source on one face of the chip and a drain on the opposite face of the chip.”, a chip that includes several IGBT will have multiple inputs and multiple outputs and therefore qualifies as a MIMO device)
With respect to claim 20, Nikitin further teaches:
wherein the metallization layer (718) follows a contour of the semiconductor die (706) to enable electrical contact between a top part of the semiconductor die (para [0021] “securely accessing the contact elements from above through openings 10b”) and a contact pad (connection pad 20a) that sits flush with a bottom part of the semiconductor die (706)
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nikiti (US 2009/0191665 A1) in view of Lin (WO 2014/070764 A1) as applied to claim 17 above and further in view of Wilson (ElectronicDesign.com, 2014).
With respect to claim 18, Nikitin/Lin teaches:
wherein the packaged semiconductor die is an insulated gate bipolar transistor (IGBT) device (para. 6).
Wilson teaches that IGBTs and MOSFETS are used in similar applications, and that “at lower switching frequencies, the MOSFET has the lower overall loss and lower operating junction temperature.”
Therefore, it would be obvious to modify the package of Nikitin/Lin with the teaching of Wilson to use a die that comprises a MOSFET such that Nikitin/Lin/Wilson teaches:
wherein the packaged semiconductor die is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.
Response to Arguments
Applicant's arguments filed April 14, 2026 have been fully considered but they are not persuasive.
Applicant's arguments filed April 1, 2026 have been fully considered but they are not persuasive.
Applicant argues that there is no reason to combine Huang with Nikitin to teach the limitation “applying a photoresist layer on both the semiconductor die and the thermal release tape.”
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
The Graham factual inquiries required to support a rejection under the basis of “Use of Known Technique To Improve Similar Devices (Methods, or Products) in the Same Way” (MPEP 2143(I)(C) are:
(1) a finding that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an “improvement;”
(2) a finding that the prior art contained a “comparable” device (method, or product that is not the same as the base device) that has been improved in the same way as the claimed invention;
(3) a finding that one of ordinary skill in the art could have applied the known “improvement” technique in the same way to the “base” device (method, or product) and the results would have been predictable to one of ordinary skill in the art; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
In this case, Nikitin teaches that openings are formed in an insulating layer 708 using “in various known ways, e.g. by laser irradiation, by etching the insulating layer 8 selectively to a mask” (the “base method” of Graham inquiry 1). The ordinary artisan would not consider the exemplary list of methods of patterning a resistive layer taught by Nikitin to be exhaustive or to exclude other methods known in the art.
Huang teaches that forming openings in an insulating layer with photolithography is a method known in the art to pattern a resistive layer and that polyimide is a common photosensitive material (“comparable method” of Graham inquiry 2). In the previous Office Action, the Examiner noted polyimide as an exemplary material listed by Nikitin to highlight that it is acceptable for the purposes of the insulative layer of Nikitin to provide evidence that the method of Huang could easily be modified by a person of ordinary skill in the art into the method of making the device of Nikitin in order to form the insulative pattern (Graham inquiry 3). The Examiner takes the position that the Graham factual inquires support the rejection and the argument is therefore found unpersuasive.
Applicant further argues that Nikitin teaches away from using a photoresist to pattern the insulative layer because Nikitin recites the use of a photoresist as mask 350 in Fig. 5B. The Examiner respectfully disagrees. The teaching of using photoresist for one purpose does not preclude the use of a photoresist for a different purpose. Further, the use of photoresist by Nikitin cited by the Applicant directs to an embodiment of Nikitin different from the embodiment relied upon as the base method in the rejection.
Applicant further argues that there is not a reason to combine the thermal release tape taught by Amrine into the method of Nikitin. The Graham factual inquiries for a rejection based on “Simple Substitution of One Known Element for Another To Obtain Predictable Results” are:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Nikitin teaches that the method includes using a flexible carrier to build a semiconductor device on that is later removed which differs from the instant invention as claimed because the instant invention uses a carrier substrate including thermal release tape so that the carrier substrate may be removed. (Graham inquiry 1). Amrine teaches that the use of a carrier substrate with thermal release tape is known in the art (Graham inquiry 2). The Examiner finds that one of ordinary skill in the art could have substituted the carrier substrate with thermal release tape of Amrine for the flexible carrier of Nikitin with predictable results (Graham inquiry 3). The Examiner takes the position that the Graham factual inquires support the rejection and the argument is therefore found unpersuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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