Prosecution Insights
Last updated: July 17, 2026
Application No. 18/061,188

Microelectronic Assembly Including Interconnect Bridges with Through Vias Embedded Therein

Non-Final OA §102§103§112
Filed
Dec 02, 2022
Examiner
AHMADI, MOHSEN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
400 granted / 462 resolved
+18.6% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
487
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
74.4%
+34.4% vs TC avg
§102
14.4%
-25.6% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 462 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to the application No. 18/061,188 filed on 12/02/2022. Election/Restrictions Applicant’s election without traverse of Group I (claims 1-18) in the reply filed on 04/06/2026 is acknowledged. Claims 19-20 are withdrawn. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, lines 4-5 of claim 1; claim 14, lines 7-8; claim 7, line 2 and claim 18, line 2 recite “an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs).” The acronym “IB” is recited three times within this limitation, namely: (1) “interconnect bridge (IB),” (2) “IB through vias,” and (3) within the acronym “(IBTVs).” However, the relationship between these recitations is unclear and confusing. In particular, it is unclear what structures are included within the recited “interconnect bridge (IB).” For example, it is unclear whether the interconnect bridge includes both the “interconnect pathways” and the “through vias,” or whether the interconnect bridge includes only the “interconnect pathways.” Additionally, the phrase “IB through vias (IBTVs)” is unclear because it fails to clearly define the structure associated with the acronym “IBTVs” and creates ambiguity as to whether the vias are part of the interconnect bridge, extend through the interconnect bridge, or represent another distinct structure altogether. Accordingly, the scope and meaning of the recited limitations are unclear, rendering the claim indefinite. Furthermore, Claim 1, lines 11-12; claim 14, lines 14-15; claim 7, lines 3-4 and claim 18, lines 3-4 recite “a first active EC (AEC)” followed later by “AECs.” It appears that the term “EC” refers to “electronic component.” However, it is unclear why the claim separately recites both “EC” and “AEC” when “AEC” already appears to include “EC” within the acronym itself. As written, the claim language creates ambiguity regarding whether “EC” and “AEC” refer to the same structure, different structures, or different categories of structures. Additionally, the later recitation of “AECs” in plural form further obscures the scope of the claim because the relationship between the previously introduced “first active EC (AEC)” and the later “AECs” is unclear. Additionally, claims 1 and 14 recites “a first active EC (AEC) and a second AEC,” thereby introducing singular elements. However, later in the claims 1 and 14, line 12 and 15, respectively, recites “at least one of the first AEC or the second AECs further electrically coupled…” The phrase “at least one of the first AEC” and the second AECs is unclear because the “first AEC” and the second AECs was not previously introduced as a plurality or group of elements from which “at least one” could be selected. Further, the claim inconsistently recites “second AEC” and “second AECs,” thereby creating ambiguity as to whether the second AEC is singular or plural. Accordingly, the scope and meaning of the recited structures are unclear, rendering the claim indefinite. Claims 2 and 15 recite “an upper surface of the IB.” Claim 3 also recites “the IB” in line 2. Claim 4 also recites “the IB” in line 1. Claim 13 also recites “the IB” in lines 2 and 5-6. However, in view of the indefiniteness noted in claim 1 regarding the term “IB” and “IB through vias (IBTVs),” it is unclear which “IB” claim 2 is referring to. For example, claim 1 ambiguously recites “an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs),” such that it is unclear whether the “IB” includes only the interconnect pathways, or includes both the interconnect pathways and the IBTVs. Accordingly, the scope of “the IB” recited in claim 2 cannot be reasonably determined. Therefore, one of ordinary skill in the art would not be reasonably apprised of the scope of claims 2 and 15. Claim 3 also recite “mold through vias extending from the lower surface of the substrate toward the IBTVs.” The phrase “mold through vias” is unclear and renders the claim indefinite because it is ambiguous whether “mold through vias” is intended to recite a single structure or element, or whether Applicant is referring to the previously-recited “mold compound” in combination with “through vias.” It is further unclear whether the term “mold” constitutes a new limitation modifying the through vias, or whether Applicant intends to recite through vias formed within the mold compound. Accordingly, the metes and bounds of the claimed subject matter cannot be reasonably determined by one of ordinary skill in the art. Claim 4 depends from claim 1 and recites “IBTVs.” However, as set forth in the 112(b) rejection of claim 1, the meaning and scope of “IB through vias (IBTVs)” is unclear. For example, it is unclear whether “IBTVs” are part of the recited interconnect bridge (IB), are separate structures from the IB, or otherwise how the IBTVs structurally relate to the IB and the interconnect pathways recited in claim 1. Accordingly, because claim 4 incorporates the indefinite subject matter of claim 1 and further relies upon the unclear term “IBTVs,” the scope of claim 4 cannot be reasonably determined by one of ordinary skill in the art. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 8 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2022/0278032 to Pietambaram et al. (Pietambaram). Regarding independent claim 1, Pietambaram discloses a microelectronic assembly (Fig. 1A) comprising: a substrate (Fig. 1A: 130) including: a panel including glass (¶0022) and defining an opening (135 and ¶0024) therein; an interconnect bridge (IB) (134 and 136 are considered the interconnect bridge) in the opening (135) and including interconnect pathways and IB through vias (IBTVs) (it is noted that in view of 112 (b) above, 134 and 136 considered to be “interconnect pathways and IB through vias (IBTVs)”); and electrically conductive structures (133) at a lower surface of the substrate (130) to electrically couple the substrate (130) to another component (such as 120 or 182), at least some of the electrically conductive structures (133) coupled to the IBTVs (134 or 136) to form respective vertical electrical connections (134) between the lower surface of the substrate (130) and an upper surface of the substrate (130); and an electronic component (EC) layer (see Examiner’s mark-up below) on the upper surface of the substrate (130), the EC layer including a first active EC (AEC) (120) and a second AEC (another 120 or 180 or 121) electrically coupled to one another through the interconnect pathways (134 or 136), at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures (133). PNG media_image1.png 559 809 media_image1.png Greyscale Regarding claim 2, Pietambaram 032” discloses wherein an upper surface of the IB (Fig. 3D: 340) is substantially coextensive with an upper surface of the panel (300B and ¶0046). Regarding claim 3, Pietambaram 032” (in view of 112(b) above discloses wherein the substrate (130) includes a mold compound (¶0024) encapsulating the IB (134, 136), and wherein the at least some of the electrically conductive structures (133) include mold through vias extending from the lower surface of the substrate toward the IBTVs (Fig. 1A). Regarding claim 4, Pietambaram 032” discloses wherein a lower surface of the IB (134, 136) is substantially coextensive with the lower surface of the substrate (130), and wherein the at least some of the electrically conductive structures (133) include contact pads (133 is metal pads) on the IBTVs. Regarding claim 5, Pietambaram 032” discloses wherein the panel (130) includes panel through vias (PTVs) (144 and ¶0023) extending from the lower surface of the substrate (130) to an upper surface of the substrate (130), the first AEC (120) and the second AEC (another 120 or 121) further electrically coupled to the PTVs (144). Regarding claim 8, Pietambaram 032” discloses the EC layer (see Examiner’s mark-up in claim 1) including a mold compound (122) encapsulating the first AEC and the second AEC. Regarding claim 12, Pietambaram 032” discloses wherein the electrically conductive structures (Fig. 1A: 133) include contact pads (133) and solder balls (137) on the contact pads (133). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2022/0278032 to Pietambaram et al. (Pietambaram 032”) in view of US Pub # 2020/0176420 to Or-Bach et al. (Or-Bach). Regarding claim 6, Pietambaram 032” disclose all of the limitations of claim 5 from which this claim depends. Pietambaram 032” discloses wherein the first AEC (120) and the second AEC (another 120 or 121) are electrically coupled to the substrate (130). Pietambaram 032” fails to explicitly discloses the hybrid bonded. Or-Bach discloses a hybrid bonding (Fig. 37B and ¶0257). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the first AEC and the second AEC and the substrate of Pietambaram 032” with the hybrid bonding as taught by Or-Bach to form direct conductive connections between electronic components (¶0257). Claims 9, 11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2022/0278032 to Pietambaram et al. (Pietambaram 032”) in view of US Pub # 2022/0375865 to Pietambaram et al. (Pietambaram 865”). Regarding claim 9, Pietambaram 032” disclose all of the limitations of claim 1 from which this claim depends. Pietambaram 032” discloses a layer (Fig. 1A) defining opening (opening are formed where 120 are disposed in Fig. 1A), the first AEC (120) and the second AEC (another 120 or 121) in one or more of the openings of the layer. Pietambaram 032” fails to explicitly discloses wherein the EC layer includes a glass layer. Pietambaram 865” discloses wherein the EC layer (component included in 104-1) includes a glass layer (Fig. 1: 104-1). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided a layer of Pietambaram 032” with a glass layer as taught by Pietambaram 865” in order to isolate conductive structures or a redistribution layers from one another. Regarding claim 11, Pietambaram 032” discloses a bonding film (Fig. 3E: 310) between the glass layer (as taught Pietambaram 865”) and the panel of the substrate (130 as taught by Pietambaram 032”). Regarding independent claim 14, Pietambaram 032” discloses a microelectronic package comprising: a microelectronic assembly including: a substrate (Fig. 1A: 130) including: a panel including glass (¶0022) and defining an opening (135 and ¶0024) therein; an interconnect bridge (IB) (134 and 136 are considered the interconnect bridge) in the opening (135) and including interconnect pathways and IB through vias (IBTVs) (it is noted that in view of 112 (b) above, 134 and 136 considered to be “interconnect pathways and IB through vias (IBTVs)”); and electrically conductive structures (133) at a lower surface of the substrate (130) to electrically couple the substrate (130) to another component (such as 120 or 182), at least some of the electrically conductive structures (133) coupled to the IBTVs (134 or 136) to form respective vertical electrical connections (134) between the lower surface of the substrate (130) and an upper surface of the substrate (130); and an electronic component (EC) layer (see Examiner’s mark-up below) on the upper surface of the substrate (130), the EC layer including a first active EC (AEC) (120) and a second AEC (another 120 or 180 or 121) electrically coupled to one another through the interconnect pathways (134 or 136), at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures (133). Pietambaram 032” does not explicitly disclose a package substrate including a plurality of redistribution layers, the redistribution layer including dielectric layers and electrically conductive layers between the dielectric layers. Pietambaram 865” does not explicitly disclose a package substrate (Fig. 1:102) including a plurality of redistribution layers, the redistribution layer including dielectric layers and electrically conductive layers between the dielectric layers (¶0026 and 0039). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the microelectronic package of Pietambaram 032” with the package substrate as taught by Pietambaram 865” in order to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias) (¶0039). PNG media_image1.png 559 809 media_image1.png Greyscale Regarding claim 15, Pietambaram 032” discloses wherein an upper surface of the IB (Fig. 3D: 340) is substantially coextensive with an upper surface of the panel (300B and ¶0046), and wherein the first AEC (120 to the left side of Fig. 1A) and the second AEC (121 to the right side of Fig. 1A) have different heights with respect to one another. Regarding claim 16, Pietambaram 032” discloses wherein the panel (130) includes panel through vias (PTVs) (144 and ¶0023) extending from the lower surface of the substrate (130) to an upper surface of the substrate (130), the first AEC (120) and the second AEC (another 120 or 121) further electrically coupled to the PTVs (144). Claim 10 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2022/0278032 to Pietambaram et al. (Pietambaram 032”) in view of US Pub # 2022/0375865 to Pietambaram et al. (Pietambaram 865”) and further in view of US Pub # 2020/0168530 to Male et al. (Male 530”). Regarding claim 10, Pietambaram 032” and Pietambaram 865” disclose all of the limitations of claim 9 from which this claim depends. The combination of Pietambaram 032” and Pietambaram 865” teach the glass layer and the panel of the substrate. Pietambaram 032” and Pietambaram 865” fail to explicitly discloses a glass to glass fusion bonding interface therebetween. Male discloses a glass to glass fusion bonding interface (¶0023) therebetween. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the glass layer and the panel of the substrate as taught by Pietambaram 032” and Pietambaram 865” with the glass to glass fusion bonding interface as taught by Male in order to secure the second circuit to the analog IC (¶0023). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2022/0278032 to Pietambaram et al. (Pietambaram 032”) in view of US Pub # 2022/0375865 to Pietambaram et al. (Pietambaram 865”) and further in view of US Pub # 2020/0176420 to Or-Bach et al. (Or-Bach). Regarding claim 17, Pietambaram 032” and Pietambaram 865” disclose all of the limitations of claim 5 from which this claim depends. Pietambaram 032” and Pietambaram 865” discloses wherein the first AEC (120) and the second AEC (another 120 or 121) are electrically coupled to the substrate (130). Pietambaram 032” fails to explicitly discloses the hybrid bonded. Or-Bach discloses a hybrid bonding (Fig. 37B and ¶0257). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the first AEC and the second AEC and the substrate of Pietambaram 032” with the hybrid bonding as taught by Or-Bach to form direct conductive connections between electronic components (¶0257). Allowable Subject Matter Claims 7, 13 and 18 stand rejected under 35 U.S.C. §112 (see above) and are dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and rewritten to overcome the §112 rejection. The following is a statement of reasons for the indication of allowable subject matter: Claims 7 and 18 recites: “wherein substrate includes contact pads on upper surfaces of corresponding ones of the IBTVs and of the PTVs, wherein the first AEC and the second AEC include contact pads on lower surfaces thereof, and wherein the first AEC and the second AEC are hybrid bonded to the substrate such that respective hybrid bonded pairs of the contact pads define hybrid bonding layers therebetween with metal grain interdiffusion of one or more metal materials of the contact pads.” Claim 13 recites: “wherein the opening is a first opening, the IB is a first IB, the interconnect pathways are first interconnect pathways, the IBTVs are first IBTVs, and the vertical electrical connections are first vertical electrical connections, and wherein: the substrate defines a second opening therein and includes a second IB in the second opening, the second IB including second interconnect pathways and second IBTVs; some of the electrically conductive structures are coupled to the second IBTVs to from second respective vertical electrical connections between the lower surface of the substrate and the upper surface of the substrate; the EC layer includes a third AEC electrically coupled to the second AEC through the second interconnect pathways; and at least one of the second AEC and the third AEC are electrically coupled to one or more of said some of the electrically conductive structures.” Each of the above recitations, interpreted in combination with all other limitations of the claim and all limitations of any claims they depend from, is not taught or rendered obvious by the prior art of record and are indicated as allowable subject matter. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2022/0375844 to Brun et al.; US Pub # 2022/0201843 to Dogiamis et al.; US Pub # 2022/0189880 to Pietambaram et al.; US Pub # 2020/0212020 to Zhang et al.; US Pub # 2020/0211927 to Wan et al. and US Pub # 2020/0105653 to Elsherbini et al. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHSEN AHMADI/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Dec 02, 2022
Application Filed
Jun 12, 2023
Response after Non-Final Action
May 13, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+9.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 462 resolved cases by this examiner. Grant probability derived from career allowance rate.

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