Prosecution Insights
Last updated: May 29, 2026
Application No. 18/061,283

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

Non-Final OA §102§103§112
Filed
Dec 02, 2022
Examiner
JEAN BAPTISTE, WILNER
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
932 granted / 1079 resolved
+18.4% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1110
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
81.0%
+41.0% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1079 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 2. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 3. Claims 6, 10, 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 6, 10 and 13 recite that “wherein a concentration of Boron or Phosphorus in the build-up layer is substantially more than a concentration of Boron or Phosphorus in the core layer” is a term of degree. The specification provides only a single, isolated reference indicating that “substantially more dopants” may refer to more than ten times (10×) the amount dopants in the of the first layer. However, this disclosure is permissive and non-limiting, and the specification does not define the 10× relationship as a required threshold, minimum value, or objective boundary for the claim term. Because the specification does not consistently define or otherwise limit the scope of “substantially more,” one of ordinary skill in the art would be unable to determine with reasonable certainty how much greater the dopant concentration in the second dielectric material must be relative to the first dielectric material to satisfy the claim limitation. Claim Rejections - 35 USC § 102 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 5. Claims 1-2, 4-5, 7, 9, 11, 12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2016/0284637 to Ma et al. (Ma). Claim 1. Ma teaches an integrated circuit package substrate (Fig. 1E) comprising: -a core layer (Fig. 1E: 150 of substrate 100) comprising Silicon and Oxygen (this limitation would read through [0029] wherein is disclosed for example, glass materials that may be used with the described embodiments include pure silica (e.g., approximately 100% SiO2); -a plurality of metal vias (items 160/165) electrically coupling a first side (top surface) of the core layer and a second side (second surface) of the core layer opposite the first side; -a build-up layer (item 130/140, [0040]) on the first side of the core layer, the build-up layer comprising metal pads (item 120) and metal traces (136a-c) within a dielectric material (item 133) comprising Silicon, Oxygen, and at least one of Boron or Phosphorus, the metal pads and metal traces electrically connected to the metal vias of the core layer (this limitation would read through [0029] wherein is disclosed for example, the disclosed embodiments are not limited to silica-based glass compositions, and glasses having alternative base materials (e.g., fluoride glasses, phosphate glasses, chalcogen glasses, etc.), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and/or oxides of these and other elements). Claim 11. Ma teaches an integrated circuit (Fig. 1E) comprising: -an integrated circuit package substrate (item 200), comprising: -a core layer (item 150) comprising Silicon and Oxygen (this limitation would read through [0029] wherein is disclosed for example, glass materials that may be used with the described embodiments include pure silica (e.g., approximately 100% SiO2); -a plurality of metal vias (items 160/165) in the core layer; -a build-up layer (item 130/140, [0040]) on the core layer, the build-up layer comprising metal pads (item 120) and metal traces (136a-c) within a dielectric material comprising Silicon, Oxygen, and Boron or Phosphorus, the metal pads and metal traces electrically connected to the metal vias in the core layer; (this limitation would read through [0029] wherein is disclosed for example, the disclosed embodiments are not limited to silica-based glass compositions, and glasses having alternative base materials (e.g., fluoride glasses, phosphate glasses, chalcogen glasses, etc.), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and/or oxides of these and other elements). -and an integrated circuit die (item 210, fig. 2, [0056]) coupled to the integrated circuit package substrate. Claim 2. Ma teaches the integrated circuit package substrate of claim 1, wherein the build-up layer comprises an adhesion promotion layer between the dielectric material and the metal vias (this limitation would read through [0051] wherein is disclosed for example, in the embodiment of FIG. 1F, a wetting layer (or adhesion layer) 170 has been disposed over the wall 165 of hole 160). Claim 4. Ma teaches the integrated circuit package substrate of claim 1, wherein the core layer comprises silica (this limitation would read through [0029] wherein is disclosed for example, glass materials that may be used with the described embodiments include pure silica (e.g., approximately 100% SiO2), soda-lime glass, boro-silicate glass, and alumo-silicate glass). Claim 5. Ma teaches the integrated circuit package substrate of claim 1, wherein the core layer further comprises Boron or Phosphorus (this limitation would read through [0029] wherein is disclosed for example, boro-silicate glass. As noted, Borosilicate glass is primarily made of silica (SiO₂) and boron trioxide (B₂O₃), with smaller amounts of alumina and alkali oxides). Claims 7, 9, 12. Ma teaches the integrated circuit package substrate of claim 1, wherein the build-up layer is a first build-up layer (item 130/140, [0040]) comprising a first dielectric material (item 133) and the package substrate further comprises a second build-up layer (item 130/140, [0040]) on the first build-up layer, the second build-up layer comprising metal vias within a second dielectric material (item 133) and electrically connected to the metal vias of the first build-up layer ([0038] disclose the first side 102 of substrate 100 is a first set of electrically conductive terminals 120), the second dielectric material comprising Silicon, Oxygen, and at least one of Boron or Phosphorus (this limitation would read through [0029] wherein is disclosed for example, boro-silicate glass. As noted, Borosilicate glass is primarily made of silica (SiO₂) and boron trioxide (B₂O₃), with smaller amounts of alumina and alkali oxides). Claim 14. Ma teaches the integrated circuit device of claim 11, wherein the core layer comprises silica. (this limitation would read through [0029] wherein is disclosed for example, glass materials that may be used with the described embodiments include pure silica (e.g., approximately 100% SiO2), soda-lime glass, boro-silicate glass, and alumo-silicate glass). Claim Rejections - 35 USC § 103 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. 7. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2016/0284637 to Ma et al. (Ma) in view of US Pub # 2021/0257309 to Pietambaram et al. (Pietambaram). Regarding claim 3, Ma discloses all of the limitations of claim 2 from which this claim depends. Ma fails to explicitly disclose wherein the adhesion promotion layer comprises Silicon and Oxygen or Silicon and Nitrogen. Pietambaram discloses wherein the adhesion promotion layer (Fig. 3:304) comprises Silicon and Oxygen or Silicon and Nitrogen (¶0017). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have substitute the adhesion promotion layer of Ma with the adhesion promotion layer as taught by Pietambaram to provide good hermeticity to protect conductive structure from corrosion (¶0017). 8. Claims 6, 8, 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2016/0284637 to Ma et al. (Ma) in view of US Pub # 2021/0193544 to Lin et al. (Lin). Regarding claims 6, 8, 10 and 13. Ma discloses all of the limitations of claim 5 from which this claim depends. However, Ma does not explicitly disclose that “wherein a concentration of Boron or Phosphorus in the build-up layer is substantially more than a concentration of Boron or Phosphorus in the core layer”, as recited in claim 6. Nevertheless, the relative dopant concentration between dielectric layers is a result-effective variable, because dopant concentration is known in the art to affect dielectric properties such as electrical performance, stability, and process compatibility. It would have been within the level of ordinary skill in the art to adjust or optimize the dopant concentration in one dielectric layer relative to another to achieve desired material or device characteristics (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed height or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990) In accordance with established case law, where the prior art recognizes a variable as affecting the result, optimization of that variable through routine experimentation is considered obvious, even if the prior art does not disclose the claimed optimum or specific value. The claimed relative concentration therefore represents a difference in degree, not in kind, from the teachings of Ma. Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to provide the second dielectric material with a higher dopant concentration than the first dielectric material, including a concentration that is substantially greater, as claimed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 02, 2022
Application Filed
Jun 12, 2023
Response after Non-Final Action
Apr 13, 2026
Non-Final Rejection mailed — §102, §103, §112
Apr 21, 2026
Applicant Interview (Telephonic)
Apr 23, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1079 resolved cases by this examiner. Grant probability derived from career allowance rate.

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