DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 12/05/2022 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Objections
Claims 13-18 are objected to because of the following informalities.
Claim 13 is objected to because of the following informalities: “sidewall of he second vertical segment,” should be written as “sidewall of the second vertical segment,”.
Claim 16 objected to because of the following informalities: “comma” is missing after claim 15.
The balance of claims are objected to for being dependent upon an already objected to claim.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 8-15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeffrey Smith et al, (hereinafter SMITH), [different embodiments], US 20190058036 A1.
Regarding Claim 1, SMITH teaches a microelectronic structure (Fig. 6, 600, structure) comprising:
a first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) that includes a plurality of first transistors (annotated Figure 6, 610, cells include three FETs on a lower level, 603 and three FETs on an upper level, 605 of the cell, [0026]), wherein the plurality of first transistors (annotated Figure 6, 610, cells include three FETs on a lower level, 603 and three FETs on an upper level, 605 of the cell, [0026]) includes at least one first source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]);
a second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) includes a plurality of second transistors (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]), wherein the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) is oriented parallel (annotated Figure 6) to the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]), wherein the plurality of second transistors (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) includes at least two second source/drains (annotated Figure 6, 631/631′, S/D regions, [0027]);
a gate cut (Figs. 4C/6, 450/650, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) located between the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]); and
a source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) connected to the at least one first source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]) and is connected to at least one of the at least two second source/drains (annotated Figure 6, 631/631′, S/D regions, [0027]), wherein a portion of the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) extends parallel (annotated Figure 6) to the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]).
Thought SMITH equate a “dummy gate, 650” for gate cut in an embodiment of Figure 6, SMITH does not explicitly disclose a microrelectronic structure comprising: a gate cut located between the first nano device and the second nanodevice.
SMITH teaches in different embodiment of Figures 4C/4D, a microrelectronic structure (Figs. 4C/4D, 400, structure) comprising: a gate cut (Figs. 4C/4D, 450, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) located between the first nano device (Figs. 4C/4D, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (Figs. 4C/4D, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified a first embodiment as represented by the Figure 6 of SMITH to incorporate the teachings of a different embodiment as represented by the Figures 4C/4D, such that the microelectronic structure, a gate cut located between the first nano device and the second nanodevice, so that the single diffusion break, 450 for the nanowire or nanosheet process is done through a gate cut in either the replacement or metal gate (SMITH, [0048]).
Regarding Claim 2, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 1, wherein the gate cut (Figs. 4C/6, 450/650, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) comprises: a dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]), wherein the dielectric liner is includes (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]) a first vertical segment (annotated Figure 6), a second vertical segment (annotated Figure 6), and a bottom segment (annotated Figure 6); and a dielectric fill layer (Fig. 6, 651, dummy gate is filled with a dielectric material, [0032]) located between the first vertical segment (annotated Figure 6) and the second vertical segments (annotated Figure 6) and located on top of the bottom segment (annotated Figure 6).
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Regarding Claim 3, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 2, wherein the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) includes a bar section (annotated Figure 6) that is located on top of the dielectric fill layer (Fig. 6, 637, dielectric cap, [0026]).
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Regarding Claim 4, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 3, wherein the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) is in contact with a top wall and sidewalls of a portion of the first vertical segment (annotated Figure 6) of the dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]).
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Regarding Claim 8, SMITH teaches a microelectronic structure (Fig. 6, 600, structure) comprising:
a first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) that includes a plurality of first transistors (annotated Figure 6, 610, cells include three FETs on a lower level, 603 and three FETs on an upper level, 605 of the cell, [0026]), wherein the plurality of first transistors (annotated Figure 6, 610, cells include three FETs on a lower level, 603 and three FETs on an upper level, 605 of the cell, [0026]) includes at least one first source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]);
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a second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) includes a plurality of second transistors (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]), wherein the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) is oriented parallel (annotated Figure 6) to the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]), wherein the plurality of second transistors (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) includes at least a second (annotated Figure 6, 631/631′, S/D regions, [0027]) and a third source/drains (annotated Figure 6, 631/631′, S/D regions, [0027]);
a gate cut (Figs. 4C/6, 450/650, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) located between the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]);
a first source/drain contact (annotated Figure 6, 633, S/D contact metal, [0026]) connected to the at least one first source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]) and is connected to at least the second source/drains (annotated Figure 6, 631/631′, S/D regions, [0027]), wherein a portion of the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) extends parallel (annotated Figure 6) to the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]); and
Thought SMITH equate a “dummy gate, 650” for gate cut in an embodiment of Figure 6, SMITH does not explicitly disclose a microrelectronic structure comprising: a gate cut located between the first nano device and the second nanodevice; and a dielectric pillar between the at least one first source/drain of the first nano device and the at least second source/drain of the second nano device.
SMITH teaches in different embodiment of Figures 4C/4D, a microrelectronic structure (Figs. 4C/4D, 400, structure) comprising: a gate cut (Figs. 4C/4D, 450, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) located between the first nano device (Figs. 4C/4D, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (Figs. 4C/4D, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]); and
a dielectric pillar (Fig. 4D, 453, dielectric fill material in the single diffusion break, 450, or to involve physical cut gate which is filled with dielectric material, 453, [0053]) located between the at least one first source/drain (annotated Figure 4D, 431, S/D structure, [0052]) of the first nano device (annotated Figure 4C, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the at least second source/drain (annotated Figure 4D, 431, S/D structure, [0052]) of the second nano device (annotated Figure 4C, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified a first embodiment as represented by the Figure 6 of SMITH to incorporate the teachings of a different embodiment as represented by the Figures 4C/4D, such that the microelectronic structure, a gate cut located between the first nano device and the second nanodevice; and a dielectric pillar between the at least one first source/drain of the first nano device and the at least second source/drain of the second nano device. The single diffusion break, 450 for the nanowire or nanosheet process is done through a gate cut in either the replacement or metal gate and is filled will dielectric material, 453 as a dielectric wall between the nano devices (SMITH, [0048], [0053]).
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Regarding Claim 9, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 8, wherein the gate cut (Figs. 4C/6, 450/650, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) comprises:
a dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]), wherein the dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]) is includes a first vertical segment (annotated Figure 6), a second vertical segment (annotated Figure 6), and a bottom segment (annotated Figure 6); and
a dielectric fill layer (Fig. 6, 651, dummy gate is filled with a dielectric material, [0032]) located between the first vertical segment (annotated Figure 6) and second vertical segments (annotated Figure 6) and located on top of the bottom segment (annotated Figure 6).
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Regarding Claim 10, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 9, wherein the first source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) includes a bar section (annotated Figure 6) that is located on top of the dielectric fill layer (Fig. 6, 637, dielectric cap, [0026]).
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Regarding Claim 11, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 10, wherein the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) is in contact with a top wall and sidewalls of a portion of the first vertical segment (annotated Figure 6) of the dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]).
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Regarding Claim 12, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 11, wherein the dielectric pillar (Fig. 4D, 453, dielectric fill material in the single diffusion break, 450, or to involve physical cut gate which is filled with dielectric material, 453, [0053]) extends vertically from the second vertical segment (annotated Figure 4D) of the dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]).
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Regarding Claim 13, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 12, wherein the bar section (annotated Figure 6) of the first source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) is flush against a sidewall of he second vertical segment (annotated Figure 6), and wherein the bar section (annotated Figure 6) of the first source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) is flush against a first sidewall of the dielectric pillar (Fig. 4D, 453, dielectric fill material in the single diffusion break, 450, or to involve physical cut gate which is filled with dielectric material, 453, [0053]).
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Regarding Claim 14, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 13, further comprising: a second source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) that is connected to the third source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]).
Regarding Claim 15, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 14, wherein the second source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) is flush against a second sidewall of the dielectric pillar, and wherein the dielectric pillar (Fig. 4D, 453, dielectric fill material in the single diffusion break, 450, or to involve physical cut gate which is filled with dielectric material, 453, [0053]) separates the bar section (annotated Figure 6) of the first source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) and the second source/drain contact (Fig. 6, 633, S/D contact metal, [0026]).
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Regarding Claim 19, SMITH teaches a method (Fig. 6, FINCUT method, [0028]) comprising:
forming a first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) that includes a plurality of first transistors (annotated Figure 6, 610, cells include three FETs on a lower level, 603 and three FETs on an upper level, 605 of the cell, [0026]), wherein the plurality of first transistors (annotated Figure 6, 610, cells include three FETs on a lower level, 603 and three FETs on an upper level, 605 of the cell, [0026]) includes at least one first source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]);
forming a second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) includes a plurality of second transistors (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]), wherein the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) is oriented parallel (annotated Figure 6) to the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]), wherein the plurality of second transistors (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) includes at least a second (annotated Figure 6, 631/631′, S/D regions, [0027]) and a third source/drains (annotated Figure 6, 631/631′, S/D regions, [0027]);
forming a gate cut (Figs. 4C/6, 450/650, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) located between the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]);
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forming a source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) connected to the at least one first source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]) and is connected to the second source/drain (annotated Figure 6, 631/631′, S/D regions, [0027]), wherein a portion of the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) extends parallel (annotated Figure 6) to the first nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (annotated Figure 6, 621, nanochannel structures, may be nanowires, or nanosheets, [0025]).
Thought SMITH equate a “dummy gate, 650” for gate cut in an embodiment of Figure 6, SMITH does not explicitly disclose a method comprising: forming a gate cut located between the first nano device and the second nanodevice; and forming a dielectric pillar located between the at least one first source/drain of the first nano device and the at least second source/drain of the second nano device.
SMITH teaches in different embodiment of Figures 4C/4D, a microrelectronic structure (Figs. 4C/4D, 400, structure) comprising: a gate cut (Figs. 4C/4D, 450, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) located between the first nano device (Figs. 4C/4D, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the second nano device (Figs. 4C/4D, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]); and
forming a dielectric pillar (Fig. 4D, 453, dielectric fill material in the single diffusion break, 450, or to involve physical cut gate which is filled with dielectric material, 453, [0053]) located between the at least one first source/drain (annotated Figure 4D, 431, S/D structure, [0052]) of the first nano device (annotated Figure 4C, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]) and the at least second source/drain (annotated Figure 4D, 431, S/D structure, [0052]) of the second nano device (annotated Figure 4C, 421, nanochannel structures, may be nanowires, or nanosheets, [0025]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified a first embodiment as represented by the Figure 6 of SMITH to incorporate the teachings of a different embodiment as represented by the Figures 4C/4D, such that the microelectronic structure, forming a gate cut located between the first nano device and the second nanodevice; and forming a dielectric pillar located between the at least one first source/drain of the first nano device and the at least second source/drain of the second nano device. The single diffusion break, 450 for the nanowire or nanosheet process is done through a gate cut in either the replacement or metal gate and is filled will dielectric material, 453 as a dielectric wall between the nano devices (SMITH, [0048], [0053]).
Regarding Claim 20, SMITH teaches the method (Fig. 6, FINCUT method, [0028]) of claim 19, further comprising:
wherein the gate cut (Figs. 4C/6, 450/650, the single diffusion break; dummy gate or a gate “cut”, [0033]; which is filled with a dielectric material, 453 [0053]) comprises:
a dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]), wherein the dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]) is includes a first vertical segment (annotated Figure 6), a second vertical segment (annotated Figure 6), and a bottom segment (annotated Figure 6); and
a dielectric fill layer (Fig. 6, 651, dummy gate is filled with a dielectric material, [0032]) located between the first (annotated Figure 6) and second vertical segments (annotated Figure 6) and located on top of the bottom segment (annotated Figure 6);
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wherein the source/drain contact (Fig. 6, 633, S/D contact metal, [0026]) includes a bar section (annotated Figure 6) that is located on top of the dielectric fill layer (Fig. 6, 637, dielectric cap, [0026]); and
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wherein the dielectric pillar (Fig. 4D, 453, dielectric fill material in the single diffusion break, 450, or to involve physical cut gate which is filled with dielectric material, 453, [0053]) extends vertically from the second vertical segment (annotated Figure 4D) of the dielectric liner (Figs. 4C/4D/6, 429/629, low-k spacer, [0041], [0025]).
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Claim(s) 5-7, and 16-18, is/are rejected under 35 U.S.C. 103 as being unpatentable over SMITH in view of Niloy Mukherjee et al, (MUKHERJEE), US 20130320417 A1.
Regarding Claim 5, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 4.
SMITH does not explicitly disclose the microelectronic structure, wherein the source/drain contact includes a first protrusion and a second protrusion that extends off the bar section of the source/drain contact.
MUKHERJEE teaches the microelectronic structure (Fig. 3, 300, active device), wherein the source/drain contact (Fig. 3, 116, contact of an epitaxial, raised structure, 112, prominence) includes a first protrusion (Fig. 3, 124, contact interconnect is disposed in the first interconnect ILD layer, 122, [0019]) and a second protrusion (Fig. 3, 124, contact interconnect, is disposed in the second interconnect ILD layer, 128, [0019]) that extends off the bar section (Fig. 3, 126, metallization trace) of the source/drain contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified SMITH to incorporate the teachings of MUKHERJEE, such that the microelectronic structure, wherein the source/drain contact includes a first protrusion and a second protrusion that extends off the bar section of the source/drain contact, so that the metallization layers include vias and interconnects that function as electrical pathways to interconnect the devices (MUKHERJEE, [0001]).
Regarding Claim 6, SMITH as modified by MUKHERJEE teaches the microelectronic structure of claim 5.
MUKHERJEE further teaches the microelectronic structure (Fig. 3, 300, active device), wherein the first protrusion (Fig. 3, 124, contact interconnect is disposed in the first interconnect ILD layer, 122, [0019]) is in contact with the at least one first source/drain (Fig. 3, 112, the prominence is a raised S/D structure, 112, [0019]), and wherein the second protrusion (Fig. 3, 124, contact interconnect, is disposed in the second interconnect ILD layer, 128, [0019]) is in contact with the at least one of the at least two second source/drains (Fig. 3, 112, the prominence is a raised S/D structure, 112, [0019]).
Regarding Claim 7, SMITH as modified by MUKHERJEE teaches the microelectronic structure of claim 6.
MUKHERJEE further teaches the microelectronic structure (Fig. 3, 300, active device), wherein the first protrusion (Fig. 3, 124, contact interconnect is disposed in the first interconnect ILD layer, 122, [0019]) and the second protrusion (Fig. 3, 124, contact interconnect, is disposed in the second interconnect ILD layer, 128, [0019]) are offset from each other (Fig. 3, [0020]).
Regarding Claim 16, SMITH teaches the microelectronic structure (Fig. 6, 600, structure) of claim 15.
SMITH does not explicitly disclose the microelectronic structure, wherein the at least one first source/drain contact includes a first protrusion and a second protrusion that extends off the bar section.
MUKHERJEE teaches the microelectronic structure (Fig. 3, 300, active device), wherein the at least one first source/drain contact (Fig. 3, 116, contact of an epitaxial, raised structure, 112, prominence) includes a first protrusion (Fig. 3, 124, contact interconnect is disposed in the first interconnect ILD layer, 122, [0019]) and a second protrusion (Fig. 3, 124, contact interconnect, is disposed in the second interconnect ILD layer, 128, [0019]) that extends off the bar section (Fig. 3, 126, metallization trace).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified SMITH to incorporate the teachings of MUKHERJEE, such that the microelectronic structure, wherein the at least one first source/drain contact includes a first protrusion and a second protrusion that extends off the bar section, so that the metallization layers include vias and interconnects that function as electrical pathways to interconnect the devices (MUKHERJEE, [0001]).
Regarding Claim 17, SMITH as modified by MUKHERJEE teaches the microelectronic structure of claim 16.
MUKHERJEE further teaches the microelectronic structure (Fig. 3, 300, active device), wherein the first protrusion (Fig. 3, 124, contact interconnect is disposed in the first interconnect ILD layer, 122, [0019]) is in contact with the at least one first source/drain (Fig. 3, 112, the prominence is a raised S/D structure, 112, [0019]), and wherein the second protrusion (Fig. 3, 124, contact interconnect, is disposed in the second interconnect ILD layer, 128, [0019]) is in contact with the at least one of the at least second source/drains (Fig. 3, 112, the prominence is a raised S/D structure, 112, [0019]).
Regarding Claim 18, SMITH as modified by MUKHERJEE teaches the microelectronic structure of claim 17.
MUKHERJEE further teaches the microelectronic structure (Fig. 3, 300, active device), wherein the first protrusion (Fig. 3, 124, contact interconnect is disposed in the first interconnect ILD layer, 122, [0019]) and the second protrusion (Fig. 3, 124, contact interconnect, is disposed in the second interconnect ILD layer, 128, [0019]) are offset from each other (Fig. 3, [0020]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220140151 A1 – Figure 14
STATEMENT OF RELEVANCE - Protrusion of 112P of the source/drain regions, 112.
US 20190164741 A1 – Figure 16
STATEMENT OF RELEVANCE - Dielectric feature, 114a/114b, between S/D features, 162a/162b,
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812