DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/16/2026 has been entered.
Response to Arguments
Applicant’s response has been fully considered.
In reference to independent claim 1, Applicant’s amendments and the accompanying arguments with respect to the first via connecting a circuit input pin to the second FET and a second via connecting the circuit input pin to the first FET, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li et al. (US 2020/0235098).
In reference to independent claim 9, Applicant’s arguments with respect to Li not anticipating a first via connecting a circuit input pin to the at least one PFET device and a second via connecting the circuit input pin to the at least one NFET device have been fully considered but are not persuasive.
Applicant argued that as seen in Figure 2A of Li, there is not one of vias MSD, MG, or MDG that is connected to both the NFET and the PFET.
“Circuit input pin” has been interpreted to include a connection to the gate electrodes, consistent with Applicant’s description of items 50, A, B, S, and
S
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, provided at least in paragraph 52 of the specification and Figures 1-3.
Li clearly discloses connection MG connected to both the NFET and PFET gates 222L and 222U by vias 230UG and 232LG in Figure 2B (and likewise, MG connected to both the NFET and PFET gates 522U and 522L by vias 532LG and 530UG in Figure 5B, currently relied upon below). By comparison to Applicant’s Figure 3, MG of Li is clearly analogous to Applicant’s feature 50, and 230UG/530UG and 232LG/532LG are clearly analogous 62 and 60, respectively.
As Applicant points out, connections of MG to both the NFET and PFET are not shown in Figure 2A of Li, however this is because both connections are not present in the cross-section shown in Figure 2A (cross section X-X’), see Figure 2D and paragraph 39. However, as seen in Figures 2B (and similarly Figure 5B), the connection of MG to both the NFET and PFET gates is clearly shown in the Y-Y’ cross section.
In reference to independent claim 17, Applicant’s amendments and the accompanying arguments with respect to the first device layer having more than one device and the second device layer having more than one device, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Guo et al. (US 2016/0211259.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 10, and 14-16 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Li et al. (US 2020/0235098).
In reference to claim 9, Li et al. (US 2020/0235098), hereafter “Li,” discloses a semiconductor structure, with reference to Figure 5B, comprising:
a first field effect transistor (FET) including a first device layer 502U having at least one N-channel field effect transistor (NFET) device;
a second FET including a second device layer 502L having at least one P-channel field effect transistor (PFET) device, paragraph 72, and
an electrical connection between a gate 522U of the first FET and a gate 522L of the second FET at a stepped portion of the first device layer, wherein a first via, VIA 532LG, connects a circuit input pin MG to the at least one PFET device and a second via, TRENCH CONTACT 530UG, connects the circuit input pin MG to the at least one NFET device, paragraph 86.
In reference to claim 10, Li discloses the first FET (NFET) 502U is stacked over the second FET (PFET) 502L, Figure 5B, paragraph 72, (mislabeled in Figure 5A).
In reference to claim 14, Li discloses the first device layer 502U generally overlaps the second device layer 502L, Figure 2B.
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[AltContent: textbox (Double stepped configuration)][AltContent: arrow][AltContent: arrow]In reference to claim 15, Li discloses the gate 522U of the first FET is positioned above the first device layer having a doubled stepped configuration, Figure 5B, annotated below.
In reference to claim 16, Li discloses the gate 522U of the first FET is positioned above both the first and second device layers, Figure 5B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0235098) in view of Guo et al. (US 2016/0211259).
In reference to claim 1, Li discloses a semiconductor structure, with reference to Figure 2B, comprising:
a first field effect transistor (FET) including a first device layer 202U;
a second FET including a second device layer 202L, where the first device layer has a stepped portion with respect to the second device layer, paragraph 39, and
an electrical connection between a gate 222U of the first FET and a gate 222L of the second FET at the stepped portion of the first device layer,
wherein a first via, VIA 232LG, connects a circuit input pin MG to the second FET and a second via, TRENCH CONTACT 230UG, connects the circuit input pin MG to the first FET, paragraph 53.
Li does not disclose the first device layer having a plurality of sections, each section being offset from an adjacent section, wherein at least one section has two offsets.
Guo et al. (US 2016/0211259), hereafter “Guo,” discloses a semiconductor structure comprising:
a first FET including a first device layer, 260 in Figures 27 and 28D, the first device layer having a plurality of sections, each section being offset from an adjacent section, wherein at least one section has two offsets (middle section), see annotated Figure 28D below;
[AltContent: connector]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first device layer to have a plurality of sections, each section being offset from an adjacent section, wherein at least one section has two offsets. One would have been motivated to do so in order to form multiple FETs arranged laterally (regions 202 and 204 for example) while accommodating electrical connection to FETs arranged vertically (contact 294 for example), paragraphs 85 and 87.
In reference to claim 2, Li discloses the first FET 202U is stacked over the second FET 202L, Figure 2B.
In reference to claim 4, Li discloses the first FET is a p-type FET and the second FET is an n-type FET, paragraph 39.
In reference to claim 5, Li discloses the gate of the first FET 227U is positioned above the first device layer having the stepped portion, Figure 2B.
In reference to claim 6, Li discloses the gate of the first FET 227U is positioned above both the first and second device layers, Figure 2B.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0235098) in view of Guo et al. (US 2016/0211259) as applied above and further in view of Lee et al. (US 2023/0361119).
In reference to claim 3, Li in view of Guo does not disclose the second device layer is larger than the first device layer.
Lee et al. (US 2023/0361119) discloses a semiconductor structure including teaching offset device layers in combination with a second device layer AR1, GE1 in Figures 4D and 4E that is larger than the first device layer AR2, GE2, see also paragraph 50. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second device layer to be larger than the first device layer. One would have been motivated to do so in order to facilitate forming interconnections to the source, drain, and gate of respective stacked devices, paragraphs 70 and 82.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0235098) in view of Guo et al. (US 2016/0211259) as applied to claim 1 above and further in view of Guo et al. (US 2017/0062319).
In reference to claim 7, Li does not disclose the second FET includes a floating gate.
Guo et al. (US 2017/0062319) discloses an analogous semiconductor device including teaching a second FET includes a floating gate, 80A in Figure 1B, paragraph 18. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify one of the gates 405G of Hwang to be a floating gate as taught by Guo for the second FET to include a floating gate. One would have been motivated to do so in order to provide an electrical contact to connect different tiers of the device, paragraph 28.
In reference to claim 8, Li discloses the gate 227L vertically aligned with the stepped portion of the first device layer, and Guo discloses the second device including the floating gate, as addressed above in reference to claims 1 and 7.
It results naturally from the combination of Li and Guo that the floating gate is vertically aligned with the stepped portion of the first device layer.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0235098) in view of Chen et al. (US 2023/0036522).
In reference to claim 11, Li does not disclose the second device layer is larger than the first device layer.
Chen et al. (US 2023/0036522), hereafter “Chen,” discloses a semiconductor device including teaching a second device layer, 134n in Figure 1C, is larger than the first device layer 134p. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second device layer to be larger than the first device layer. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one device overlap configuration for another.
In reference to claim 12, Li discloses the first device layer is centered with respect to the second device layer, Figure 5A.
In reference to claim 13, Li discloses the first device layer is positioned adjacent (vertically adjacent), Figure 5A, the second device layer such that a surface of the first device layer is horizontally aligned with a surface of the second device layer, Figure 5A.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0235098) in view of Chen et al. (US 2023/0036522) and Guo et al. (US 2016/0211259.
In reference to claim 17, Li discloses a semiconductor structure, with reference to Figure 2B, comprising:
a first field effect transistor (FET) including a first device layer 202U;
a second FET including a second device layer 202L; and
an electrical connection between a gate 222U of the first FET and a gate 222L of the second FET at a stepped portion of the first device layer, wherein a first via, VIA 232LG, connects a circuit input pin MG to the second FET and a second via, TRENCH CONTACT 230UG, connects the circuit input pin to the first FET, paragraph 53.
Li does not disclose the first device layer having more than one device,
the second device layer having more than one device, or
the second device layer is larger than the first device layer.
Chen discloses a semiconductor device including teaching a second device layer, 134n in Figure 1C, is larger than the first device layer 134p. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second device layer to be larger than the first device layer. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one device overlap configuration for another.
Guo discloses an analogous semiconductor device including teaching a first field effect transistor (FET) including a first device layer having more than one device, P2, N2 in Figure 27; and
a second FET including a second device layer having more than one device, P1, N1, paragraph 87.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first device layer to have more than one device and the second device layer to have more than one device. One would have been motivated to do so in order to provide a multiple transistor circuit device such as the NAND gate exemplified by Figures 27 and 29 of Guo.
In reference to claim 18, Li discloses the first device layer has a stepped portion with respect to the second device layer, Figure 2B.
In reference to claim 19, Li discloses the first FET 202U is stacked over the second FET 202L.
In reference to claim 20, Li discloses the gate 222U of the first FET is positioned above the first device layer having a stepped portion (202U at a level above the lower portion of the stepped portion in the Z direction, Figure 2B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chehab et al. (US 2025/0048690), Liebmann et al. (US 2022/0181322), Zhu et al. (US 2018/0108577), Smith et al. (US 2019/0172828), Kim et al. (US 2023/0105461), Lee (US 2023/0107258), Kim et al. (US 2023/0282703), and Lee et al. (US 2023/0292508), disclose related three dimensionally integrated semiconductor devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
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