Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The objection to the specification has been withdrawn in view of the amendments filed 12/08/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Takahashi et. Al. (WO 2022104660 A1 hereinafter Takahashi).
Regarding claim 1, Takahashi teaches in Figs. 1 and 18 with associated text, an image sensor comprising: a first semiconductor substrate 2; a photoelectric conversion region 8 in the first semiconductor substrate (Fig. 18, [0060]); a buried insulating film 6 on the first semiconductor substrate, the buried insulating film covering a first region (region of 2 contacting 6) of the first semiconductor substrate and exposing a second region (region of 2 not contacting 6)) of the first semiconductor substrate (Fig. 18, [0059]); a second semiconductor substrate 4 on the buried insulating film (Fig. 18, [0059]); an operating gate structure 30 defining a first channel (portion of 4 between 26 and 28) of a first conductive type (the device is a PMOS so has P-type doping [0070]) in the second semiconductor substrate (Fig. 18, [0063]); and a transfer gate structure 14 defining a second channel of a second conductive type (embodiment where 12 is n-type is chosen for the floating diffusion region and so the conductivity type of the transistor [0061]) (Fig. 18, [[0061]]), wherein the buried insulating film and the second semiconductor substrate are spaced laterally apart from the transfer gate structure (Fig. 18).
Regarding claim 2, Takahashi teaches the first conductive type is a p-type, and the second conductive type is an n-type ([0061] and [0071]).
Regarding claim 3, Takahashi teaches the first semiconductor substrate has the first conductive type [0060], and the second semiconductor substrate has the second conductive type (device is PMOS [0070] so that at least the channel region of 4 is N-type).
Regarding claim 4, Takahashi teaches the second region of the first semiconductor substrate defines a substrate trench (trench in 6 and 4, Fig. 18) at least partially overlapping the photoelectric conversion region, and at least a part of the transfer gate structure fills the substrate trench (Fig. 18).
Regarding claim 7, Takahashi teaches a source/drain region (26 or 28) in the second semiconductor substrate, the source/drain region adjacent to side surfaces of the operating gate structure and having the first conductive type (Fig. 18, conductivity type of the source drain regions defines the conductivity type of a field effect transistor).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 9, 11-12, 15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi as applied to claim 1 and further in view of Takahashi et. Al. (US 20200266229 A1 hereinafter Takahashi229).
Regarding claim 5, Takahashi teaches the image sensor of claim 1, wherein a longitudinal direction of the first channel is parallel to an upper surface of the second semiconductor substrate (Fig. 18, [0070]).
Takahashi does not specify a longitudinal direction of the second channel intersects an upper surface of the first semiconductor substrate (from 112 to 106 Fig. 9, [0030]).
Takahashi229 discloses in Figs. 9 with associated text a device similar to that of Takahashi wherein a longitudinal direction of a second channel (channel extending along vertical edge of 114 [0030]) intersects an upper surface of the first semiconductor substrate (from 112 to 106 Fig. 9, [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use transistor and a second channel structure similar to Takahashi229 for that of Takahashi because according to Takahashi229 the transfer gate 114 is configured to selectively form a conductive channel between the photodetector 106 and the floating diffusion node 112, such that charge accumulated (e.g., via absorbing incident radiation) in the photodetector 106 may be transferred to the floating diffusion node 112 [0032] so that such a structure would be suitable for transferring charge accumulated in the photodetector of Takahashi.
Regarding claim 9, Takahashi teaches the image sensor of claim 1, wherein an upper surface of the second region of the first semiconductor substrate is higher than an upper surface of the first region of the first semiconductor substrate and lower than an upper surface of the buried insulating film (Fig. 18)..
Takahashi does not specify an upper surface of the second region of the first semiconductor substrate is higher than an upper surface of the first region of the first semiconductor substrate.
Takahashi229 discloses in Figs. 9 with associated text a device similar to that of Takahashi wherein an upper surface of a second region 120f of a first semiconductor substrate 104 is higher than an upper surface of a first region (surface interfacing gate dielectric 1118) of the first semiconductor substrate (Fig. 9 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use transistor and a second channel structure similar to Takahashi229 for that of Takahashi so that an upper surface of the second region of the first semiconductor substrate is higher than an upper surface of the first region of the first semiconductor substrate because according to Takahashi229 the transfer gate 114 is configured to selectively form a conductive channel between the photodetector 106 and the floating diffusion node 112, such that charge accumulated (e.g., via absorbing incident radiation) in the photodetector 106 may be transferred to the floating diffusion node 112 [0032] so that such a structure would be suitable for transferring charge accumulated in the photodetector of Takahashi.
Regarding claim 11, Takahashi teaches in Figs. 1 and 18 with associated text an image sensor comprising: a first semiconductor substrate 2 including a first surface (upper surface) and a second surface opposite to each other; a photoelectric conversion region 8 in the first semiconductor substrate (Fig. 18, [0061]); a buried insulating film 6 on the first surface of the first semiconductor substrate, the buried insulating film covering a first region (region of 2 contacting 6) of the first semiconductor substrate and exposing a second region (region of 2 contacting 6) of the first semiconductor substrate (Fig. 18, [0059]); a second semiconductor substrate 4 on the buried insulating film (Fig. 14, [0059]); an operating gate structure 30 on the second semiconductor substrate (Fig. 18, [0070]); and a transfer gate structure 14 on the second region of the first semiconductor substrate, wherein the buried insulating film and the second semiconductor substrate are spaced laterally apart from the transfer gate structure (Fig. 18)..
Takahashi does not specify at least a part of the transfer gate structure extending from the first surface of the first semiconductor substrate toward the photoelectric conversion region.
Takahashi229 discloses in Figs. 9 with associated text a device similar to that of Takahashi wherein at least a part of a transfer gate structure 116 extending from the first surface 102f of the first semiconductor substrate 102 toward the photoelectric conversion region 106 (Fig. 9, [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use transfer gate structure similar to Takahashi229 for that of Takahashi so that an upper surface of the second region of the first semiconductor substrate is higher than an upper surface of the first region of the first semiconductor substrate because according to Takahashi229 the transfer gate 114 is configured to selectively form a conductive channel between the photodetector 106 and the floating diffusion node 112, such that charge accumulated (e.g., via absorbing incident radiation) in the photodetector 106 may be transferred to the floating diffusion node 112 [0032] so that such a structure would be suitable for transferring charge accumulated in the photodetector of Takahashi.
Regarding claim 12, Takahashi in view of Takahashi229 teaches the transfer gate structure includes a gate electrode (116 or Takahashi229) including a first portion disposed in the second region of the first semiconductor substrate and a second portion protruding from the first surface of the first semiconductor substrate (Fig. 9, [0030]), a gate dielectric film 118 interposed between the first portion of the gate electrode and the first semiconductor substrate (Fig. 9, [0030]), and a gate spacer 702 extending alongside surfaces of the second portion of the gate electrode (Fig. 9, [0030]).
Regarding claim 15, Takahashi teaches the operating gate structure and the second semiconductor substrate define a PMOS transistor ([0070]), and the transfer gate structure and the second region of the first semiconductor substrate define an NMOS transistor (the floating diffusion node is N-type [0061] so that the transistor is NMOS).
Regarding claim 17, Takahashi teaches the second surface of the first semiconductor substrate is a photo-receiving surface arranged to receive incident light (Fig. 18, [0103]).
Regarding claim 18, Takahashi teaches in Fig. 9 with associated text an image sensor comprising: a first semiconductor substrate 2 including a first surface and a second surface opposite to each other, the first semiconductor substrate being a p-type (Fig. 18, [0060]); an element separation pattern 116 defining a plurality of pixel regions in the first semiconductor substrate (Fig. 18, [0062]); an n-type photoelectric conversion region 8 in the first semiconductor substrate of each of the pixel regions (Fig. 18, [0060]); a buried insulating film 6 on the first surface of the first semiconductor substrate, the buried insulating film covering a first region of the first semiconductor substrate and exposing a second region of the first semiconductor substrate (see annotated figure above, [0122]); an n-type second semiconductor substrate 4 on the buried insulating film (Fig. 18, region between 26 and 28 at least has a doping type opposite that of 256 and 28 so that it would be the second conductivity and so n-type [0126]); an operating gate structure 30 defining a p-type channel in the second semiconductor substrate (Fig. 18, [0070]); a transfer gate structure 14 defining an n-type channel in the second region of the first semiconductor substrate (the floating diffusion node has n-type doping type [0061] so that the channel is n-type); a first wiring structure 216 on the first surface of the first semiconductor substrate, the first wiring structure connected to the operating gate structure and the transfer gate structure (Fig. 18, [0093]); and a microlens 202 on the second surface of the first semiconductor substrate, the microlens corresponding to each of the pixel regions (Fig. 18, [0093]), wherein the buried insulating film and the n-type second semiconductor substrate are spaced laterally apart from the transfer gate structure (Fig. 18)..
Takahashi does not specify at least a part of the transfer gate structure extending from the first surface of the first semiconductor substrate toward the photoelectric conversion region.
Takahashi229 discloses in Figs. 9 with associated text a device similar to that of Takahashi wherein at least a part of a transfer gate structure 116 extending from the first surface 102f of the first semiconductor substrate 102 toward the photoelectric conversion region 106 (Fig. 9, [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use transfer gate structure similar to Takahashi229 for that of Takahashi so that an upper surface of the second region of the first semiconductor substrate is higher than an upper surface of the first region of the first semiconductor substrate because according to Takahashi229 the transfer gate 114 is configured to selectively form a conductive channel between the photodetector 106 and the floating diffusion node 112, such that charge accumulated (e.g., via absorbing incident radiation) in the photodetector 106 may be transferred to the floating diffusion node 112 [0032] so that such a structure would be suitable for transferring charge accumulated in the photodetector of Takahashi.
Regarding claim 19, Takahashi teaches a peripheral circuit board 212 including a third surface (lower surface of 212 opposite to the first surface of the first semiconductor substrate (Fig. 18, [0093]); a peripheral circuit element [0093] on the third surface of the peripheral circuit board (Fig. 18, [0034]); and a second wiring structure ([0093]) on the third surface of the peripheral circuit board, the second wiring structure connected to the peripheral circuit element, wherein the first wiring structure and the second wiring structure are bonded to each other ([0093]).
Regarding claim 20, Takahashi teaches the operating gate structure defines at least one of a reset transistor, a source/follower transistor, and a selection transistor (source/follower transistor [0063]).
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view or Takahashi229 as applied to claims 5 and 9 and further in view of Takahashi et. Al. (WO 2022110135 A1 hereinafter Takahashi135).
Regarding claim 6, Takahashi in view of Takahashi229 teaches the image sensor of claim 5.
Takahashi does not specify the transfer gate structure and the operating gate structure are at a same vertical level.
Takahashi135 discloses in Figs. 10 with associated text a device similar to that of Takahashi wherein a transfer gate structure 14 and an operating gate structure 30 are at a same vertical level (Fig. 10, page 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the transfer gate structure and the operating gate structure of Takahashi in view of Takahashi229 to be at a same vertical level similar to Takahashi135 because according to Takahashi135 in the method for forming such a structure since the semiconductor layer 4 and the semiconductor layer 44 are planarized, subsequent process steps may be easily carried out..
Regarding claim 14, Takahashi in view of Takahashi229 teaches the image sensor of claim 9.
Takahashi does not specify an upper surface of the operating gate structure and an upper surface of the transfer gate structure extend in a same plane (both are on a plane defined by for example 802 the claim wouldn’t necessarily require them to be in the same plane)..
Takahashi135 discloses in Figs. 10 with associated text an upper surface of an operating gate structure 30 and an upper surface of the transfer gate structure 14 extend in a same plane (Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the transfer gate structure and the operating gate structure of Takahashi in view of Takahashi229 extend in a same plane similar to Takahashi135 because according to Takahashi135 in the method for forming such a structure since the semiconductor layer 4 and the semiconductor layer 44 are planarized, subsequent process steps may be easily carried out..
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi as applied to claim 1 and further in view of Koyama et. Al. (US 20110108836 A1 hereinafter Koyama).
Regarding claim 8, Takahashi teaches the image sensor of claim 1.
Takahashi does not specify, wherein a thickness of the second semiconductor substrate is in a range from 10 nm to 30 nm.
Koyama discloses in Fig. 1 with associated text a semiconductor substrate 122 similar to that of Takahashi is in a range from 2 nm to 200 nm
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi as applied to claim 1 and further in view of Koyama et. Al. (US 20110108836 A1 hereinafter Koyama).
Regarding claim 10, Takahashi in view of Takahashi229 teaches the image sensor of claim 9.
Takahashi does not specify, wherein a thickness of the second semiconductor substrate is in a range from 10 nm to 30 nm
Koyama discloses in Fig. 1 with associated text a step between the second region of the first semiconductor substrate and the second semiconductor substrate is in a range from 10 nm to 50 nm (step is thickness of oxide layer 114 and so 5 nm to 30 nm).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), .
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Takahashi229 as applied to claim 12 and further in view of Oh et. Al. (US 20150243693 A1 hereinafter Oh).
Regarding claim 13, Takahashi teaches the image sensor of claim 12
Takahashi does not specify a width of the first portion of the gate electrode is greater than a width of the second portion of the gate electrode.
Oh discloses in Figs. 3A with associated text a width of a first portion 120a of a gate electrode 120 similar to that of Takahashi is greater than a width of the second portion 120b of the gate electrode (Fig. 3A, [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a gate electrode similar to Oh for the gate electrode of Takahashi because according to Oh by using such a structure a non-uniform electric field is prevented from occurring between the transfer gate electrode 120 and the floating diffusion region FD, image lag may be reduced [0047].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi as applied to claim 11 and further in view of Matsumoto et. Al. (US 20100026866 A1 hereinafter Matsumoto).
Regarding claim 16, Takahashi teaches the image sensor of claim 11, further comprising: an element separation pattern 16 defining a plurality of pixel regions in the first semiconductor substrate (Fig. 18), wherein the photoelectric conversion region is in each of the pixel regions (Fig. 18, [0062]).
Takahashi does not specify an upper surface of the element separation pattern protrudes from the first surface of the first semiconductor substrate.
Matsumoto discloses in Figs. 1 with associated text an upper surface of an element separation pattern 14 protrudes from a first surface of a first semiconductor substrate 11 similar to that of Takahashi (Fig. 1, [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an isolation structure with a protrusion similar to Matsumoto for the solation structure of Takahashi because according to Matsumoto the heights of protrusion of the first element isolation region 14 and the second element isolation region 15 are set at a low level of, for example, about 0 to 20 nm from a silicon surface [0111] so that such a protrusion in an isolation structure is suitable It would have been obvious to one of ordinary skill in the art, in view of the teachings of Takahashi and Matsumoto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to use protruding isolation structures of Matsumoto in Takahashi with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007)..
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AARON J GRAY/Examiner, Art Unit 2897