DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I directed at a semiconductor device and corresponding to claims 1-10 in the reply filed on 02/23/2026 is acknowledged.
Claims 11-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II directed at a method of fabricating a semiconductor device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/23/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/05/2022 was filed after the mailing date of the application on 12/05/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al, US 20230093897 A1 (Kim).
Regarding claim 1; Kim teaches a semiconductor device comprising:
a first nanosheet device (Kim: Annotated Fig (7) shared in this OA: First Nanosheet Device) including
a plurality of active semiconductor layers (135),
a first metal stack (First Metal Stack; 152-1; [0071]) wrapping around the active semiconductor layers (135), and
a first gate insulator layer (First Gate Insulator Layer;154-1) between the active semiconductor layers (135) and the first metal stack (First Metal Stack; 152-1; [0071]); and
and a second nanosheet device (Second Nanosheet Device) including
a second metal contact (Second Metal Contact; 152-1; [0071]),
the first metal stack (First Metal Stack; 152-1; [0071]) wrapping around the second metal contact (Second Metal Contact; 152-1; [0071]), and
a second gate insulator layer (Second Gate Insulator Layer;154-1) between the second metal contact (Second Metal Contact; 152-1; [0071]) and the first metal stack (First Metal Stack; 152-1; [0071]).
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Regarding claim 2; Kim teaches all the limitations of the semiconductor device of claim 1.
Further, Kim teaches wherein the first nanosheet device (Kim: Annotated Fig (7) shared in this OA: First Nanosheet Device) is a metal oxide semiconductor field effect transistor (MOSFET) device ([0005]-[0006]).
Regarding claim 3; Kim teaches all the limitations of the semiconductor device of claim 1.
Further, Kim teaches wherein the second nanosheet device (Second Nanosheet Device) is a metal-insulator-metal capacitor (MIMCAP) device (the structure of the Second Nanosheet Device is that of a metal (152-1) – insulator (154-1) – metal (152-1) capacitor).
Regarding claim 4; Kim teaches all the limitations of the semiconductor device of claim 1.
Further Kim teaches, further comprising a substrate (Kim: Annotated Fig (7) shared in this OA: 110), wherein the first nanosheet device (First Nanosheet Device) and the second nanosheet device (Second Nanosheet Device) are formed on the substrate (110), and wherein a portion of the first gate insulator (First Gate Insulator Layer) is formed between a bottom surface of the second nanosheet device (Second Nanosheet Device) and the substrate (110).
Regarding claim 6; Kim teaches all the limitations of the semiconductor device of claim 1.
Further, Kim teaches wherein the first gate insulator layer substrate (Kim: Annotated Fig (7) shared in this OA: First Gate Insulator Layer; 154-1; [0058]) comprises HfO2.
Regarding claim 7; Kim teaches all the limitations of the semiconductor device of claim 1.
Further, Kim teaches wherein the first metal stack (Kim: Annotated Fig (7) shared in this OA: First Metal Stack: 152-1) includes a high-κ metal gate (HKMG) layer ([0058]).
Regarding claim 8; Kim teaches all the limitations of the semiconductor device of claim 1.
Further, Kim teaches wherein the first nanosheet device (Kim: Annotated Fig (7) shared in this OA: First Nanosheet Device) includes a source/drain (S/D) epitaxial layer (141) in contact with the active semiconductor layers (135).
Regarding claim 9; Kim teaches all the limitations of the semiconductor device of claim 1.
Further, wherein the second nanosheet device (Kim: Annotated Fig (7) shared in this OA: Second Nanosheet Device) further includes a gate contact (Gate Contact; 152-1) that is a bottom electrode, and wherein the second metal contact (Second Metal Contact) is a top electrode.
Regarding claim 10; Kim teaches all the limitations of the semiconductor device of claim 9.
Further, Kim teaches wherein the first nanosheet device (Kim: Annotated Fig (7) shared in this OA: First Nanosheet Device) is a MOSFET ([0005]-[0006]) device and the second nanosheet device (Second Nanosheet Device) is a MIMCAP device (the structure of the Second Nanosheet Device is that of a metal (152-1) – insulator (154-1) – metal (152-1) capacitor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20230093897 A1 (Kim) in view of Chiu et al, US 20220285528 A1 (Chiu)
Regarding claim 5; Kim teaches all the limitations of the semiconductor device of claim 1.
However, Kim does not teach wherein the first gate insulator layer includes a different material than the second gate insulator layer.
Chiu teaches wherein the first gate insulator layer (Chiu: Fig (17A): 240) includes a different material ([0062]) than the second gate insulator layer (242).
Kim and Chiu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kim by making the first gate insulator layer and the second gate insulator layer out of different materials as disclosed by Chiu to achieve the predictable result of improving the insulation of the gate leading to a more reliable device.
Conclusion
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/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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