CTNF 18/062,029 CTNF 99490 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/06/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant's election with traverse of Species 3 (claims 1-20) in the reply filed on 03/10/2026 is acknowledged. The traversal is on the ground(s) that the figure groupings identified above do not disclose different species having mutually exclusive characteristics. Applicant’s arguments have been fully considered and are persuasive. The restriction requirement of 01/15/2026 is withdrawn. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-05 AIA Claim s 3, 10, and 16 recites the limitation " the length " in line 1 . There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-15 AIA Claim s 1-2, 5-9, and 12-13 are rejected under 35 U.S.C. 102( a)(1)(a)(2 ) as being anticipated by Hsieh et al. (US Publication 20180174904) . Regarding independent claim 1 , teaches a stacked transistor structure (fig. 25, 2) comprising: a top source drain region (74) above a bottom source drain region (42), wherein a width of the bottom source drain region is greater than a width of the top source drain region (fig. 25); a bottom contact structure (60) directly above and in electrical contact with the bottom source drain region (fig. 25); a metal silicide (52) between the bottom source drain region and the bottom contact structure, the metal silicide having a width larger than a width of the bottom contact structure (fig. 25); a replacement spacer (56) surrounding the bottom contact structure; and a top gate spacer (40) separating the replacement spacer from a gate conductor (30). Regarding independent claim 8 , Hsieh teaches a stacked transistor structure (fig. 25, 2) comprising: a top source drain region (74) above a bottom source drain region (42), wherein a width of the bottom source drain region is greater than a width of the top source drain region (fig. 25); a bottom contact structure (60) directly above and in electrical contact with the bottom source drain region (fig. 25); a metal silicide (52) between the bottom source drain region and the bottom contact structure, the metal silicide having a lateral width larger than a lateral width of the bottom contact structure (fig. 25); a replacement spacer (56) surrounding the bottom contact structure; and a top gate spacer (40) separating the replacement spacer from a gate conductor (30), wherein the replacement spacer is made from a different material than the top gate spacer (paragraph 0018, “spacer layer 54 may be formed of a dielectric material such as SiN, SiCN, SiC, AlON, HfO.sub.x, etc.” of which replacement spacer 56 is made of, see paragraph 0019, and paragraph 0016, “ILD0 40 may be formed of an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like”). Regarding dependent claims 2 and 9 , Hsieh teaches the stacked transistor structure according to claim 1/claim 8, further comprising: inner spacers (fig. 25, 38) separating the bottom source drain region from the gate conductor, PNG media_image1.png 520 686 media_image1.png Greyscale wherein at least one of the inner spacers nearest to an uppermost surface of the bottom source drain region comprises a first top surface (see figure below) above a second top surface (see figure below), the second top surface being substantially flush with the uppermost surface of the bottom source drain region (see figure below). Regarding dependent claims 5 and 12 , Hsieh teaches the stacked transistor structure according to claim 1/claim 8, wherein the width of the bottom source drain region and the width of the top source drain are measured in a direction parallel to the gate conductor (fig. 25, width is measured parallel to gate conductor 30 in opposite direction of line 21). Regarding dependent claims 6 and 13 , Hsieh teaches the stacked transistor structure according to claim 1, wherein a length of the bottom source drain region is greater than a length of the bottom contact structure, wherein length is measured perpendicular to the gate conductor (fig. 25, length is measured perpendicular to gate conductor 30 in direction of line 21). Regarding dependent claim 7 , Hsieh teaches the stacked transistor structure according to claim 1, wherein the bottom contact structure is self-aligned to the replacement spacer (fig. 25) . . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3-4, 10-11, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Merchant et al. (US Publication 20220301936) . Regarding dependent claims 3 and 10 , Hsieh teaches the stacked transistor structure according to claim 1. Hsieh does not teach wherein the length of the metal silicide is substantially equal to a length of the bottom source drain region. Merchant teaches wherein the length of the metal silicide (fig. 24, 38) is substantially equal to a length of the bottom source drain region (36A, length is taken in horizontal direction). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked transistor structure of Hsieh and the lengths of Merchant in order to cover at least the etched epitaxial source/drain regions (Merchant paragraph 0047). Regarding dependent claims 4 and 11 , Hsieh teaches the stacked transistor structure according to claim 1, [wherein the replacement spacer directly contacts] and an uppermost surface of the metal silicide (fig. 25). Hsieh does not teach wherein the replacement spacer directly contacts a sidewall of the metal silicide. Merchant teaches wherein the replacement spacer (fig. 24, 55) directly contacts a sidewall of the metal silicide. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked transistor structure of Hsieh and the replacement spacer placement of Merchant in order to fill the gaps between the silicide layers (Merchant paragraphs 0059-0060). Regarding independent claim 14 , Hsieh teaches a stacked transistor (fig. 25, 2) structure comprising: a top source drain region (74) above a bottom source drain region (42), wherein a width of the bottom source drain region is greater than a width of the top source drain region (fig. 25); a bottom contact structure (60) directly above and in electrical contact with the bottom source drain region (fig. 25); a metal silicide (52) between the bottom source drain region and the bottom contact structure, the metal silicide having a lateral width larger than a lateral width of the bottom contact structure (fig. 25); a replacement spacer (56) surrounding all sides of the bottom contact structure (paragraph 0019); and a top gate spacer (40) separating the replacement spacer from a gate conductor (30). Hsieh does not teach a top stack of nanosheet channels above a bottom stack of nanosheet channels, wherein a width of the bottom stack of nanosheet channels is greater than a width of the top stack of nanosheet channels. PNG media_image2.png 364 614 media_image2.png Greyscale Merchant teaches a top stack of nanosheet channels (see figure below) above a bottom stack of nanosheet channels (see figure below). Hsieh in view of Merchant does not explicitly teach wherein a width of the bottom stack of nanosheet channels is greater than a width of the top stack of nanosheet channels, however, Merchant figure 25 discloses a length of the bottom stack of nanosheet channels (DG1) to be greater than a length of the top stack of nanosheet channels (DG2). It would have been an obvious matter of design choice to change the width of the nanosheet channel stacks such that a width of the bottom stack is greater than a width of the top stack in order to reduce complexity and cost (Merchant paragraph 0029), since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Regarding dependent claim 15 , Hsieh further teaches the stacked transistor structure according to claim 14, further comprising: inner spacers (fig. 25, 38) separating the bottom source drain region from the gate conductor, wherein at least one of the inner spacer nearest to an uppermost surface of the bottom source drain region comprises a first top surface (see marked figure corresponding to claims 2 and 9) above a second top surface (see marked figure corresponding to claims 2 and 9), the second top surface being substantially flush with the uppermost surface of the bottom source drain region (see marked figure corresponding to claims 2 and 9). Regarding dependent claim 16 , Merchant further teaches the stacked transistor structure according to claim 14, wherein the length of the metal silicide (fig. 24, 38) is substantially equal to a length of the bottom source drain region (36A, length is taken in horizontal direction). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked transistor structure of Hsieh and the lengths of Merchant per the reason(s) stated above in claim 14. Regarding dependent claim 17 , Hsieh further teaches the stacked transistor structure according to claim 14, [wherein the replacement spacer directly contacts] and an uppermost surface of the metal silicide (fig. 25). Merchant further teaches wherein the replacement spacer (fig. 24, 55) directly contacts a sidewall of the metal silicide. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked transistor structure of Hsieh and the replacement spacer placement of Merchant per the reason(s) stated above in claim 14. Regarding dependent claim 18 , Hsieh further teaches the stacked transistor structure according to claim 14, wherein the width of the bottom source drain region and the width of the top source drain are measured in a direction parallel to the gate conductor (fig. 25, width is measured parallel to gate conductor 30 in opposite direction of line 21). Regarding dependent claim 19 , Hsieh further teaches the stacked transistor structure according to claim 14, wherein a length of the bottom source drain region is greater than a length of the bottom contact structure, wherein length is measured perpendicular to the gate conductor (fig. 25, length is measured perpendicular to gate conductor 30 in direction of line 21). Regarding dependent claim 20 , Merchant further teaches the stacked transistor structure according to claim 14, wherein the top source drain region (fig. 25, 39) directly contacts ends of the top stack of nanosheet channels and the bottom source drain region (36A) directly contact ends of the bottom stack of nanosheet channels (fig. 25, see also marked figure corresponding to claim 14). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked transistor structure of Hsieh and the top/bottom source drain region placements of Merchant per the reason(s) stated above in claim 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRACE CHA/Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/062,029 Page 2 Art Unit: 2897 Application/Control Number: 18/062,029 Page 4 Art Unit: 2897 Application/Control Number: 18/062,029 Page 5 Art Unit: 2897 Application/Control Number: 18/062,029 Page 6 Art Unit: 2897 Application/Control Number: 18/062,029 Page 7 Art Unit: 2897 Application/Control Number: 18/062,029 Page 8 Art Unit: 2897 Application/Control Number: 18/062,029 Page 9 Art Unit: 2897 Application/Control Number: 18/062,029 Page 10 Art Unit: 2897 Application/Control Number: 18/062,029 Page 11 Art Unit: 2897 Application/Control Number: 18/062,029 Page 12 Art Unit: 2897
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