DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Drawings 3
III. Claim Objections 4
IV. Claim Rejections - 35 USC § 112 5
A. Claims 2-10, 12, 13, 19, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 5
V. Claim Rejections - 35 USC § 102 7
A. Claims 1-9, 11, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0373242 (“Hiblot”). 8
VI. Allowable Subject Matter 13
Conclusion 15
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “second backside power connecting line” recited in claims 5, 6, 7, 9, 10, 14, 15, 17, 18, and 20, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Note that the limitation, “second backside power connecting line” is only recited in the claims but is nowhere recited in the specification nor given a reference character in any of the figures. Instead, in the specification, the element designated “300” in Fig. 3B is the “second backside power line 300”, and the element designated “305” in Fig. 3B is the “third backside power line 305”. Also, the element designated “205” in Fig. 3B is the “first backside power connecting line 205”, and the element designated “110” is the “first backside power line 110”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
III. Claim Objections
Claims 1, 8, 9, 13, 15-17, and 19 are objected to because of the following informalities:
(1) In the last line of claim 1, replace “either footer gate transistor and the header gate transistor” with “either of the footer gate transistor and the header gate transistor” or “either the footer gate transistor or the header gate transistor” for clarity.
(2) In line 4 of claim 8, replace “connected” with “is connected to” for clarity.
(3) In line 4 of claim 9, replace “connected” with “is connected to” for clarity.
(4) In the last line of claim 13, replace “are” with “is” for correct subject-verb agreement.
(5) In the last line of claim 15, replace “are” with “is” for correct subject-verb agreement.
(6) In line 4 of claim 16, replace “connected” with “is connected to” for clarity.
(7) In line 4 of claim 17, replace “connected” with “is connected to” for clarity.
(8) In the last two lines of claim 19, replace “either footer gate transistor and the header gate transistor” with “either of the footer gate transistor and the header gate transistor” or “either the footer gate transistor or the header gate transistor” for clarity.
Appropriate correction is required.
IV. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 2-10, 12, 13, 19, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 reads, in pertinent part,
2. The microelectronic architecture of claim 1, wherein the header gate transistor further comprises:
a first backside power line connected to the header gate transistor,
It is unclear how the “first backside power line” can be part of the header gate transistor, while simultaneously being “connected to” the header gate transistor.
As best understood by Examiner, the first backside power line, while connected to the header gate transistor, is a separate entity from the header gate transistor and therefore not part of the header gate transistor. To the extent that this is what the Instant Inventors intended, then the rejection could be overcome by replacing “wherein the header gate transistor further comprises” with just “further comprising”.
Claims 3-10 are rejected for including the same indefinite feature by depending from claim 2 either directly or indirectly.
Claim 5 reads, in pertinent part,
5. The microelectronic architecture of claim 2, wherein the footer gate transistor further comprises:
a second backside power line connected to the footer gate transistor,
It is unclear how the “second backside power line” can be part of the footer gate transistor, while simultaneously being “connected to” the footer gate transistor.
As best understood by Examiner, the first backside power line, while connected to the header gate transistor, is a separate entity from the header gate transistor and therefore not part of the header gate transistor. To the extent that this is what the Instant Inventors intended, then the rejection could be overcome by replacing “wherein the footer gate transistor further comprises” with just “further comprising”.
Claims 6-10 are rejected for including the same indefinite feature by depending from claim 5 either directly or indirectly.
Claim 12 reads, in pertinent part,
12. The microelectronic architecture of claim 11, wherein the header gate transistor further comprises:
a first frontside power line connected to the header gate transistor,
It is unclear how the “first frontside power line” can be part of the header gate transistor, while simultaneously being “connected to” the header gate transistor.
As best understood by Examiner, the first frontside power line, while connected to the header gate transistor, is a separate entity from the header gate transistor and therefore not part of the header gate transistor. To the extent that this is what the Instant Inventors intended, then the rejection could be overcome by replacing “wherein the header gate transistor further comprises” with just “further comprising”.
Claim 13 is rejected for including the same indefinite feature by depending from claim 12.
Claim 19 recites the limitation,
a header gate transistor and a footer gate transistor located a side of the logic device, respectively,
The term “respectively” results the limitation having more than one interpretation. It may be interpreted to mean Applicant claiming that the header and footer gate transistors are on two different sides of the logic device or that both are on the same side of the logic device, i.e. perhaps on the front side and back side of the substrate but on the same side of the logic device.
For the purposes of examination, the claim will be interpreted as broadly as allowed by the claim language.
Claim 20 is rejected for including the same indefinite feature by depending from claim 19.
Claim 20 recites the limitations “the second backside power line” in line 10 and “the second backside power connecting line” in line 11. There is insufficient antecedent basis in the claim for each of these limitations.
V. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-9, 11, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0373242 (“Hiblot”).
With regard to claims 1-9, Hiblot discloses, generally in Fig. 4,
1. A microelectronic architecture comprising:
[1] a logic device 10 [¶¶ 2-4, 61];
[2a] a header gate transistor 101 located adjacent to a first side [right side in Fig. 4] of the logic device 10,
[2b] wherein the header gate transistor 101 has a parallel orientation to the logic device 10 [in the plane of the substrate 1(=1a/1b) as shown in Fig. 4],
[2c] wherein the header gate transistor 101 is connected to a VSS source or a VDD source; and
[3a] a footer gate transistor 100 [¶ 68] located adjacent to a second side [left side in Fig. 4] of the logic device 10,
[3b] wherein the footer gate transistor 100 has a parallel orientation to the logic device 10 [in the plane of the substrate 1(=1a/1b) as shown in Fig. 4],
[4] wherein the first side [right side] and the second side [left side] are opposite sides of the logic device 10,
[3c] wherein the footer gate transistor 101 is connected to a VSS source or a VDD source,
[5] wherein the footer gate transistor 100 is connected to a different source [i.e. Vss] than the header gate transistor [i.e. Vdd],
[6] wherein the logic device 10 is connected to the VSS source and the VDD source through either footer gate transistor 100 and the header gate transistor 101 [as shown in Fig. 4].
2. The microelectronic architecture of claim 1, wherein the header gate transistor 100 further comprises:
[1] a first backside power line Vdd connected [by 25/26/27] to the header gate transistor 101,
[2] wherein the first backside power line Vdd is connected to the VSS source or the VDD source; and
[3] a first backside power connecting line 31 [labeled in Fig. 3 but not in Fig. 4] that connects the header gate transistor 101 to the logic device 10 [¶ 66].
3. The microelectronic architecture of claim 2, wherein the first backside power line Vdd and the first backside power connecting line 31 are located on a backside [bottom side in Fig. 4] of the header gate transistor 101.
4. The microelectronic architecture of claim 3,
[1] wherein the first backside power line Vdd is located at a first level,
[2] wherein the first backside power connecting line 31 is located at a second level, and
[3] wherein the first level and the second level are different [as shown in Figs. 3 and 4].
5. The microelectronic architecture of claim 2, wherein the footer gate transistor 100 further comprises:
[1] a second backside power line Vss connected to the footer gate transistor 100,
[2] wherein the second backside power line Vss is connected to the VSS source or the VDD source; and
[3] a second backside power connecting line 31 [labeled in Fig. 2 but not in Fig. 4 (¶ 66)] and that connects the footer gate transistor 100 to the logic device 10.
6. The microelectronic architecture of claim 5, wherein the second backside power line Vss and the second backside power connecting line 31 are located on the backside [bottom side in Fig. 4] of the footer gate transistor 100.
7. The microelectronic architecture of claim 6,
[1] wherein the second backside power line Vss is located at a first level,
[2] wherein the second backside power connecting line 31 is located at a second level, and
[3] wherein the first level and the second level are different [as shown in Figs. 2 and 4].
8. The microelectronic architecture of claim 5, wherein the header gate transistor 101 further comprises:
[1] a first header source/drain epi 17 and a second header source/drain epi 16 [¶¶ 74-75, 80; Figs. 9B];
[2] wherein the first backside power line Vdd [is] connected [by 25/26/27] [to] a backside surface [bottom side in Fig. 4] of the first header source/drain epi 17,
[3] wherein the first backside power connecting line 31 is connected to a backside surface of the second header source/drain epi 16.
9. The microelectronic architecture of claim 8, wherein the footer gate transistor 100 further comprises:
[1] a first footer source/drain epi 16 and a second footer source/drain epi 17 [labeled in Fig. 2 but not in Fig. 4];
[2] wherein the second backside power line Vss [is] connected [by 25/26/27] [to] a backside surface [bottom side in Fig. 4] of the first footer source/drain epi 16,
[3] wherein the second backside power connecting line 31 is connected to a backside surface of the second footer source/drain epi 17.
With regard to feature [1] of each of claims 8 and 9, the layer 52 is formed by epitaxial growth and then implanted to form the source and drain regions 16, 17; therefore, the source/drain regions 16, 17 are source/drain epi’s, as required by claims 8 and 9.
With regard to claim 11, Hiblot discloses, generally in Fig. 4,
11. A microelectronic architecture comprising:
[1] a logic device 10;
[2a] a header gate transistor 101 located adjacent to a first side [right side in Fig. 4] of the logic device 10,
[2b] wherein the header gate transistor 101 has a parallel orientation to the logic device 10 [in the plane of the substrate 1(=1a/1b) as shown in Fig. 4],
[2c] wherein the header gate transistor 101 is connected to a VSS source or a VDD source; and,
[2d] wherein the VSS source or the VDD source Vdd is [at least electrically] connected to the frontside of the header gate transistor 101; and
[3a] a footer gate transistor 100 located adjacent to a second side [left side in Fig. 4] of the logic device 10,
[3b] wherein the footer gate transistor 100 has parallel orientation to the logic device 10 [in the plane of the substrate 1(=1a/1b) as shown in Fig. 4],
[4] wherein the first side [right side] and the second side [left side] are opposite sides of the logic device 10,
[3c] wherein the footer gate transistor 100 is connected to a VSS source or a VDD source,
[5] wherein the footer gate transistor 100 is connected to a different source Vss than the header gate transistor 101 [i.e. Vdd],
[6] wherein the logic device 10 is connected to the VSS source Vss and the VDD source Vdd through either footer gate transistor 100 and the header gate transistor 101,
[3d] wherein the VSS source Vss or the VDD source Vdd is [at least electrically] connected to the frontside of the footer gate transistor 100.
With regard to claim 19, Hiblot discloses, generally in Fig. 4,
19. A microelectronic architecture comprising:
[1] a logic device 10;
[2] a header gate transistor 101 and a footer gate transistor 100 located a side of the logic device 10 [see below], respectively,
[3] wherein the backside [bottom side in Fig. 4] of the header gate transistor 101 and the backside [bottom side in Fig. 4] of the footer gate transistor 100 is each connected to either a VSS source Vss or a VDD source Vdd,
[4] wherein the backside of the logic device is [at least electrically] connected to the VSS source Vss and the VDD source Vdd through either footer gate transistor 100 and the header gate transistor 101.
With regard to feature [2] of claim 19, bearing in mind the rejection of claim 19 under 35 USC 112(b), Hiblot discloses both “a side of the logic device, respectively” being interpreted as the bottom side as a same side of the logic device 10 or may be the right and left sides of the logic device 10, respectively, if Applicant intended opposite sides of the logic device 10.
With regard to claim 20, Hiblot further discloses,
20. The microelectronic architecture of claim 19, further comprising:
[1a] wherein the header gate transistor 101 further comprises:
[1b] a first backside power line Vdd connected to the header gate transistor 101,
[1c] wherein the first backside power line Vdd is connected to the VSS source or the VDD source; and
[2] a first backside power connecting line 31 that connects the header gate transistor 101 to the logic device 10 [as shown in Figs. 3-4];
[3] wherein the footer gate transistor 100 further comprises: a first footer source/drain epi 16 and a second footer source/drain epi 17;
[4] wherein the second backside power line Vss is connected [to] a backside surface of the first footer source/drain epi 16 [Figs. 2, 4],
[5] wherein the second backside power connecting line 31 is connected to a backside surface of the second footer source/drain epi 17 [Figs. 2, 4];
[6] wherein the second backside power line Vss is located at a first level,
[7] wherein the second backside power connecting line 31 is located at a second level, and
[8] wherein the first level and the second level are different [as shown in Figs. 2 and 4].
VI. Allowable Subject Matter
Claims 10 and 12-18 (pending overcoming the rejections under 35 USC 112(b) for claims 10, 12, and 13) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 reads,
10. The microelectronic architecture or claim 8, wherein the logic device further comprises:
[1] a first logic source/drain epi and a second logic source/drain epi;
[2] wherein the first backside power connecting line is connected to a backside surface of the first logic source/drain epi, and
[3] wherein the second backside power connecting line is connected to a backside surface of the second logic source/drain epi.
The prior art does not reasonably teach or suggest—in the context of the claims—the features recited in claim 10.
Claim 12 reads,
12. The microelectronic architecture of claim 11, wherein the header gate transistor further comprises:
[1] a first frontside power line connected to the header gate transistor,
[2] wherein the first frontside power line is connected to the VSS source or the VDD source; and
[3] a first backside power connecting line that connects the header gate transistor to the logic device.
The prior art does not reasonably teach or suggest—in the context of the claims—the features recited in claim 12.
Claim 13 would be allowable at least for including the same allowable limitations by depending from claim 12.
Claim 14 reads,
14. The microelectronic architecture of claim 11, wherein the footer gate transistor further comprises:
[1] a second frontside power line connected to the footer gate transistor,
[2] wherein the second frontside power line is connected to the VSS source or the VDD source; and
[3] a second backside power connecting line that connects the footer gate transistor to the logic device.
The prior art does not reasonably teach or suggest—in the context of the claims—both of the frontside and backside power lines recited in claim 14.
Claims 15-18 would be allowable at least for including the same allowable limitations by depending from claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814