DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 17 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/04/2026.
Applicant’s election without traverse of Species Device Embodiment 6 in the reply filed on 03/04/2026 is acknowledged.
Claim 13, reads on unelected Device Embodiment 1, device of embodiment 1 has a source/drain region (640) of a T-Shape that extends over first epitaxial layer (550). And first epitaxial layer (550) extends beyond the sidewalls of the sidewalls of the gate spacer as shown in Fig 6A. Therefore claim 13 is withdrawn from further consideration, as being drawn to a nonelected species.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “dielectric inner spacer” as cited in Claim 1 must be shown or the feature(s) canceled from the claim(s). Examiner notes that embodiments using the epitaxial material 550 between channels are shown in the figures but no figure exists where a dielectric inner spacer is shown. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9,10,11 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the plurality of channel layers" and “the source/drain region” in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the plurality of channel layers" in the second line and third line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “the source/drain region” in the third line of the claim. It is unclear if the limitation “the source/drain region” refers to the “a first source/drain region” of the “a second source/drain region” as recited in lines four and eight of Claim 1.
Claim 12 recites the limitation “the metal gate stack" in the second line of the claim and “the plurality of channel layers” in the third line of the claim. There is insufficient antecedent basis for the limitation “the plurality of channel layers” in the claim. It is also unclear if the limitation “the metal gate stack” refers to “the first metal gate stack” of the fourth line of Claim 1 of “the second metal gate stack” as referenced in the eighth line of Claim 1.
Examiner notes that the language of Claims 9-12 is consistent with the language of Claim 8, therefore, for purposes of examination, Examiner interprets Claims 9-12 as dependent on Claim 8 instead of Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-9, 12, 14-16 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by More et al. (US 2022/0392894 A1, hereinafter More ‘894).
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With respect to Claim 1 More ‘894 discloses a semiconductor structure (Fig 1-4C), comprising:
a first gate-all-around device (device of GAA 100 in region 106B, Fig 2H, Para [0013], hereinafter FGAA) disposed on a first region (106B, Fig 2H, Para [0013]) of a substrate (105, Fig 2H, Para [0013]), the first gate-all-around device (FGAA) comprising a first metal gate stack (160C, Fig 2H, Para [0057]) surrounding a first channel layer (120’ in stack 160C, Fig 2H, Para [0058]), the first metal gate stack (160C) being separated from a first source/drain region (third 150 region from left, Fig 2H, Para [0030]) by a dielectric inner spacer (148’, Fig 2F, Para [0028]) disposed on opposite sides (disclosed in Fig 2F) of the first metal gate stack (160C); and
a second gate-all-around device (device of GAA 100 in region 106A, Fig 2H, Para [0013], hereinafter SGAA) disposed on a second region (106A, Fig 2H, Para [0013]) of the substrate (105), the second gate-all-around device (SGAA) comprising a second metal gate stack (160A, Fig 2H, Para [0057]) surrounding a second channel layer (120’ in stack 160A, Fig 2H, Para [0058]), the second metal gate stack (160A) being separated from a second source/drain region (first 150 from left as shown in Fig 2H, Para [0030]) by an epitaxial layer (154A, Fig 2H, Para [0030]) disposed on opposite sides (disclosed in Fig 2F) of the second metal gate stack (160A).
With respect to Claim 2 More ‘894 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 further discloses wherein the first gate-all-around device (FGAA) is an n-FET device (disclosed in Para [0013]), and the second gate-all-around device (SGAA) is a p-FET device (disclosed in Para [0013]).
With respect to Claim 3 More ‘894 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 further discloses wherein each of the first metal gate stack (160C) and the second metal gate stack (160A) further comprises a gate dielectric material (Para [0060] discloses 160A and 160C further comprises a gate dielectric material).
With respect to Claim 4 More ‘894 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 further discloses wherein the second gate-all-around device (SGAA) further comprises:
a second sidewall gate spacer (132, Fig 2H, Para [0019]) located along opposite sidewalls (left and right sides of 164A) of a portion (164A, Fig 2H, Para [0060]) of the second metal gate stack (160A) disposed above the second channel layer (120’ in stack 160A), wherein a thickness (thickness of 132 as shown in annotated Fig 2H of More ‘894) of the second sidewall gate spacer (132) defines an extension region (extension region of 132 shown in annotated Fig 2H of More ‘894) for the second gate-all-around device (SGAA); and
a diffusion region (Para [0052] discloses region under extension region of 132 as a diffusion region, hereinafter DR) located within the extension region (annotated Fig 2H of More ‘894 discloses DR is located within extension region of 132), the diffusion region (DR) including an outer portion (outer portion of 120’ in stack 160A) of the second channel layer (120’ in stack 160A) and an outer portion (outer portion of 154A) of the epitaxial layer (154A)(annotated Fig 2H of More ‘894 discloses diffusion region includes outer portion of 120’ and outer portion of 154A).
With respect to Claim 5 More ‘894 discloses all limitations of the semiconductor structure of claim 4, and More ‘894 further discloses wherein the diffusion region (DR) is located at an interface between the second source/drain region (first 150 from left as shown in Fig 2H), the second channel layer (120’ in stack 160A) and the epitaxial layer (154A)(annotated Fig 2H of More ‘894 discloses DR is located at interface of second source/drain, second channel and epitaxial layer), the diffusion region (DR) having a U-shaped perimeter (U-Shape of DR disclosed in annotated Fig 2H) that surrounds (DR surrounding first 150 from left as shown in annotated Fig 2H) the second source/drain region (first 150 from left as shown in Fig 2H), the diffusion region (DR) including diffused dopant atoms from the second source/drain region (first 150 from left as shown in Fig 2H)(Annotated Fig 2H of More ‘894 discloses regions of first 150 from left as shown in Fig 2H is present in the DR, therefore the diffused dopants in 150 (Para [0030] discloses 156A, part of 150, as doped) are part of DR).
With respect to Claim 8 More ‘894 discloses a semiconductor structure (100 in region 106A) (Fig 1-4C), comprising:
a plurality of channel layers (plurality of 120’ in stack 160A, Fig 2H, Para [0058]) vertically stacked (disclosed in Fig 2H) over a substrate (105, Fig 2H, Para [0013]);
a metal gate stack (160A, Fig 2H, Para [0057]) including a gate dielectric material (162A, Fig 2H, Para [0060]), the metal gate stack (160A) being located between (disclosed in Fig 2H) the plurality of channel layers (plurality of 120’ in stack 160A);
an epitaxial layer (154A, Fig 2H, Para [0030]) disposed on opposite sides (disclosed in Fig 2H) of the metal gate stack (160A);
a source/drain region (first 150 from left as shown in Fig. 2H, Para [0030]) adjacent to (disclosed in Fig 2H) the plurality of channel layers (plurality of 120’ in stack 160A) and the epitaxial layer (154A); and
a diffusion region (Para [0052] discloses region under extension region of 132 as a diffusion region, hereinafter DR) located at an interface between the source/drain region (first 150 from left as shown in Fig 2H), the plurality of channel layers (plurality of 120’ in stack 160A) and the epitaxial layer (154A) (annotated Fig 2H of More ‘894 discloses DR is located at interface of source/drain region, plurality of channel layers and epitaxial layer), the diffusion region (DR) having a U-shaped perimeter (U-Shape of DR disclosed in annotated Fig 2H) that surrounds the source/drain region (first 150 from left as shown in Fig 2H) (DR surrounding first 150 from left as shown in annotated Fig 2H), the diffusion region (DR) including diffused dopant atoms from the source/drain region (first 150 from left as shown in Fig 2H)(Annotated Fig 2H of More ‘894 discloses regions of first 150 from left as shown in Fig 2H is present in the DR, therefore the diffused dopants in 150 (Para [0030] discloses 156A, part of 150, as doped) are part of DR).
With respect to Claim 9 More ‘894 discloses all limitations of the semiconductor structure of claim 1 (Note Examiner’s above interpretation of Claim 9 being dependent on claim 8), and More ‘894 further discloses wherein the metal gate stack (160A) surrounds the plurality of channel layers (plurality of 120’ in stack 160A) and is separated from the source/drain region (first 150 from left as shown in Fig 2H) by the epitaxial layer (154A)(Fig 2H discloses 160A surrounds the second channel layer and is separated from the second source/drain region by 154A).
With respect to Claim 12 More ‘894 discloses all limitations of the semiconductor structure of claim 1 (Note Examiner’s above interpretation of Claim 12 being dependent on claim 8), and More ‘894 discloses further comprising:
a sidewall gate spacer (132, Fig 2H, Para [0019]) located along opposite sidewalls (left and right of 164A) of a portion (164A, Fig 2H, Para [0060]) of the metal gate stack (160A) disposed above an uppermost channel layer (top layer 120’ in stack 160A as shown in Fig 2H) of the plurality of channel layers (plurality of 120’ in stack 160A).
With respect to Claim 14 More ‘894 discloses all limitations of the semiconductor structure of claim 12, and More ‘894 further discloses wherein outer sidewalls (outer sidewalls of upper and lower regions of 154A as shown in annotated Fig 2H of More ‘894) of the epitaxial layer (154A) are vertically aligned with outer sidewalls (outer sidewalls of plurality of 120’ in stack 160A) of the plurality of channel layers (plurality of 120’ in stack 160A) and outer sidewalls (outer sidewalls of 132 as shown in annotated Fig 2H of More ‘894) of the sidewall gate spacer (132)(annotated Fig 2H of More ‘894 discloses outer sidewalls of 154A and outer sidewalls of plurality of 120’ in stack of 160A are vertically aligned with the sidewalls of gate spacer 132).
With respect to Claim 15 More ‘894 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 further discloses wherein the diffusion region (DR) further comprises dopant atoms diffused within an outer portion (outer portion of each of plurality of 120’ in stack 160A) of each of the plurality of channel layers (plurality of 120’ in stack 160A) and within an outer portion (outer portion of 154A) of the epitaxial layer (154A)(Para [0047] discloses 120’ doped with Ge and Para 154A doped with boron. Therefore DR comprises dopants in the portions of 120’ and 154A in the DR region as described in claim 8).
With respect to Claim 16 More ‘894 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 further discloses wherein the diffusion region (DR) further comprises dopant atoms (Para [0030] discloses 154A comprises dopants) diffused within an uppermost portion (154A in 105 as shown in Fig 2H) of the substrate (105) located below the source/drain region (first 150 from left as shown in Fig 2H).
With respect to Claim 19 More ‘894 discloses all limitations of the semiconductor structure of claim 12, and More ‘894 discloses further comprising:
a source/drain contact (source/drain contacts, not shown in figures but disclosed in Para [0044], hereinafter SDC) in contact with (Para [0044] discloses MD contacts regions 150) an uppermost surface (158A, Fig 2H, Para [0044])) of the source/drain region (first 150 from left as shown in Fig 2H), the source/drain contact (SDC) being separated from the metal gate stack (160A) by the sidewall gate spacer (132)(Para [0044] discloses SDC formed over 158A which is separated from 160A by the sidewall gate spacer); and
a portion of the substrate (105P’, Fig 2H, Para [0021]) below the plurality of channel layers (plurality of 120’ in stack 160A) being located between shallow trench isolation regions (152, Fig 2H, Para [0030]).
With respect to Claim 20 More ‘894 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 further discloses wherein the plurality of channel layers (plurality of 120’ in stack 160A) comprises at least one of a nanosheet, a nanowire, and a nano-ellipse (Para [0012] disclose channel layers as nanosheets).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over More ‘894 in view of Chang et al. (US 2014/0151639 A1, hereinafter Chang ‘639), in view of the following arguments.
With respect to Claim 6 More ‘894 discloses all limitations of the semiconductor structure of claim 1, but More ‘894 fails to explicitly disclose wherein the second source/drain region and the epitaxial layer generate at least one of a compressive strain and a tensile strain on the second channel layer depending on a type of material selected to form the second source/drain region and the epitaxial layer.
Nevertheless, in a related endeavor (Fig 1-11F or Chang ‘639), Chang ‘639 teaches wherein the second source/drain region (120D/130D, Fig 11B, Para [0127]) and the epitaxial layer (layer of 120D/130D nearest channel 120N) generate at least one of a compressive strain and a tensile strain on the second channel layer (120N, Fig 11B, Para 0127]) depending on a type of material selected to form the second source/drain region and the epitaxial layer. (Para [0122] of Chang ‘639 teaches the lattice mismatch between silicon and germanium can achieve a compressive or tensile strain.)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chang ‘639’s teaching of using the lattice mismatch between the silicon and germanium regions of the source/drain region and epitaxial layer and the channel layer to generate a compressive strain or tensile strain into More ‘894’s device. More ‘894 teaches a transistor device with source/drain and epitaxial layers and nanosheet channel layers of silicon and silicon germanium. Chang ‘639 teaches a transistor device using nanosheet channel layers of silicon and silicon germanium. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, one of ordinary skill in the art would recognize that modulating the strain in transistor can achieve the well-known advantage of improving electron mobility.
As incorporated, the use of the differing lattice structures of silicon and germanium to achieve strain, as taught by Chang ‘639 would be used to achieve a strain between the silicon and germanium materials of the second source/drain region (first 150 from left as shown in Fig 2H) and the epitaxial layer (154a) and the second channel layer (120’ in stack 160A) of More ‘894 so that one of a compressive strain and a tensile strain exists on the second channel layer depending on a type of material selected to form the second source/drain region and the epitaxial layer.
With respect to Claim 10 More ‘894 discloses all limitations of the semiconductor structure of claim 1 (Note Examiner’s above interpretation of Claim 10 being dependent on claim 8), but More ‘894 fails to explicitly disclose wherein the source/drain region adjacent to the plurality of channel layers and the epitaxial layer generate at least one of a compressive strain and a tensile strain on the plurality of channel layers depending on a type of material selected to form the source/drain region and the epitaxial layer.
Nevertheless, in a related endeavor (Fig 1-11F or Chang ‘639), Chang ‘639 teaches wherein the source/drain region (120D/130D, Fig 11B, Para [0127]) adjacent to the plurality of channel layers (120N, Fig 11B, Para 0127]) and the epitaxial layer (layer of 120D/130D nearest channel 120N) generate at least one of a compressive strain and a tensile strain on the second channel layer (120N) depending on a type of material selected to form the second source/drain region and the epitaxial layer. (Para [0122] of Chang ‘639 teaches the lattice mismatch between silicon and germanium can achieve a compressive or tensile strain.)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chang ‘639’s teaching of using the lattice mismatch between the silicon and germanium regions of the source/drain region and epitaxial layer and the channel layer to generate a compressive strain or tensile strain into More ‘894’s device. More ‘894 teaches a transistor device with source/drain and epitaxial layers and nanosheet channel layers of silicon and silicon germanium. Chang ‘639 teaches a transistor device using nanosheet channel layers of silicon and silicon germanium. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, one of ordinary skill in the art would recognize that modulating the strain in transistor can achieve the well-known advantage of improving electron mobility.
As incorporated, the use of the differing lattice structures of silicon and germanium to achieve strain, as taught by Chang ‘639 would be used to achieve a strain between the silicon and germanium materials of the second source/drain region first 150 from left as shown in Fig 2H) and the epitaxial layer (154a) and the second channel layer (120’ in stack 160A) of More ‘894 so that one of a compressive strain and a tensile strain exists on the second channel layer depending on a type of material selected to form the second source/drain region and the epitaxial layer.
Claims 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over More ‘894 in view of Chung et al. (US 2022/0140078 A1, hereinafter Chung ‘078), in view of the following arguments.
With respect to Claim 7 More ‘894 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 further discloses, and a material forming the second source/drain region (first 150 from left as shown in Fig 2H) comprises Silicon-Germanium doped with Boron (Para [0047] discloses 156A as silicon germanium that is boron doped).
But More ‘894 fails to explicitly disclose wherein a material forming the epitaxial layer comprises at least one of Silicon and Silicon doped with Boron.
Nevertheless, in a related endeavor (Fig 1-18D of Chung ‘078), Chung ‘078 teaches e wherein a material forming the epitaxial layer (261A, Fig 18C, Para [0030]) comprises at least one of Silicon and Silicon doped with Boron (Para [0034] of Chung ‘078 discloses 261A comprises silicon).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘078’s teaching of wherein a material forming the epitaxial layer comprises at least one of Silicon and Silicon doped with Boron into More ‘894’s device. More ‘894 teaches a GAA device with pFET and nFET regions and a epitaxial layer around the channel structures of those devices. Chung ‘078 also teaches a GAA device with pFET and nFET regions and a epitaxial layer around the channel structures of those devices and further teaches details on material choices for the epitaxial layer and source/drain region. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, because as Chung ‘078 teaches in Para [0033] that using silicon in the epitaxial layer can provide protection to the channel layers during process etch steps.
As incorporated, the use of silicon as the epitaxial layer as taught by Chung ‘078 would be used epitaxial layer (154A) of More ‘894.
With respect to Claim 11 More ‘894 discloses all limitations of the semiconductor structure of claim 1 (Note Examiner’s above interpretation of Claim 11 being dependent on claim 8), and More ‘894 further discloses wherein the semiconductor structure (100 in region 106A) is a P-type transistor (disclosed in Para [0013]), and the source/drain region (first 150 from left as shown in Fig 2H) comprising Silicon-Germanium doped with Boron (Para [0047] discloses 1556A as silicon germanium that is boron doped).
But More ‘894 fails to explicitly disclose wherein a material forming the epitaxial layer comprises at least one of Silicon and Silicon doped with Boron.
Nevertheless, in a related endeavor (Fig 1-18D of Chung ‘078), Chung ‘078 teaches e wherein a material forming the epitaxial layer (261A, Fig 18C, Para [0030]) comprises at least one of Silicon and Silicon doped with Boron (Para [0034] of Chung ‘078 discloses 261A comprises silicon).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘078’s teaching of wherein a material forming the epitaxial layer comprises at least one of Silicon and Silicon doped with Boron into More ‘894’s device. More ‘894 teaches a GAA device with pFET and nFET regions and a epitaxial layer around the channel structures of those devices. Chung ‘078 also teaches a GAA device with pFET and nFET regions and a epitaxial layer around the channel structures of those devices and further teaches details on material choices for the epitaxial layer and source/drain region. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, because as Chung ‘078 teaches in Para [0033] that using silicon in the epitaxial layer can provide protection to the channel layers during process etch steps.
As incorporated, the use of silicon as the epitaxial layer as taught by Chung ‘078 would be used epitaxial layer (154A) of More ‘894.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over More ‘894 in view of Ju et al. (US 2021/0134795 A1, hereinafter Ju ‘795), in view of the following arguments.
With respect to Claim 18 More ‘894 discloses all limitations of the semiconductor structure of claim 8, wherein each of the plurality of channel layer includes a dumbbell-like shape.
But More ‘894 fails to explicitly disclose wherein each of the plurality of channel layer includes a dumbbell-like shape.
Nevertheless, in a related endeavor (Fig 3A-3K of Ju ‘795), Ju ‘795 teaches wherein each of the plurality of channel layer (104b’-104d’/105b-105d, Fig 3K of Ju ‘795, Para [0074]) includes a dumbbell-like shape (Fig 3J and 3K of Ju ‘795 disclose channel layers 104b’-104d’/105b-105d have a dumbbell shape).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ju ‘795’s teaching of wherein each of the plurality of channel layer includes a dumbbell-like shape into More ‘894’s device. More ‘894 teaches a GAA CMOS structure and in Para [0058] discloses different shapes are possible for channel layer 120 but More ‘894 does not explicitly disclose possible shapes. Ju ‘795 also teaches a GAA CMOS and teaches that the channel layers with different shapes. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, because, as the narrower channel region between the metal gate areas while maintain a larger region contacting the epitaxial region would enable a device with an overall lower vertical height.
As incorporated, the shape of channel layers 104b’-104d’/105b-105d as taught by Ju ‘795 would be used as the channel layers 120’ of More ‘894.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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