DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 3-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
Amendment to Claim 1 in Applicant’s Arguments dated 07/15/2026 overcomes the Drawing Objection in the Non-Final Office Action mailed on 04/16/2026, therefore that objection is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Amendments to Claims 9-12 in Applicant’s Arguments dated 07/15/2026 overcome the 35 USC § 112 in the Non-Final Office Action mailed on 04/16/2026, therefore those 35 USC § 112 are withdrawn.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "…each of the first metal stack and…” in first and second lines of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination Examiner interprets Claim 3 as “The semiconductor structure of claim 1, wherein the second metal gate stack further comprises a gate dielectric material.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 11-12, 14-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over More et al. (US 2022/0392894 A1, hereinafter More ‘894) in view of Chung et al. (US 2022/0140078 A1, hereinafter Chung ‘078), in view of the following arguments.
PNG
media_image1.png
648
710
media_image1.png
Greyscale
With respect to Claim 1 More ‘894 discloses a semiconductor structure (Fig 1-4C), comprising:
a gate-all-around device (device of GAA 100 in region 106A, Fig 2H, Para [0013], hereinafter SGAA) disposed on a substrate (105, Fig 2H, Para [0013]), the gate-all-around device (SGAA) comprising a metal gate stack (164A/162A, Fig 2H, Para [0060], hereinafter MGS, Note Examiner notes that the specification of the instant application in Para [0102] discloses metal gate stack may include a layer of hafnium-based material (162A disclosed as hafnium-based in Para [0060]) surrounding a channel layer (120’, Fig 2H, Para [0058])(MGS surrounding 120’ disclosed in Fig 2H), the metal gate stack (MGS) being separated from a source/drain region (first 150 from left as shown in Fig 2H, Para [0030]) by an epitaxial layer (154A, Fig 2H, Para [0030]) disposed on opposite sides (disclosed in Fig 2F) of the metal gate stack (MGS).
But More ‘894 fails to explicitly disclose wherein the epitaxial layer is in direct contact with the metal gate stack.
Nevertheless, in a related endeavor (Fig. 1-18D of Chung ‘078), Chung ‘078 teaches wherein the epitaxial layer (261A, Fig 18C of Chung ‘078, Para [0028]) is in direct contact with the metal gate stack (282/284, Fig 18C of Chung ‘078, Para [0055])(Fig 18C of Chung ‘078 discloses 261A in direct contact with metal gate stack 282/284).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘078’s teaching of s wherein the epitaxial layer is in direct contact with the metal gate stack into More ‘894’s device. More ‘894 discloses a gate all around structure with an epitaxial layer between the channel structure and the source drain region. Chung ‘078 also teaches a gate all around structure with an epitaxial layer between the metal gate stack and channel structure and the source drain region and Chung ‘078 further teaches the epitaxial layer is in direct contact with the metal gate stack. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, because extending the epitaxial layer along the surface of both the channel layers and metal gate stack as Chung ‘078 teaches in Para [0028] that the interfaces of the epitaxial layer and the channel and metal gate stack layers serve as additional pathways for change movement in operation and mitigate current crowding issues.
As incorporated, the teaching of Chung ‘078 of the epitaxial layer (261A) in direct contact with the metal gate stack would be used in place of the epitaxial layer (154A) and inner spacer (148’) of More ‘894 such that the epitaxial layer (261A of Chung ‘078) would be in direct contact with the metal gate stack (MGS) of More ‘894.
With respect to Claim 3 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 as modified by Chung ‘078further discloses wherein each of the first metal gate stack and the metal gate stack further comprises a gate dielectric material (Note above Examiner’s interpretation of “wherein each of the first metal gate stack and the metal gate stack further comprises a gate dielectric material” as “wherein the metal gate stack further comprises a gate dielectric material”)(Para [0060] of Chung ‘078 discloses MSG of More ‘894 as modified by Chung’078 above contains a high-k dielectric hafnium-oxide material.)
With respect to Claim 4 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 as modified by Chung ‘078 further discloses wherein the gate-all-around device (SGAA) further comprises:
a sidewall gate spacer (132, Fig 2H, Para [0019]) located along opposite sidewalls (left and right sides of 164A) of a portion (164A, Fig 2H, Para [0060]) of the metal gate stack (MGS) disposed above the channel layer (120’), wherein a thickness (thickness of 132 as shown in annotated Fig 2H of More ‘894) of the sidewall gate spacer (132) defines an extension region (extension region of 132 shown in annotated Fig 2H of More ‘894) for the gate-all-around device (SGAA); and
a diffusion region (Para [0052] discloses region under extension region of 132 as a diffusion region, hereinafter DR) located within the extension region (annotated Fig 2H of More ‘894 discloses DR is located within extension region of 132), the diffusion region (DR) including an outer portion (outer portion of 120’) of the channel layer (120’) and an outer portion (outer portion of 261A of Chung ‘078 as incorporated in More ‘894 as above) of the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894)(annotated Fig 2H of More ‘894 discloses diffusion region includes outer portion of 120’ and outer portion of 154A (as incorporated above 261A occupies the area of 154A/148’ in Fig 2H of More ‘894)).
With respect to Claim 5 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 4, and More ‘894 as modified by Chung ‘078 further discloses wherein the diffusion region (DR) is located at an interface between the source/drain region (first 150 from left as shown in Fig 2H), the channel layer (120’) and the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894 as above)(annotated Fig 2H of More ‘894 discloses DR is located at interface of second source/drain, second channel and epitaxial layer), the diffusion region (DR) having a U-shaped perimeter (U-Shape of DR disclosed in annotated Fig 2H) that surrounds (DR surrounding first 150 from left as shown in annotated Fig 2H) the source/drain region (first 150 from left as shown in Fig 2H), the diffusion region (DR) including diffused dopant atoms from the source/drain region (first 150 from left as shown in Fig 2H)(Annotated Fig 2H of More ‘894 discloses regions of first 150 from left as shown in Fig 2H is present in the DR, therefore the diffused dopants in 150 (Para [0030] discloses 156A, part of 150, as doped) are part of DR).
With respect to Claim 7 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 1, and More ‘894 as modified by Chung ‘078 further discloses, wherein a material forming the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894 as above) comprises at least one of Silicon and Silicon doped with Boron (Para [0036] of Chung ‘078 discloses 261A of Chung ‘078 as incorporated in More ‘894 comprises Si doped with boron) and a material forming the second source/drain region (first 150 from left as shown in Fig 2H of More ‘894) comprises Silicon-Germanium doped with Boron (Para [0047] discloses 156A as silicon germanium that is boron doped).
With respect to Claim 8 More ‘894 discloses a semiconductor structure (100 in region 106A) (Fig 1-4C), comprising:
a plurality of channel layers (plurality of 120’, Fig 2H, Para [0058]) vertically stacked (disclosed in Fig 2H) over a substrate (105, Fig 2H, Para [0013]);
a metal gate stack (164A/162A, Fig 2H, Para [0060], hereinafter MGS, Note Examiner notes that the specification of the instant application in Para [0102] discloses metal gate stack may include a layer of hafnium-based material (162A disclosed as hafnium-based in Para [0060])) including a gate dielectric material (162A, Fig 2H, Para [0060]), the metal gate stack (MGS) being located between (disclosed in Fig 2H) the plurality of channel layers (plurality of 120’);
an epitaxial layer (154A, Fig 2H, Para [0030]) disposed on opposite sides (disclosed in Fig 2H) of the metal gate stack (MGS);
a source/drain region (first 150 from left as shown in Fig. 2H, Para [0030]) adjacent to (disclosed in Fig 2H) the plurality of channel layers (plurality of 120’) and the epitaxial layer (154A); and
a diffusion region (Para [0052] discloses region under extension region of 132 as a diffusion region, hereinafter DR) located at an interface between the source/drain region (first 150 from left as shown in Fig 2H), the plurality of channel layers (plurality of 120’ in stack 160A) and the epitaxial layer (154A) (annotated Fig 2H of More ‘894 discloses DR is located at interface of source/drain region, plurality of channel layers and epitaxial layer), the diffusion region (DR) having a U-shaped perimeter (U-Shape of DR disclosed in annotated Fig 2H) that surrounds the source/drain region (first 150 from left as shown in Fig 2H) (DR surrounding first 150 from left as shown in annotated Fig 2H), the diffusion region (DR) including diffused dopant atoms from the source/drain region (first 150 from left as shown in Fig 2H)(Annotated Fig 2H of More ‘894 discloses regions of first 150 from left as shown in Fig 2H is present in the DR, therefore the diffused dopants in 150 (Para [0030] discloses 156A, part of 150, as doped) are part of DR).
But More ‘894 fails to explicitly disclose wherein the epitaxial layer is in direct contact with the metal gate stack.
Nevertheless, in a related endeavor (Fig. 1-18D of Chung ‘078), Chung ‘078 teaches wherein the epitaxial layer (261A, Fig 18C of Chung ‘078, Para [0028]) is in direct contact with the metal gate stack (282/284, Fig 18C of Chung ‘078, Para [0055])(Fig 18C of Chung ‘078 discloses 261A in direct contact with metal gate stack 282/284).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chung ‘078’s teaching of s wherein the epitaxial layer is in direct contact with the metal gate stack into More ‘894’s device. More ‘894 discloses a gate all around structure with an epitaxial layer between the channel structure and the source drain region. Chung ‘078 also teaches a gate all around structure with an epitaxial layer between the metal gate stack and channel structure and the source drain region and Chung ‘078 further teaches the epitaxial layer is in direct contact with the metal gate stack. The ordinary artisan would have been motivated to modify More ‘894 in the manner set forth above, at least, because extending the epitaxial layer along the surface of both the channel layers and metal gate stack as Chung ‘078 teaches in Para [0028] that the interfaces of the epitaxial layer and the channel and metal gate stack layers serve as additional pathways for change movement in operation and mitigate current crowding issues.
As incorporated, the teaching of Chung ‘078 of the epitaxial layer (261A) in direct contact with the metal gate stack would be used in place of the epitaxial layer (154A) and inner spacer (148’) of More ‘894 such that the epitaxial layer (261A of Chung ‘078) would be in direct contact with the metal gate stack (MGS) of More ‘894.
With respect to Claim 9 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 as modified by Chung ‘078 further discloses wherein the metal gate stack (MGS) surrounds the plurality of channel layers (plurality of 120’) and is separated from the source/drain region (first 150 from left as shown in Fig 2H) by the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894 as above) (Fig 2H discloses 160A surrounds the second channel layer and is separated from the second source/drain region by 261A of Chung ‘078 as incorporated in More ‘894 as above (as incorporated above 261A occupies the area of 154A/148’ in Fig 2H of More ‘894)).
With respect to Claim 11 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 as modified by Chung ‘078 further discloses wherein the semiconductor structure (100 in region 106A) is a P-type transistor (disclosed in Para [0013]), with the epitaxial layer (261A, Fig 18C, Para [0030]) comprising at least one of Silicon and Silicon doped with Boron (Para [0036] of Chung ‘078 discloses 261A of Chung ‘078 as incorporated in More ‘894 comprises Si doped with boron) and the source/drain region (first 150 from left as shown in Fig 2H) comprising Silicon-Germanium doped with Boron (Para [0047] discloses 156A as silicon germanium that is boron doped).
With respect to Claim 12 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 as modified by Chung ‘078 discloses further comprising:
a sidewall gate spacer (132, Fig 2H, Para [0019]) located along opposite sidewalls (left and right of 164A) of a portion (164A, Fig 2H, Para [0060]) of the metal gate stack (MGS) disposed above an uppermost channel layer (top layer 120’ as shown in Fig 2H) of the plurality of channel layers (plurality of 120’).
With respect to Claim 14 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 12, and More ‘894 as modified by Chung ‘078 further discloses wherein outer sidewalls (outer sidewalls of 261A of Chung ‘078 as incorporated in More ‘894) of the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894) are vertically aligned with outer sidewalls (outer sidewalls of plurality of 120’) of the plurality of channel layers (plurality of 120’) and outer sidewalls (outer sidewalls of 132 as shown in annotated Fig 2H of More ‘894) of the sidewall gate spacer (132)(annotated Fig 2H of More ‘894 discloses outer sidewalls of 154A and outer sidewalls of plurality of 120’ in stack of 160A are vertically aligned with the sidewalls of gate spacer 132 (as incorporated above 261A occupies the area of 154A/148’ in Fig 2H of More ‘894)).
With respect to Claim 15 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 as modified by Chung ‘078 further discloses wherein the diffusion region (DR) further comprises dopant atoms diffused within an outer portion (outer portion of each of plurality of 120’) of each of the plurality of channel layers (plurality of 120’) and within an outer portion (outer portion of 261A of Chung ‘078 as incorporated in More ‘894 above) of the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894 above)(Para [0047] discloses 120’ doped with Ge and Para [0036] of Chung ‘078 discloses 261A of Chung ‘078 as incorporated in More ‘894 doped with boron. Therefore DR comprises dopants in the portions of 120’ and 261A of Chung ‘078 as incorporated in More ‘894 in the DR region as described in claim 8).
With respect to Claim 16 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 as modified by Chung ‘078 further discloses wherein the diffusion region (DR) further comprises dopant atoms (Para [0036] of Chung ‘078 discloses 261A of Chung ‘078 as incorporated in More ‘894 comprises dopants) diffused within an uppermost portion (261A of Chung ‘078 as incorporated in More ‘894 in 105 as shown in Fig 2H (as incorporated above 261A occupies the area of 154A/148’ in Fig 2H of More ‘894)) of the substrate (105) located below the source/drain region (first 150 from left as shown in Fig 2H).
With respect to Claim 19 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 12, and More ‘894 as modified by Chung ‘078 discloses further comprising:
a source/drain contact (source/drain contacts, not shown in figures but disclosed in Para [0044], hereinafter SDC) in contact with (Para [0044] discloses MD contacts regions 150) an uppermost surface (158A, Fig 2H, Para [0044])) of the source/drain region (first 150 from left as shown in Fig 2H), the source/drain contact (SDC) being separated from the metal gate stack (MGS) by the sidewall gate spacer (132)(Para [0044] discloses SDC formed over 158A which is separated from 160A by the sidewall gate spacer); and
a portion of the substrate (105P’, Fig 2H, Para [0021]) below the plurality of channel layers (plurality of 120’ in stack 160A) being located between shallow trench isolation regions (152, Fig 2H, Para [0030]).
With respect to Claim 20 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, and More ‘894 as modified by Chung ‘078 further discloses wherein the plurality of channel layers (plurality of 120’) comprises at least one of a nanosheet, a nanowire, and a nano-ellipse (Para [0012] disclose channel layers as nanosheets).
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over More ‘894 in view of Chung ‘078 in further view of Chang et al. (US 2014/0151639 A1, hereinafter Chang ‘639), in view of the following arguments.
With respect to Claim 6 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 1, but More ‘894 as modified by Chung ‘078 fails to explicitly disclose wherein the second source/drain region and the epitaxial layer generate at least one of a compressive strain and a tensile strain on the second channel layer depending on a type of material selected to form the second source/drain region and the epitaxial layer.
Nevertheless, in a related endeavor (Fig 1-11F or Chang ‘639), Chang ‘639 teaches wherein the source/drain region (120D/130D, Fig 11B, Para [0127]) and the epitaxial layer (layer of 120D/130D nearest channel 120N) generate at least one of a compressive strain and a tensile strain on the channel layer (120N, Fig 11B, Para 0127]) depending on a type of material selected to form the source/drain region and the epitaxial layer. (Para [0122] of Chang ‘639 teaches the lattice mismatch between silicon and germanium can achieve a compressive or tensile strain.)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chang ‘639’s teaching of using the lattice mismatch between the silicon and germanium regions of the source/drain region and epitaxial layer and the channel layer to generate a compressive strain or tensile strain into More ‘894 as modified by Chung ‘078’s device. More ‘894 as modified by Chung ‘078 teaches a transistor device with source/drain and epitaxial layers and nanosheet channel layers of silicon and silicon germanium. Chang ‘639 teaches a transistor device using nanosheet channel layers of silicon and silicon germanium. The ordinary artisan would have been motivated to modify More ‘894 as modified by Chung ‘078 in the manner set forth above, at least, one of ordinary skill in the art would recognize that modulating the strain in transistor can achieve the well-known advantage of improving electron mobility.
As incorporated, the use of the differing lattice structures of silicon and germanium to achieve strain, as taught by Chang ‘639 would be used to achieve a strain between the silicon and germanium materials of the second source/drain region (first 150 from left as shown in Fig 2H) and the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894) and the channel layer (120’) of More ‘894 as modified by Chung ‘078 so that one of a compressive strain and a tensile strain exists on the channel layer depending on a type of material selected to form the source/drain region and the epitaxial layer.
With respect to Claim 10 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, but More ‘894 as modified by Chung ‘078 fails to explicitly disclose wherein the source/drain region adjacent to the plurality of channel layers and the epitaxial layer generate at least one of a compressive strain and a tensile strain on the plurality of channel layers depending on a type of material selected to form the source/drain region and the epitaxial layer.
Nevertheless, in a related endeavor (Fig 1-11F or Chang ‘639), Chang ‘639 teaches wherein the source/drain region (120D/130D, Fig 11B, Para [0127]) adjacent to the plurality of channel layers (plurality of 120N, Fig 11B, Para 0127]) and the epitaxial layer (layer of 120D/130D nearest channel 120N) generate at least one of a compressive strain and a tensile strain on the plurality of channel layer (plurality of 120N) depending on a type of material selected to form the source/drain region and the epitaxial layer. (Para [0122] of Chang ‘639 teaches the lattice mismatch between silicon and germanium can achieve a compressive or tensile strain.)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chang ‘639’s teaching of using the lattice mismatch between the silicon and germanium regions of the source/drain region and epitaxial layer and the channel layer to generate a compressive strain or tensile strain into More ‘894 as modified by Chung ‘078’s device. More ‘894 as modified by Chung ‘078 teaches a transistor device with source/drain and epitaxial layers and nanosheet channel layers of silicon and silicon germanium. Chang ‘639 teaches a transistor device using nanosheet channel layers of silicon and silicon germanium. The ordinary artisan would have been motivated to modify More ‘894 as modified by Chung ‘078 in the manner set forth above, at least, one of ordinary skill in the art would recognize that modulating the strain in transistor can achieve the well-known advantage of improving electron mobility.
As incorporated, the use of the differing lattice structures of silicon and germanium to achieve strain, as taught by Chang ‘639 would be used to achieve a strain between the silicon and germanium materials of the source/drain region (first 150 from left as shown in Fig 2H) and the epitaxial layer (261A of Chung ‘078 as incorporated in More ‘894) and the channel layer (120’) of More ‘894 as modified by Chung ‘078 so that one of a compressive strain and a tensile strain exists on the channel layer depending on a type of material selected to form the source/drain region and the epitaxial layer.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over More ‘894 in view of Chung ‘078 in further view of Ju et al. (US 2021/0134795 A1, hereinafter Ju ‘795), in view of the following arguments.
With respect to Claim 18 More ‘894 as modified by Chung ‘078 discloses all limitations of the semiconductor structure of claim 8, wherein each of the plurality of channel layer includes a dumbbell-like shape.
But More ‘894 as modified by Chung ‘078 fails to explicitly disclose wherein each of the plurality of channel layer includes a dumbbell-like shape.
Nevertheless, in a related endeavor (Fig 3A-3K of Ju ‘795), Ju ‘795 teaches wherein each of the plurality of channel layer (104b’-104d’/105b-105d, Fig 3K of Ju ‘795, Para [0074]) includes a dumbbell-like shape (Fig 3J and 3K of Ju ‘795 disclose channel layers 104b’-104d’/105b-105d have a dumbbell shape).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ju ‘795’s teaching of wherein each of the plurality of channel layer includes a dumbbell-like shape into More ‘894 as modified by Chung ‘078’s device. More ‘894 as modified by Chung ‘078 teaches a GAA CMOS structure and in Para [0058] discloses different shapes are possible for channel layer 120 but More ‘894 as modified by Chung ‘078 does not explicitly disclose possible shapes. Ju ‘795 also teaches a GAA CMOS and teaches that the channel layers with different shapes. The ordinary artisan would have been motivated to modify More ‘894 as modified by Chung ‘078 in the manner set forth above, at least, because, as the narrower channel region between the metal gate areas while maintain a larger region contacting the epitaxial region would enable a device with an overall lower vertical height.
As incorporated, the shape of channel layers 104b’-104d’/105b-105d as taught by Ju ‘795 would be used as the channel layers 120’ of More ‘894 as modified by Chung ‘078.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights