Prosecution Insights
Last updated: May 29, 2026
Application No. 18/062,245

VERTICAL NON-VOLATILE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

Non-Final OA §102
Filed
Dec 06, 2022
Priority
Dec 07, 2021 — RE 10-2021-0174019
Examiner
WARREN, MATTHEW E
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
867 granted / 991 resolved
+19.5% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
26 currently pending
Career history
1014
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
70.3%
+30.3% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 991 resolved cases

Office Action

§102
DETAILED ACTION This Office Action is in response to the RCE and Amendment filed on February 23, 2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 6 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arreghini (US Pub. 2019/0198525 A1). In re claim 6, Arreghin shows (figs. 1 and 5) avertical non volatile memory device comprising: a substrate (105); a plurality of insulating layers (102) and a plurality of conductive layers (104) alternately stacked on a surface of the substrate in a direction perpendicular to the surface of the substrate; a channel layer(502) on the substrate, the channel layer extending in the direction perpendicular to the surface of the substrate, the channel layer on lateral surfaces of the plurality of insulating layers and lateral surfaces of the plurality of conductive layers; and a ferroelectric layer (108; [0035]) between the channel layer and the lateral surfaces of the plurality of conductive layers, wherein the lateral surfaces of the plurality of conductive layers are flat with the lateral surfaces of the plurality of insulating layers, and wherein the ferroelectric layer extends onto the lateral surfaces of the plurality of insulating layers. Allowable Subject Matter Claims 1-5 and 7-20 are allowed. Response to Arguments Applicant’s arguments with respect to claim 6 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Takahashi et al. (US Pub. 2021/0358925 A1) also discloses elements of the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Show 3 earlier events
Sep 12, 2025
Applicant Interview (Telephonic)
Sep 13, 2025
Examiner Interview Summary
Sep 15, 2025
Response Filed
Dec 23, 2025
Final Rejection mailed — §102
Feb 23, 2026
Response after Non-Final Action
Mar 20, 2026
Request for Continued Examination
Mar 24, 2026
Response after Non-Final Action
Apr 08, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641771
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
3y 8m to grant Granted May 26, 2026
Patent 12641794
SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC LAYER AND METHOD OF MANUFACTURING THE SAME
3y 1m to grant Granted May 26, 2026
Patent 12635142
THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION
3y 6m to grant Granted May 19, 2026
Patent 12635228
POWER SEMICONDUCTOR DEVICE
2y 9m to grant Granted May 19, 2026
Patent 12628522
DISPLAY PANEL AND DISPLAY DEVICE
2y 6m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.6%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 991 resolved cases by this examiner. Grant probability derived from career allowance rate.

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