DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered. An action on the RCE follows.
Response to Arguments
Applicant’s reply filed on 12/22/2025 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over SASAKI et al (US 2017/0213918 A1; hereafter SASAKI).
Regarding claim 1. SASAKI discloses a semiconductor device (Fig 1) comprising:
a semiconductor substrate made of β-type gallium oxide (Fig 1, base substrate 11, Para [ 0153-0158]), the semiconductor substrate having a rectangular shape as viewed in a thickness direction of the semiconductor substrate (Fig 1, base substrate 11, Para [ 0153-0158]), the rectangular shape having a side extending in a first direction and another side extending in a second direction (Fig 1, base substrate 11, Para [ 0153-0158]),
wherein a thermal conductivity in the first direction of the semiconductor substrate is different from a thermal conductivity in the second direction of the semiconductor substrate (Fig 1, base substrate 11, Para [ 0157-0158]),
wherein a top surface of the semiconductor substrate is a (001) plane of the β-type gallium oxide, wherein the first direction is a [010] direction of the β -type gallium oxide (Fig 1, base substrate 11, Para [ 0157-0158]).
But SASAKI does not disclose explicitly wherein the semiconductor substrate is configured to satisfy a mathematical relation of L1/L2 = (K1/K2)05 with an inclusive tolerance range of -5% to +5%, where L1 denotes a length of the semiconductor substrate in the first direction, L2 denotes a length of the semiconductor substrate in the second direction, K1 denotes the thermal conductivity in the first direction of the semiconductor substrate, and K2 denotes the thermal conductivity in the second direction of the semiconductor substrate.
However, SASAKI discloses “The principal surface of the base substrate 11 is, e.g., a surface rotated not less than 50° and not more than 90° from the (100) plane of the β-Ga.sub.2O.sub.3-based single crystal”, Para [ 0153], and “the β-Ga.sub.2O.sub.3-based crystal is known to have a high thermal conductivity in a direction (the b-axis direction). For example, a β-Ga.sub.2O.sub.3 crystal has a thermal conductivity of 13.6 W/(m.Math.k) in the [100] direction (the a-axis direction), but has a thermal conductivity of 22.8 W/(m.Math.k) in the [010] direction (the b-axis direction) which is nearly double the thermal conductivity in the [100] direction”, in para [0157].
In addition, “principal surface of the base substrate 11 is, e.g., a surface rotated not less than 50° and not more than 90° from the (100) plane of the β-Ga.sub.2O.sub.3-based single crystal. In other words, an angle θ (0<θ≦90°) formed between the principal surface of the base substrate 11 and the (100) plane is not less than 50°. Examples of the surface rotated not less than 50° and not more than 90° from the (100) plane include a (010) plane, a (001) plane, a (−201) plane, a (101) plane and a (310) plane” and “where a percentage of the re-evaporated raw material during growth of the β-Ga.sub.2O.sub.3-based crystal at a growth temperature of 500° C”, Para [ 0154].
Based on that, semiconductor substrate includes same materials and variable temperature with same direction [010/001] as disclosed instant application as a result effective variable can have same mathematical results.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention in light of SASAKI teaching for thermal conductivity in the first direction of the semiconductor substrate is different from a thermal conductivity in the second direction of the semiconductor substrate for further advantage such as to provide excellent heat dissipation property and withstand voltage property (Sasaki, Para [ 0006]).
Regarding claim 2. SASAKI discloses the semiconductor device according to Claim 1, SASAKI further discloses wherein the semiconductor substrate is made of an oxide semiconductor (Para [ 0032, 0262]).
Regarding claim 3. SASAKI discloses the semiconductor device according to Claim 1, SASAKI further discloses wherein the semiconductor substrate is made of gallium oxide (Para [ 0032, 0262]).
Regarding claim 13. SASAKI discloses the semiconductor device according to claim 1, SASAKI further discloses wherein a thermal resistance of the semiconductor substrate in the first direction is identical to a thermal resistance of the semiconductor substrate in the second direction (substrate made with same material Ga.sub.2O.sub.3-based crystal, therefore, same material can have same characteristics, Para [ 0153-0158]).
Claims 6-7, 9-10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over SASAKI et al (US 2017/0213918 A1; hereafter SASAKI) as applied claims above and further in view of Kanskar et al (US 2019/0044302 A1; hereafter Kanskar).
Regarding claim 6. SASAKI discloses the semiconductor device according to Claim 1, But SASAKI does not disclose explicitly further comprising: a top electrode located on a top surface of the semiconductor substrate; and a bottom electrode located on a bottom surface of the semiconductor substrate, wherein the semiconductor substrate is further configured to allow a current flowing between the top electrode and the bottom electrode through the semiconductor substrate.
In a similar field of endeavor, Kanskar discloses
a top electrode (Fig 6, copper layer 610A, Para [ 0048]) located on a top surface of the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]); and
a bottom electrode (element 644, Para [ 0048]) located on a bottom surface of the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]), wherein the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]) is further configured to allow a current flowing between the top electrode (Fig 6, copper layer 610A, Para [ 0048]) and the bottom electrode (element 644, Para [ 0048]) through the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar teaching” a top electrode (Fig 6, copper layer 610A, Para [ 0048]) located on a top surface of the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]); and
a bottom electrode (element 644, Para [ 0048]) located on a bottom surface of the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]), wherein the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]) is further configured to allow a current flowing between the top electrode (Fig 6, copper layer 610A, Para [ 0048]) and the bottom electrode (element 644, Para [ 0048]) through the semiconductor substrate (Fig [6], substrate 602, Para [ 0048])” for further advantage such as can provide high thermal conductivities with reliable semiconductor device formation.
Regarding claim 7. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 6, Kanskar another embodiment discloses further comprising: a heat sink joined to the bottom electrode (Fig 2, heatsink 240, bottom electrode 220, substrate 202, Para [ 0040,0048]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar teaching “a heat sink joined to the bottom electrode (Fig 2, heatsink 240, bottom electrode 220, substrate 202, Para [ 0040,0048])” for further advantage such as excellent heat dissipation.
Regarding claim 9. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 6, Kanskar further discloses further comprising:
a metal block (Fig 6, solder layer 624, Para [ 0048]) joined to the top electrode (Fig 6, copper layer 610A, Para [ 0048]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar teaching” a metal block (Fig 6, solder layer 624, Para [ 0048]) joined to the top electrode (Fig 6, copper layer 610A, Para [ 0048])” for further advantage such as can provide high thermal conductivities with reliable semiconductor device formation.
Regarding claim 10. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 9, Kanskar further discloses wherein the metal block has an isotropic thermal conductivity (Fig 6, solder layer 624, Para [ 0048]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar teaching” wherein the metal block has an isotropic thermal conductivity (Fig 6, solder layer 624, Para [ 0048])” for further advantage such as can provide high thermal conductivities with reliable semiconductor device formation.
Regarding claim 15. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 6, SASAKI further discloses wherein, the second thickness direction is a [001] direction of the β- type gallium oxide, and the second direction is a [100] direction of the β- type gallium oxide (Para [ 0157-0158]).
Regarding claim 16. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 6, Kanskar further discloses wherein the top electrode (Fig 6, copper layer 610A, Para [ 0048]) has a Schottky contact (based on the semiconductor materials contact with the metal can have Schottky contact) with the semiconductor substrate (Fig [6], substrate 602, Para [ 0048]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar teaching” wherein the top electrode (Fig 6, copper layer 610A, Para [ 0048]) has a Schottky contact (based on the semiconductor materials contact with the metal can have Schottky contact) with the semiconductor substrate (Fig [6], substrate 602, Para [ 0048])” for further advantage such as can provide high thermal conductivities with reliable semiconductor device formation.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over SASAKI et al (US 2017/0213918 A1; hereafter SASAKI) and Kanskar et al (US 2019/0044302 A1; hereafter Kanskar) as applied claims above and further in view of Mohammed et al (US 2012/0206882 A1; hereafter Mohammed).
Regarding claim 8. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 7, But SASAKI in light of Kanskar does not disclose explicitly wherein the heat sink has an isotropic thermal conductivity.
In a similar field of endeavor, Mohammed discloses wherein the heat sink has an isotropic thermal conductivity (Para [ 0060]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar in light of Mohammed teaching “wherein the heat sink has an isotropic thermal conductivity (Para [ 0060]))” for further advantage such as excellent heat dissipation.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over SASAKI et al (US 2017/0213918 A1; hereafter SASAKI) and Kanskar et al (US 2019/0044302 A1; hereafter Kanskar) as applied claims above and further in view of Shimono (US 2016/0233214 A1; hereafter Shimono).
Regarding claim 11. SASAKI in light of Kanskar discloses the semiconductor device according to Claim 1, But SASAKI in light of Kanskar does not disclose explicitly further comprising: a temperature sensing element configured to sense a temperature of the semiconductor substrate.
In a similar field of endeavor, Shimono discloses a temperature sensing element (diode 30, Para [ 0017]) configured to sense a temperature of the semiconductor substrate (Para [ 0005,0017]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI in light of Kanskar in light of Shimono teaching “a temperature sensing element (diode 30, Para [ 0017]) configured to sense a temperature of the semiconductor substrate (Para [ 0005,0017])” for further advantage such as a temperature sense diode capable of sensing a temperature of a semiconductor substrate with higher accuracy (Shimono, Para [ 0005]).
Regarding claim 12. SASAKI and Kanskar in light of Shimono discloses the semiconductor device according to Claim 11, Shimono further discloses wherein the temperature sensing element (Fig 1, diode 30, Para [ 0017]) is located at a central portion of a top surface of the semiconductor substrate (Fig 1, substrate 12, Para [ 0019]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI and Kanskar in light of Shimono teaching “wherein the temperature sensing element (Fig 1, diode 30, Para [ 0017]) is located at a central portion of a top surface of the semiconductor substrate (Fig 1, substrate 12, Para [ 0019])” for further advantage such as a temperature sense diode capable of sensing a temperature of a semiconductor substrate with higher accuracy (Shimono, Para [ 0005]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over SASAKI et al (US 2017/0213918 A1; hereafter SASAKI) and Kanskar et al (US 2019/0044302 A1; hereafter Kanskar) as applied claims above and further in view of CHEN et al (US 2023/0354897 A1; hereafter CHEN).
Regarding claim 14. SASAKI and Kanskar discloses the semiconductor device according to Claim 1, SASAKI further discloses a β-Ga.sub.2O.sub.3 crystal has a thermal conductivity of 13.6 W/(m.Math.k) in the [100] direction (the a-axis direction), but has a thermal conductivity of 22.8 W/(m.Math.k) in the [010] direction (the b-axis direction) which is nearly double the thermal conductivity in the [100] direction”, in para [0157].
But SASAKI and Kanskar does not disclose explicitly wherein the thermal conductivity in the first direction of the semiconductor substrate is 14.4 W/mK, and the thermal conductivity in the second direction of the semiconductor substrate is 7.2 W/mK.
In a similar field of endeavor, CHEN discloses wherein the thermal conductivity in the first direction of the semiconductor substrate is 14.4 W/mK, and the thermal conductivity in the second direction of the semiconductor substrate is 7.2 W/mK.
(Fig 2, Para [ 0029-0033] discloses thermal conductivity of substrate varies with temperature. Based on the temperature variation, substrate (as discloses by SASAKI substrate β-Ga.sub.2O.sub.3 ) can have desire thermal conductivity with different direction, as a result effective variable based on the temperature variation).
It would have been obvious to ordinary skilled in the art before the effective filing date, to optimize the thermal conductivity in the first direction of the semiconductor substrate is 14.4 W/mK, and the thermal conductivity in the second direction of the semiconductor substrate is 7.2 W/mK with respect to the limitations of claim 14, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed thermal conductivity would have been obvious to one of ordinary skill in the art for further advantages such as control thermal conductivity in order to control heat dissipation.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine SASAKI and Kanskar in light of CHEN teaching “wherein the thermal conductivity in the first direction of the semiconductor substrate is 14.4 W/mK, and the thermal conductivity in the second direction of the semiconductor substrate is 7.2 W/mK. (Fig 2, Para [ 0029-0033] discloses thermal conductivity of substrate varies with temperature. Based on the temperature variation, substrate (as discloses by SASAKI substrate β-Ga.sub.2O.sub.3 ) can have desire thermal conductivity with different direction, as a result effective variable based on the temperature variation)” for further advantage such as control thermal conductivity in order to control heat dissipation.
Conclusion
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898