DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-5, 8-9, 11-12, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai; Ming Chian et al. (US 2023/0069137; hereinafter Tsai).
Regarding claim 1, Tsai discloses a semiconductor structure comprising:
a first circuit row (comprising power tap cell 160, along the X-direction; Fig 2A; ¶ [0044-53]);
a first power rail (120b; Figs 2A,2D; ¶ [0048]) on a front side (upper side; Figs 2A,2D) of the first circuit row;
a second power rail (110a; Figs 2A,2D; ¶ [0048]) on a back side of the first circuit row; and
a first cell in the first circuit row (160; Figs 2A,2D; ¶ [0048]), wherein the first cell includes one or more power vias (161,163,165,121; Fig 2D; ¶ [0048]) connecting the first power rail to the second power rail.
Regarding claim 2, Tsai discloses the semiconductor structure of claim 1, wherein the second power rail (110a; Figs 2A,2D) is orthogonal to the first power rail (120b; Figs 2A,2D).
Regarding claim 4, Tsai discloses the semiconductor structure of claim 1, wherein the one or more power vias (161,163,165,121; Figs 2D,2E) have at least two or more different sized power vias (for example, a height of 165 is different from a height of 163; Fig 2E; ¶ [0051]).
Regarding claim 5, Tsai discloses the semiconductor structure of claim 1, wherein the one or more power vias (161,163,165,121; Figs 2D,2E) include at least two or more different aspect ratios (for example, an aspect ratio ranges from five to ten for 165, but from one to three for 163; Fig 2E; ¶ [0051]).
Regarding claim 8, Tsai discloses a semiconductor structure comprising:
a plurality of circuit rows (comprising 120a,120b, along the X-direction; Fig 2A; ¶ [0044-53]);
a plurality of first power rails (120a,120b; Figs 2A,2D; ¶ [0048]) positioned on front sides (upper side; Figs 2A,2D) of the plurality of circuit rows;
a plurality of second power rails (110a,110b; Figs 2A,2D; ¶ [0048]) positioned on back sides of the plurality of circuit rows; and
power tap cells (160 {160a,160b}; Figs 2A,2D, {1}; ¶ [0048,{0038}]) associated with each of the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias (161,163,165,121; Fig 2D; ¶ [0048]) connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality of second power rails.
Regarding claim 9, Tsai discloses the semiconductor structure of claim 8, wherein the plurality of second power rails (110a,110b; Figs 2A,2D) are orthogonal to the plurality of first power rails (120a,120b; Figs 2A,2D).
Regarding claim 11, Tsai discloses the semiconductor structure of claim 8, wherein the one or more power vias (161,163,165,121; Figs 2D,2E) include at least two or more different sized power vias (for example, a height of 165 is different from a height of 163; Fig 2E; ¶ [0051]).
Regarding claim 12, Tsai discloses the semiconductor structure of claim 8, wherein the one or more power vias (161,163,165,121; Figs 2D,2E) have at least two or more different aspect ratios (for example, an aspect ratio ranges from five to ten for 165, but from one to three for 163; Fig 2E; ¶ [0051]).
Regarding claim 17, Tsai discloses a semiconductor structure comprising:
a first power rail (120b; Figs 2A,2D; ¶ [0048]) on a front side (upper side; Figs 2A,2D) of a stacked field effect transistor (FET) (CFET 150a; Figs 2A,2D; ¶ [0044]);
a second power rail (110a; Figs 2A,2D; ¶ [0048]) on a back side (lower side; Figs 2A,2D) of the stacked FET; and
a tap power cell (160; Figs 2A,2D; ¶ [0048]) having one or more power vias (161,163,165,121; Fig 2D; ¶ [0048]) connecting the first power rail to the second power rail.
Regarding claim 18, Tsai discloses the semiconductor structure of claim 17, wherein the second power rail (110a; Figs 2A,2D) is orthogonal to the first power rail (120b; Figs 2A,2D).
Regarding claim 20, Tsai discloses the semiconductor structure of claim 17, wherein the one or more power vias (161,163,165,121; Figs 2D,2E) have at least two or more different sized power vias (for example, a height of 165 is different from a height of 163; Fig 2E; ¶ [0051]).
Claims 1, 7-8, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai; Ming Chian et al. (US 2023/0069137; hereinafter Tsai) (Second Interpretation).
Regarding claim 1, Tsai discloses a semiconductor structure comprising:
a first circuit row (comprising power tap cell 460, along the X-direction; Fig 4A; ¶ [0063,0044-53]);
a first power rail (120b; Figs 4A; ¶ [0063,0048]) on a front side (upper side; Figs 4A) of the first circuit row;
a second power rail (110a; Figs 4A; ¶ [0063,0048]) on a back side of the first circuit row; and
a first cell in the first circuit row (460; Figs 4A; ¶ [0063,0048]), wherein the first cell includes one or more power vias (FTV; Fig 4A; ¶ [0064]) connecting the first power rail to the second power rail.
Regarding claim 7, Tsai discloses the semiconductor structure of claim 1 (second interpretation), wherein additional power rails (130a; Fig 4A; ¶ [0063-64]) are positioned over the first power rail (120b; Figs 4A), such that the additional power rails are perpendicular to the first power rail.
Regarding claim 8, Tsai discloses a semiconductor structure comprising:
a plurality of circuit rows (extending along the X-direction; Fig 4A; ¶ [0063,0044-53]);
a plurality of first power rails (120a,120b; Figs 4A; ¶ [0063,0048]) positioned on front sides (upper side; Figs 4A) of the plurality of circuit rows;
a plurality of second power rails (110a,110b; Figs 4A; ¶ [0063,0048]) positioned on back sides of the plurality of first circuit rows; and
power tap cells (460 {one labeled beneath 130a, a second unlabeled beneath the intersection of 120b,130b}; Figs 4A; ¶ [0063,0048]) associated (through 130) with each of the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias (FTV; Fig 4A; ¶ [0064]) connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality of second power rails.
Regarding claim 16, Tsai discloses the semiconductor structure of claim 8 (second interpretation), wherein additional power rails (130a,130b; Fig 4A; ¶ [0063-64]) are positioned over the plurality of first power rails (120a,120b; Figs 4A), such that the additional power rails are perpendicular to the plurality of first power rails.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai; Ming Chian et al. (US 2023/0069137; hereinafter Tsai) in view of Lai; Po-Chia et al. (US 2020/0019666; hereinafter Lai).
Regarding claim 6, Tsai discloses the semiconductor structure of claim 1, wherein the first cell (160; Fig 2A) is positioned on an edge of the first circuit row (lower edge, comprising 110a; Fig 2A), but does not disclose, from a circuit layout perspective, the first cell is positioned on an edge of the first circuit row.
In the same field of endeavor, Lai discloses an integrated circuit design method comprising a power tap cell (312, coupled to a VDD or VSS power rail; Fig 3A; ¶ [0034-35,0038]) positioned on an edge of a first circuit row (left edge of row 1; Fig 3A). Accordingly, it would have been obvious to position the first (power tap) cell of Tsai on an edge of the first circuit row. One would have been motivated to do this, with a reasonable expectation of success, because the cell positioning is decided based upon a number of factors specific to particular design and manufacturing needs, as is well-known in the art, and Lai has disclosed a power tap cell in this position, as a viable option.
Regarding claim 15, Tsai discloses the semiconductor structure of claim 8, wherein the power tap cells (160; Fig 2A) are positioned on an edge of the plurality of circuit rows (lower edge, comprising 110a; Fig 2A), but does not disclose, from a circuit layout perspective, the power tap cells are positioned on an edge of the plurality of circuit rows.
In the same field of endeavor, Lai discloses an integrated circuit design method comprising power tap cells (312, coupled to a VDD or VSS power rail; Fig 3A; ¶ [0034-35,0038]) positioned on an edge of a plurality of circuit rows (left edge of rows 1-9; Fig 3A). Accordingly, it would have been obvious to position the power tap cells of Tsai on an edge of the plurality of circuit rows. One would have been motivated to do this, with a reasonable expectation of success, because the cell positioning is decided based upon a number of factors specific to particular design and manufacturing needs, as is well-known in the art, and Lai has disclosed power tap cells in this position, as a viable option.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai; Ming Chian et al. (US 2023/0069137; hereinafter Tsai) in view of Liebmann; Lars et al. (US 2021/0118798; hereinafter Liebmann798).
Regarding claim 13, Tsai discloses the semiconductor structure of claim 8, but does not disclose wherein each of the plurality of circuit rows is associated with a single power tap cell of the power tap cells.
In the same field of endeavor, Liebmann discloses a semiconductor structure (200; Fig 2; ¶ [0047-50]) wherein each of a plurality of circuit rows (Cell Rows A-C; Fig 2) is associated with a single power tap cell (221; Fig 2; ¶ [0048]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the semiconductor structure of claim 8 may be configured in this manner. One would have been motivated to do this, in order to minimize the number of power tap cells, and thereby the required area of, power tap cells (Tsai; fewer power tap cells, area penalty; ¶ [0067,0073,0128,0130]). One would have had a reasonable expectation of success because of the similar structures (stacked transistors {CFET}, buried power rails) in the similar endeavors.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai; Ming Chian et al. (US 2023/0069137; hereinafter Tsai) in view of Liebmann; Lars et al. (US 2022/0181258; hereinafter Liebmann258).
Regarding claim 14, Tsai discloses the semiconductor structure of claim 8, but does not disclose wherein at least one power tap cell of the power tap cells is positioned within two circuit rows of the plurality of circuit rows.
In the same field of endeavor, Liebmann258 discloses a semiconductor structure (100; Fig 1; ¶ [0051-57]) wherein a power tap cell is positioned within two cells (Cells A and B, Fig 1; Cells C and D; Fig 2; ¶ [0055-59]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the semiconductor structure of claim 8 may be configured in this manner. One would have been motivated to do this, in order to reduce the required area occupied by power tap cells (Tsai; fewer power tap cells, area penalty; ¶ [0067,0073,0128,0130]) and improve performance (Liebmann258; ¶ [0055]). One would have had a reasonable expectation of success because of the similar structures (stacked transistors {CFET}, buried power rails) in the similar endeavors.
Allowable Subject Matter
Claims 3, 10, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the first power rail is horizontally offset from the second power rail.” In the prior art Tsai, for example, the second power rail is orthogonal to the first power rail (see the 102 rejection of claim 2 above). In another example, the prior art Lin; Chin-Shen et al. (US 2023/0420369) comprises a backside power rail (BM0 VDD, 1063; Fig 10D; ¶ [0141]) parallel to a front side power rail (VDD 1061; Fig 10D; ¶ [0141]), but 1061 overlaps 1063 and is not horizontally offset from it.
Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the plurality of first power rails are horizontally offset from the plurality of second power rails.” In the prior art Tsai, for example, the second power rails are orthogonal to the first power rails (see the 102 rejection of claim 9 above). In another example, the prior art Lin; Chin-Shen et al. (US 2023/0420369) comprises a backside power rail (BM0 VDD, 1063; Fig 10D; ¶ [0141]) parallel to a front side power rail (VDD 1061; Fig 10D; ¶ [0141]), but 1061 overlaps 1063 and is not horizontally offset from it.
Regarding claim 19, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the first power rail is horizontally offset from the second power rail”. In the prior art Tsai, for example, the second power rail is orthogonal to the first power rail (see the 102 rejection of claim 18 above). In another example, the prior art Lin; Chin-Shen et al. (US 2023/0420369) comprises a backside power rail (BM0 VDD, 1063; Fig 10D; ¶ [0141]) parallel to a front side power rail (VDD 1061; Fig 10D; ¶ [0141]), but 1061 overlaps 1063 and is not horizontally offset from it.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lin; Chin-Shen et al. (US 2023/0420369; the prior art discloses a first power rail on a front side of the first circuit row, a second power rail on a back side of the first circuit row, and a power via connecting the first power rail to the second power rail);
Chen; Andy Wangkun et al. (US 2022/0068813; the prior art discloses frontside power rails coupled to backside power rails through power vias).
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817