DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 10/15/2025. Claims 1, 5, 7-9, and 19 have been amended. No new claims have been added or canceled. Currently, claims 1-20 are pending.
Applicant’s amendment to claim 9 successfully overcomes the 112(b) rejection of claim 9 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to independent claims 1, 9, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-10, 12-14, 16-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 20220037340).
Regarding claim 1, Yang teaches, in Fig. 16B, a semiconductor device (200, [0039]) comprising:
an active region (base portion 212B of fin structure 212, see Fig. 2C, [0019]) on a substrate (202, see Fig. 2C, [0019]) and extending in a first direction (Y-direction);
a plurality of channel layers (208, [0018], labelled in Fig. 9C) vertically spaced apart from each other on the active region (212B),
a gate structure (270, [0037]) intersecting the active region (212B) and the plurality of channel layers (208), extending on the substrate in a second direction (X-direction), and surrounding the plurality of channel layers (208);
a source/drain region (248, [0030]) contacting the plurality of channel layers (208) on at least one side of the gate structure (270) and including a first semiconductor material having first impurities of a first conductivity type ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”); and
a lower structure (246/241/242) in contact with the active region (212B) and below the source/drain region (248),
wherein the lower structure includes:
a first layer (242 below 241) on the active region and including an insulating material ([0029]), and
a second layer (246) on the first layer and including a second semiconductor material ([0030]),
the first layer and the second layer defining an air gap (241, [0031]),
wherein the second semiconductor material of the second layer (246) does not have impurities of a conductivity type or has impurities of a second conductivity type different from the first conductivity type ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”), and
wherein the gate structure (270) and the air gap (241) do not overlap each other in a vertical direction (see Fig. 16B).
Regarding claim 2, Yang further teaches that the first semiconductor material (of first source/drain region 248) includes the first impurities in a first concentration, and the second semiconductor material (of second layer 246) includes second impurities different from the first impurities in a second concentration that is less than the first concentration ([0030], “Regardless of the conductivity type of the source/drain features 245, a doping concentration in the inner layer 248 may be greater than the outer layer 246 to reduce contact resistance”).
Regarding claim 4, Yang further teaches, in Fig. 16B, that the source/drain region (248) includes a plurality of first patterns (concave areas of 248 filled by the ends of 208) on both sides of the plurality of channel layers (208) taken in the first direction (Y-direction) and spaced apart from each other (see Fig. 16B), and the source/drain region (248) includes a second pattern surrounding the plurality of first patterns on the second layer (see Fig. 16B how the convex regions of 248 between the first patterns form a second pattern).
Regarding claim 6, Yang further teaches, in Fig. 16B, internal spacer layers on both sides of the gate structure ([0029], 242 at the sides of gate structure 270) taken in the first direction (Y-direction) on a lower surface of each of the plurality of channel layers (208), wherein the internal spacer layers include a same material as the insulating material of the first layer ([0029], both the internal spacer layers and the first layer is labelled “242”).
Regarding claim 7, Yang further teaches that the insulating material included in the first layer (242 below 241) includes at least one of SiN, SiO, SiCN, SiOC, SiON, SiOCN, or SiBCN ([0029], “silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbide, silicon carbide, or silico oxynitride”).
Regarding claim 8, Yang further teaches that each of the first semiconductor material (of first source/drain region 248) and the second semiconductor material (of second layer 246) independently includes at least one of arsenic (As), antimony (Sb), phosphorus (P), boron (B), gallium (Ga), carbon (C), oxygen (O), or nitrogen (N) ([0030]).
Regarding claim 9, Yang teaches, in Fig. 16B, a semiconductor device (200, [0039]) comprising:
an active region (base portion 212B of fin structure 212, see Fig. 2C, [0019]) extending on a substrate (202, see Fig. 2C, [0019]) in a first direction (Y-direction);
a plurality of channel layers (208, [0018], labelled in Fig. 9C) vertically spaced apart from each other on the active region (212B),
a gate structure (270, [0037]) on the substrate, intersecting the active region (212B) and the plurality of channel layers (208), extending in a second direction (X-direction), and surrounding the plurality of channel layers (208);
a source/drain region (248, [0030]) contacting the plurality of channel layers (208) on at least one side of the gate structure (270);
a lower structure (246/241/242) in contact with the active region (212B), below the source/drain region (248), and including a first layer (242 below 241, [0029], and a second layer (246, [0030]) with an air gap (241, [0031]) between the first layer and the second layer, the first layer (242), the air gap (241), and the second layer (246) in sequence from the active region (212B) (see Fig. 16B),
wherein the second layer (246) of the lower structure includes:
an upper surface in contact with the source/drain region (248),
a side surface including at least a portion in contact with the active region (212B), and
a lower surface in contact with the first layer (242) and capping the air gap (241) (see Fig. 16B),
wherein the source/drain region (248) includes a first semiconductor material including first impurities having a first conductivity type ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”); and
wherein the second layer (246) includes a second semiconductor material having no conductivity type or having impurities of a second conductivity type different from the first conductivity type ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”), and
wherein the gate structure (270) and the air gap (241) do not overlap each other in a vertical direction (see Fig. 16B).
Regarding claim 10, Yang further teaches, in Fig. 16B, that the upper surface of the second layer (246) is on a level below a level of a lower surface of a lowermost channel layer among the plurality of channel layers (208).
Regarding claim 12, Yang further teaches, in Fig. 16B, that the active region (212B) includes a recess region, and at least a portion of the lower structure is within the recess region (the recess region is filled with entire lower structure 242/241/246).
Regarding claim 13, Yang further teaches, in Fig. 16B, that the lower surface of the second layer (246) is on a level below a level of an uppermost surface of the active region (the uppermost surface of 212B is at the top of 202 in Fig. 16B).
Regarding claim 14, Yang further teaches, in Fig. 16B, that a plurality of internal spacer layers on both sides of the gate structure ([0029], 242 at the sides of gate structure 270) taken in the first direction (Y-direction) on a lower surface of each of the plurality of channel layers (208).
Regarding claim 16, Yang further teaches, in Fig. 16B, that the source/drain region (248) includes a plurality of first patterns (concave areas of 248 filled by the ends of 208) covering both side surfaces of the plurality of channel layers (208) taken in the first direction (Y-direction), and the source/drain region (248) includes a second pattern on the second layer and surrounding the plurality of first patterns (see Fig. 16B how the convex regions of 248 between the first patterns form a second pattern).
Regarding claim 17, Yang further teaches, in Fig. 16B, that the plurality of first patterns (concave areas of 248 filled by the ends of 208) are spaced apart from each other in a direction perpendicular to an upper surface of the substrate (vertical direction).
Regarding claim 19, Yang teaches, in Fig. 16B, a semiconductor device (200, [0039]), comprising:
an active structure (base portion 212B of fin structure 212, see Fig. 2C, [0019]) extending in a first direction (Y-direction) and including a channel region (208, [0018], labelled in Fig. 9C) and a recess region (the recess region is filled with entire lower structure 242/241/246),
a lower structure (246/241/242) within the recess region;
a source/drain region (248, [0030]) on the lower structure (246/241/242) and doped with first impurities having a first conductivity type ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”); and
gate structures (270, [0037]) on both sides of the source/drain region (248) taken in the first direction (Y-direction), intersecting the channel region (208), and extending in a second direction (X-direction),
wherein the lower structure (246/241/242) includes:
a first layer (242 below 241) in contact with the active structure (202) and including an insulating material ([0029]), and
a second layer (246) disposed on the first layer (242) and including a semiconductor material ([0030]), and
with an air gap (241, [0031]) interposed between the first layer (242) and the second layer (246),
wherein the semiconductor material of the second layer (246) has no conductivity type or has impurities of a second conductivity type different from the first conductivity type ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”), and
wherein the gate structure (270) and the air gap (241) do not overlap each other in a vertical direction (see Fig. 16B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 5, 11, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20220037340) in view of Liu et al. (US 12336237).
Regarding claim 3, Yang teaches the limitations of claim 2. Yang does not explicitly teach that the second concentration is greater than or equal to 1 x 1017at/cm3 and less than or equal to 1 x 1020at/cm3.
In a similar field of endeavor, Liu teaches that the second concentration (of second layer 91; Fig. 25B, col. 14, lines 5-10) is greater than or equal to 1 x 1017at/cm3 and less than or equal to 1 x 1020at/cm3 (col. 14, lines 20-30), in order to “reduce leakage between the epitaxial source/drain regions” (col. 14, lines 40-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Yang with the second concentration of Liu, in order to reduce leakage between the source/drain regions.
Regarding claim 5, Yang teaches the limitations of claim 4. Yang further teaches, in Fig. 16B, that the plurality of first patterns (concave areas of 248 filled by the ends of 208) include a same material as the second semiconductor material (of second layer 246) ([0018], [0030], both are silicon), and that the second pattern (the convex regions of 248 between the first patterns) includes the first semiconductor material (of source/drain region 248).
Yang does not explicitly teach that the second semiconductor material of the second layer has no conductivity.
In a similar field of endeavor, Liu teaches that the second semiconductor material of the second layer (91; Fig. 25B, col. 14, lines 5-10) has no conductivity (col. 14, lines 5-10), order to “reduce leakage between the epitaxial source/drain regions” (col. 14, lines 40-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Yang with the second layer of Liu, in order to reduce leakage between the source/drain regions.
Regarding claim 11, Yang teaches the limitations of claim 10. Yang does not explicitly teach that the upper surface of the second layer is on a level between the lower surface of the lowermost channel layer among the plurality of channel layers and an uppermost surface of the active region.
In a similar field of endeavor, Liu teaches, in Fig. 25B, that the upper surface of the second layer (91; col. 14, lines 5-10) is on a level between the lower surface of the lowermost channel layer (54A; col. 13, lines 10-15) among the plurality of channel layers (54) and an uppermost surface of the active region (66; col. 5, lines 1-10), in order to “reduce leakage between the epitaxial source/drain regions” (col. 14, lines 45-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Yang with the second layer configuration of Liu, in order to reduce leakage between the epitaxial source/drain regions (col. 14, lines 45-50).
Regarding claim 18, Yang teaches the limitations of claim 16. Yang further teaches, in Fig. 16B, that the plurality of first patterns (concave areas of 248 filled by the ends of 208) includes a same material as the second semiconductor material (of second layer 246) ([0018], [0030], both are silicon), and that the second pattern (the convex regions of 248 between the first patterns) includes the first semiconductor material (of source/drain region 248).
Yang does not explicitly teach that the second semiconductor material of the second layer has no conductivity type.
In a similar field of endeavor, Liu teaches that the second semiconductor material of the second layer (91; Fig. 25B, col. 14, lines 5-10) has no conductivity type (col. 14, lines 5-10), order to “reduce leakage between the epitaxial source/drain regions” (col. 14, lines 40-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Yang with the second layer of Liu, in order to reduce leakage between the source/drain regions.
Regarding claim 20, Yang teaches the limitations of claim 19. Yang further teaches that the second layer (246) includes second impurities different from the first impurities ([0030], “the inner layer 248 and the outer layer 246 may be doped with different dopant species”).
Yang does not explicitly teach that the second layer has a concentration greater than or equal to 1 x 1017at/cm3 and less than or equal to 1 x 1020at/cm3.
In a similar field of endeavor, Liu teaches that the second layer (91; Fig. 25B, col. 14, lines 5-10) has a concentration greater than or equal to 1 x 1017at/cm3 and less than or equal to 1 x 1020at/cm3 (col. 14, lines 20-30), in order to “reduce leakage between the epitaxial source/drain regions” (col. 14, lines 40-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Yang with the second layer concentration of Liu, in order to reduce leakage between the source/drain regions.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20220037340) in view of Chu et al. (US 20220069135).
Regarding claim 15, Yang teaches the limitations of claim 14. Yang does not explicitly teach that the side surface of the second layer includes a portion in contact with a portion of the plurality of internal spacer layers.
In a similar field of endeavor, Chu teaches, in Fig. 19A, that the side surface of the second layer (236B, [0028]) includes a portion in contact with a portion of the plurality of internal spacer layers (234, [0028]), in order to “reduce parasitic resistance in the source/drain features” ([0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Yang with the second layer configuration of Chu, in order to reduce parasitic resistance in the source/drain features ([0039]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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