DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 8-9, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over NAKANISHI (US 20190097002 A1, hereinafter Nakanishi’002) of record in view of D’Arrigo’335 (US 5168335 A, hereinafter D'Arrigo’335) of record.
Regarding independent claim 1, Nakanishi’002 teaches, “A semiconductor device (fig. 1-30; ¶ [0057] - ¶ [0146]) comprising:
a semiconductor substrate (SB, fig. 5) having a main surface (top surface) and a back surface (bottom surface) located on opposite sides to each other;
a field plate portion (FP) formed on the main surface of the semiconductor substrate (SB) via a first insulating film (FiF, TiF);
a second insulating film (iF) formed on the main surface of the semiconductor substrate (SB) so as to cover the first insulating film (FiF, TiF) and the field plate portion (FP);
a first metal pattern (FCW) and a second metal pattern (SCW) formed on the second insulating film (iF); and
an insulating protective film (PF, MB) formed on the second insulating film (iF) so as to cover the first metal pattern (FCW) and the second metal pattern (SCW),
wherein each of the first metal pattern (FCW) and the second metal pattern (SCW) is electrically connected to the field plate portion (FP),
wherein each of the first metal pattern (FCW) and the second metal pattern (SCW) is thicker than the field plate portion (FP),
wherein the field plate portion (FP) is made of polycrystalline silicon (¶ [0083]), and
((wherein the second insulating film is composed of a stacked film of a first silicon oxide film, a first silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the first silicon nitride film,
wherein the first silicon oxide film is in contact with the field plate portion (FP), and
wherein a thickness of the field plate portion is thicker than a thickness of the first silicon oxide film))”.
PNG
media_image1.png
516
724
media_image1.png
Greyscale
But Nakanishi’002 is silent upon the provision of wherein the second insulating film is composed of a stacked film of a first silicon oxide film, a first silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the first silicon nitride film,
wherein the first silicon oxide film is in contact with the field plate portion, and
wherein a thickness of the field plate portion is thicker than a thickness of the first silicon oxide film.
However, D'Arrigo’335 teaches a similar semiconductor device (fig. 7) wherein the second insulating film (44, ONO layer) is composed of a stacked film of a first silicon oxide film (bottom Silicon oxide film of ONO), a first silicon nitride film (middle silicon nitride film of ONO) on the first silicon oxide film, and a second silicon oxide film (top Silicon oxide film of ONO) on the first silicon nitride film,
wherein the first silicon oxide film (O of ONO) is in contact with the field plate portion (48), and (also, referring to fig. 5 of primary prior art Nakanishi’002, bottom surface of second insulating film (iF) is in direct contact with field plate portion (FP), thus bottom Silicon oxide film of ONO will be in direct contact with field plate portion (FP))
wherein a thickness of the field plate portion (48) is thicker than a thickness of the first silicon oxide film (44).
PNG
media_image2.png
371
1114
media_image2.png
Greyscale
Regarding claim 8, Nakanishi’002 modified with D’Arrigo’335 further teaches, “The semiconductor device according to claim 1,
wherein the protective film (PF, fig. 5, Nakanishi’002) is in contact with the first metal pattern (FCW) and the second metal pattern (SCW), and
wherein the protective film (PF) does not include a silicon nitride film (¶ [0075])”.
Regarding claim 9, Nakanishi’002 modified with D’Arrigo’335 further teaches, “The semiconductor device according to claim 8, wherein the protective film (PF, MB, fig. 5, Nakanishi’002) is a film in an uppermost layer”.
Regarding claim 11, Nakanishi’002 modified with D’Arrigo’335 further teaches, “The semiconductor device according to claim 1,
wherein an element region (DR, fig. 2, Nakanishi’002) in which a semiconductor element is formed is arranged in a central part of the main surface of the semiconductor substrate (SB),
wherein the first metal pattern (FCW, fig. 1) is arranged so as to surround the element region (DR) in plan view and is electrically connected to a first portion of the semiconductor substrate (left upper corner of SB in fig. 5) exposed from the second insulating film (iF),
wherein the second metal pattern (SCW, fig. 1) is arranged so as to surround the first metal pattern (FCW) in plan view and is electrically connected to a second portion of the semiconductor substrate (right upper corner of SB in fig. 5) exposed from the second insulating film (iF),
wherein the field plate portion (FP, fig. 4) integrally includes a first conductor pattern (FCP) arranged so as to surround the element region (DR) in plan view, a second conductor pattern (SCP) arranged so as to surround the first conductor pattern (FCP) in plan view, and a third conductor pattern (TCP) arranged between the first conductor pattern (FCP) and the second conductor pattern (SCP) in plan view and connecting the first conductor pattern (FCP) and the second conductor pattern (SCP),
wherein the first metal pattern (FCW, fig. 5) is electrically connected to the first conductor pattern (FCP) of the field plate portion (FP), and
wherein the second metal pattern (SCW, fig. 5) is electrically connected to the second conductor pattern of the field plate portion (FP)”.
Regarding claim 12, Nakanishi’002 modified with D’Arrigo’335 further teaches, “The semiconductor device according to claim 11,
wherein a first electrode (EE/MCF, BCF, fig. 5; ¶ [0073], Nakanishi’002) for the semiconductor element is formed on the second insulating film (iF) on the element region,
wherein a second electrode (CE) for the semiconductor element is formed on the back surface of the semiconductor substrate (SB), and
wherein the protective film (PF, MB) covers a part of the first electrode (EE)”.
Regarding claim 13, Nakanishi’002 modified with D’Arrigo’335 further teaches, “The semiconductor device according to claim 12,
wherein the first metal pattern (FCW, fig. 5, Nakanishi’002) is electrically connected to the first electrode (EE), and
wherein the second metal pattern (SCW) is electrically connected to the second electrode (EE) through the semiconductor substrate (SB)”.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nakanishi’002 modified with D’Arrigo’335 as applied to claim 11 as above, and further in view of Shirai; Koji et al. (US 4707720 A, hereinafter Shirai’720).
Regarding claim 14, Nakanishi’002 modified with D’Arrigo’335 teaches all the limitations described in claim 11.
But Nakanishi’002 modified with D’Arrigo’335 is silent upon the provision of wherein a plurality of p-type semiconductor regions and n-type semiconductor regions are alternately arranged in the third conductor pattern along an extending direction of the third conductor pattern.
However, Shirai’720 teaches a filed plate (20, fig. 11-12; column 9 lines 3-20) comprising a plurality of p-type semiconductor regions (‘P portion’) and n-type semiconductor regions (‘N portion’) alternately arranged in the third conductor pattern (‘field plate electrode 20’) along an extending direction of the third conductor pattern.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Nakanishi’002 modified with D’Arrigo’335 and Shirai’720 to form the field plates including alternate p-type semiconductor regions and n-type semiconductor regions according to the teachings of Shirai’720 with a motivation of achieving high breakdown voltage by avoiding sharp variation of the depletion layer in the field plates. See Shirai’720, column 9 lines 3-20 for details.
Response to Arguments
Applicant's arguments filed 04/20/2026 have been fully considered but they are not persuasive.
Applicant argues:
[Page 9] of REMARKS,
Applicant respectfully submits that the cited references, taken individually or in combination, fail to disclose or suggest the features of amended independent claim 1, particularly with respect to the features of "wherein a thickness of the field plate portion is thicker than a thickness of the first silicon oxide film."
Examiner’s reply:
The office disagrees.
Referring to fig. 7 of D’Arrigo’335, wherein a thickness of the field plate portion (48, ‘field plate conductor’) is thicker than a thickness of the first silicon oxide film (44, ‘a oxide/nitride/oxide (ONO) sandwich’, Thickness of element 48 is larger than element 44, first silicon oxide film is one part of the element 48, thus field plate 48 will be thicker than the bottom silicon oxide film of the ONO layer 44).
PNG
media_image2.png
371
1114
media_image2.png
Greyscale
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Prosecution Insights