DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, Fig. 6, claims 1-15 and 20 in the reply filed on May 26, 2026 is acknowledged.
Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 26, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 5, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Metzler et al. (US 9,817,122).
Regarding claim 1, Metzler et al. disclose: at least one light emitter device (3); a logic block (53) configured to accept a plurality of indicator inputs (33, 34) and to provide an output signal (output signal to switch 13) (Fig. 6, col. 10, lines 11-56); a laser driver circuit (10, 13, 14) electrically coupled to the at least one light emitter device (3), wherein the laser driver circuit comprises: at least one switch (13); and a logical gate (14) configured to accept a first input and a second input (pulse generator 14, which actuates the switch 13 and determines the pulse sequence (for example: on time, off time, pulse repetition rate, pulse duty factor, burst duty factor, burst repetition rate, pulses per burst, etc.). This can be configured and triggered via a communications interface (for example single-wire interface, SSI, SPI, I2C, UART, . . . ) instead of or in addition to the lines 33/34 from the superordinate controller 53), wherein the output signal is coupled to the second input (output signal coupled to line 34), wherein the laser driver circuit is configured to: cause a drive current to flow through the at least one switch when the first input and the second input correspond to a predetermined trigger combination, wherein the drive current causes the at least one light emitter device to emit at least one light pulse (pulse generator 14 controls the switch 13 and causes the laser diode 3 to emit a laser pulse) (Fig. 6, col. 10, lines 11-56).
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Fig. 6 of Metzler
Regarding claim 3, Metzler et al. disclose: wherein the logic block and the logical gate are configured to operate continuously and independently from a clock source (there are no clock sources in the device of Fig. 6) (Fig. 6, col. 10, lines 11-56).
Regarding claim 4, Metzler et al. disclose: wherein the first input (34) comprises a laser trigger input pulse (enable input 34 suppresses or allows the provision of the laser supply voltage) (Metzler, Fig. 6, col. 10, lines 37-41).
Regarding claim 5, Metzler et al. disclose: wherein the at least one light emitter device comprises a laser diode (laser diode 3) (Fig. 6, col. 10, lines 11-56).
Regarding claim 11, Metzler et al. disclose: further comprising a lock out circuit (51), wherein the lock out circuit is configured to: determine a fault condition (short circuit); and in response to determining the fault condition, disable the laser drive circuit or the at least one light emitter device for a predetermined amount of time or until the fault condition is cleared (Fig. 6, col. 10, lines 11-56).
Regarding claim 20, the apparatus of claim 1 discloses the claimed method (see the rejection of claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Metzler et al. (US 9,817,122) in view of Schultz (US 7,368,940).
Regarding claim 2, Metzler et al. do not disclose: wherein the logic block and the logical gate comprise analog circuit elements or one or more field-programmable gate arrays (FPGAs).
Schultz discloses: analog circuits 402 can include any or all of the following logic blocks: input/output blocks (IOBs); multi-gigabit transceivers (MGTs); digital clock managers (DCMs); digitally controlled impedance (DCI) circuitry; system monitors; analog-to-digital (A/D) converters (col. 6, lines 53-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Metzler by forming the logic blocks and logic gates with analog circuit element in order to increase device reliability.
Regarding claim 6, Metzler et al. do not disclose: wherein the logic block comprises an analog multi-input logic block.
Schultz discloses: analog circuits 402 can include any or all of the following logic blocks: input/output blocks (IOBs); multi-gigabit transceivers (MGTs); digital clock managers (DCMs); digitally controlled impedance (DCI) circuitry; system monitors; analog-to-digital (A/D) converters (col. 6, lines 53-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Metzler by forming the logic block comprising an analog multi-input logic block in order to increase device reliability.
Regarding claim 8, Metzler as modified disclose: wherein the plurality of indicator inputs comprises at least one of: a capacitor undervoltage indicator signal; a capacitor overvoltage indicator signal; an angular velocity out-of-range indicator signal; a device temperature out-of-range indicator signal; an angular velocity out-of-range indicator signal; or an enable indicator signal (enable input 34) (Metzler, Fig. 6, col. 10, lines 11-40).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Metzler et al. (US 9,817,122) in view of Harel et al. (CN 113692540).
Regarding claim 9, Metzler et al. do not disclose: wherein the at least one switch comprises a Transistor (Metzler, col. 10, lines 54-56).
Metzler et al. do not disclose: a Gallium Nitride-based Field Effect Transistor (GaNFET).
Harel et al. disclose: Gallium Nitride-based Field Effect Transistor (GaNFET) (claim 16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Metzler by using a GaNFET as the switch in order to increase the switching speed of the device.
Regarding claim 10, Metzler et al. do not disclose: wherein the laser driver circuit comprises a Low-Side GaN Driver or a High-Side GaN Driver.
Harel et al. disclose: a high-side and low-side GaN FET driver circuit 600 for a combination of laser diodes (page 11, first paragraph) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Metzler by designing the laser driver circuit using a Low-Side GaN Driver or a High-Side GaN Driver in order to increase the switching speed of the device.
Allowable Subject Matter
Claims 7, 12, 13, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 is allowable as the prior art fails to anticipate or render obvious the claimed limitations including “…wherein the logic block comprises a multi-input AND gate or a multi-input OR gate.”
Claim 12 is allowable as the prior art fails to anticipate or render obvious the claimed limitations including “…wherein the logic block further comprises a verification input, wherein the logic block is configured to conduct a self-test procedure in response to receiving a verification signal by way of the verification input.”
Claim 13 is allowable as the prior art fails to anticipate or render obvious the claimed limitations including “…wherein the logic block is configured to determine a fault condition, wherein the fault condition is based on a maximum permissible exposure of laser light.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Saha (US PG Pub 2017/0285078) discloses: a device such as a laser diode is provided with a monitoring arrangement. The monitoring arrangement has voltage to current convertors arranged to provide respectively currents which are proportional to the respective voltages on an anode and on a cathode of the laser diode. The monitoring arrangement provides a first output signal when the laser diode is on too long. That output signal is used to cause the laser diode to be switched off (Abstract). Ichikawa et al. (US PG Pub 2016/0156152) disclose: a lighting circuit is configured to turn on or off a semiconductor light source in accordance with a turning-on/off instruction signal. The lighting circuit includes a pulse input determining circuit and a drive circuit. The pulse input determining circuit receives the turning-on/off instruction signal which is in pulse form in commanding turning-on and which is at a constant level in commanding turning-off. The pulse input determining circuit determines whether or not the turning-on/off instruction signal is in a turn-on state in which the turning-on/off instruction signal is in pulse form. The pulse input determining circuit generates a determination signal which is asserted if the turning-on/off instruction signal is in pulse form. The drive circuit supplies the semiconductor light source with a drive current if the determination signal is asserted. The drive circuit does not supply the semiconductor light source with the drive current if the determination signal is negated (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINNING(TOM) NIU whose telephone number is (571)270-1437. The examiner can normally be reached M-F: 9:30am-6:00pm.
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/XINNING(Tom) NIU/Primary Examiner, Art Unit 2828
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