DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 through 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a first semiconductor layer, wherein the first semiconductor layer is disposed on a first die” in lines 1 and 2. The specification as filed does not support a first semiconductor layer disposed on a semiconductor die, but rather that the first semiconductor layer is a first die, see also claim 8. As such, the specification as filed does not support the semiconductor die and the semiconductor layer to be distinguishable or adjacent structures.
Claim 14 recites “a first semiconductor layer, wherein the first semiconductor layer is disposed on a first die” in lines 3 and 4. The specification as filed does not support a first semiconductor layer disposed on a semiconductor die, but rather that the first semiconductor layer is a first die, see also claim 8. As such, the specification as filed does not support the semiconductor die and the semiconductor layer to be distinguishable or adjacent structures.
Claims 2 through 13 and 15 through 17 are rejected as being dependent on and incorporating claims1 and 14.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a first semiconductor layer, wherein the first semiconductor layer is disposed on a first die” in lines 1 and 2.
Claim 14 recites “a first semiconductor layer, wherein the first semiconductor layer is disposed on a first die” in lines 3 and 4.
The claims are unclear and ambiguous because the specification and accompanying figures do not support a semiconductor layer being on a first die, but rather that the semiconductor layer is a first die (see us pgpub 2023/0104555 paragraph 20). It is therefore unclear what the claim comprises. For the purpose of examination, the semiconductor layer will be understood to be a first die.
Claims 2 through 13 and 15 through 17 depend from and incorporate claims 1 and 14.
Claim 8 recites “the first semiconductor layer is the first die or a first interconnection layer” in lines 1 and 2. The phrase is ambiguous because it is unclear whether the semiconductor layer is a separate element
Claim 9 recites “the first semiconductor layer is the first die” in lines 1 and 2. The phrase is ambiguous because it is unclear whether the semiconductor layer is a separate element.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 4, 8, 9, 10, 11, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 2016/0260687) in view of Nakano (US 2020/0211996)
Regarding claim 1.
Gao teaches a semiconductor apparatus, comprising: a first semiconductor layer (202,200) (fig 2f), wherein the first semiconductor layer is disposed on a first die (200) (fig 2g) (paragraph 29); a second die (200) (fig 2) (paragraph 30); a thermally conductive layer (210) stacked with the first semiconductor layer (202,200) (paragraph 24) and the second die (200) and located between the first semiconductor layer (202,200) and the second die (200), the thermally conductive layer (210) being configured to conduct heat from at least one of the first semiconductor layer or the second die at the thermally conductive layer (paragraph 25), wherein a coefficient of thermal conductivity of the thermally conductive layer in a horizontal direction is greater than or equal to a coefficient of thermal conductivity in a vertical direction (paragraph 21,22, note graphene, graphite and nanotubes are materials that have a greater horizontal coefficient of thermal conductivity than vertical coefficient of thermal conductivity [graphite for example has a vertical coefficient of thermal conductivity of about 20 W/mK and a horizontal coefficient of thermal conductivity of over 300 w/mK (see Miller (US 2016/0302260) Table 5 paragraph 257 for reference)] the material properties of graphite or graphene are inherent to the material and recognition of such properties does not confer patentability. MPEP 2112);
PNG
media_image1.png
464
731
media_image1.png
Greyscale
a first insulation layer (216) disposed on a lower surface and a side surface of the thermally conductive layer (210); a second [adhesive] layer (208) disposed on an upper surface of the thermally conductive layer (210); and a first conductive pillar (204,218) penetrating through the thermally conductive layer (210) (paragraph 28), so that the first semiconductor layer (202,200) and the second die (200) are electrically interconnected by using the first conductive pillar (204,218) (fig 2e,2g) (paragraph 27,30), wherein the first conductive pillar (204,218) is electrically insulated from the thermally conductive layer (210) (fig 2e) (paragraph 27), wherein an extension direction of the first conductive pillar is the vertical direction (fig 2g), and wherein the coefficient of thermal conductivity of the thermally conductive layer in the horizontal direction is greater than a coefficient of thermal conductivity of the first semiconductor layer (paragraph 22).
PNG
media_image2.png
504
774
media_image2.png
Greyscale
Gao does not teach the adhesive layer is an insulating layer.
Nakano teaches providing an adhesive layer that is an insulating layer (106) (fig 16) (paragraph 54)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the adhesive layer to be an insulating layer because insulating resins, such as epoxy, have adhesive properties that are capable of bonding together substrates, and the insulating properties will prevent possible short circuits and leakage currents.
Regarding claim 2.
Gao in view of Nakano teaches elements of the claim 1
Gao teaches there are a plurality of vias (213) at the thermally conductive layer (210), and wherein the first conductive pillar (204,218) penetrates through one of the plurality of vias (213) (fig 2d,2e) (paragraph 27,28).
Regarding claim 3.
Gao in view of Nakano teaches elements of the claim 1
Gao teaches there is a bonding- based connection (206,220) between the thermally conductive layer (210) and the first semiconductor layer (202,200) (fig 2f,2g) (paragraph 28,30).
Regarding claim 4.
Gao in view of Nakano teaches elements of the claim 1
Gao teaches an insulating material (234) covering a surface of the thermally conductive layer (210), wherein the first conductive pillar further penetrates through the insulating material (234) (fig 2g) (paragraph 30).
PNG
media_image3.png
517
709
media_image3.png
Greyscale
Regarding claim 8
Gao in view of Nakano teaches elements of the claim 1
Gao teaches the first semiconductor layer (202,200) (fig 2d) is the first die (200) (fig 2g) or a first interconnection layer (paragraph 27).
Regarding claim 9.
Gao in view of Nakano teaches elements of the claim 1
Gao teaches the first semiconductor layer (202,200) is the first die (fig 2a,2g) (paragraph 27,30), and wherein the first conductive pillar (204,218) further penetrates through the first die (202,200) (fig 2e,2g) (paragraph 27).
Regarding claim 10.
Gao in view of Nakano teaches elements of the claim 9
Gao teaches a side semiconductor layer (200), disposed on a side of the first semiconductor layer (202,200) far away from the thermally conductive layer (210) and electrically coupled to the conductive pillar (204,218) (fig 2e,2g).
PNG
media_image4.png
505
948
media_image4.png
Greyscale
Regarding claim 11.
Gao in view of Nakano teaches elements of the claim 1
Gao teaches the thermally conductive layer (210) comprises a carbon-based material, a metal material, or a combination thereof (paragraph 25).
Regarding claim 12.
Gao in view of Nakano teaches elements of the claim 11
Gao teaches the carbon-based material comprises a graphene film (paragraph 25).
Claim 13.
Gao in view of Nakano teaches elements of the claim 1
Gao teaches a thickness of the thermally conductive layer is at least 5um (paragraph 25).
Note the claimed range and the prior art range substantially overlap and are therefore prima facie obvious. In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997. "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). MPEP 2144.05
Claim(s) 14, 15, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 2016/0260687) in view of Nakano (US 2020/0211996).
Regarding claim 14.
Gao teaches an electronic device comprising a semiconductor apparatus, the semiconductor apparatus comprising (fig 2g): a first semiconductor layer (202,2g), wherein the first semiconductor layer (202,200) is disposed on a first die (fig 2e,2g) (paragraph 27); a second die (200) (paragraph 30); a thermally conductive layer (210) stacked with the first semiconductor layer (202,200) and the second die (200) and located between the first semiconductor layer (202,200) and the second die (200) (fig 2g) (paragraph 30), the thermally conductive layer (210) being configured to conduct heat from at least one of the first semiconductor layer (202,200) or the second die (200) at the thermally conductive layer (210) (paragraph 25), wherein a coefficient of thermal conductivity of the thermally conductive layer in a horizontal direction is greater than or equal to a coefficient of thermal conductivity in a vertical direction (paragraph 21,22, note graphene, graphite and nanotubes are materials that have a greater horizontal coefficient of thermal conductivity than vertical coefficient of thermal conductivity [graphite for example has a vertical coefficient of thermal conductivity of about 20 W/mK and a horizontal coefficient of thermal conductivity of over 300 w/mK (see Miller (US 2016/0302260) Table 5 paragraph 257 for reference)] the material properties of graphite or graphene are inherent to the material and recognition of such properties does not confer patentability. MPEP 2112)); a first insulation layer (216) disposed on a lower surface and a side surface of the thermally conductive layer (210); a second [adhesion] layer (208) disposed on an upper surface of the thermally conductive layer (210); and
PNG
media_image5.png
565
616
media_image5.png
Greyscale
a first conductive pillar (204,218) penetrating through the thermally conductive layer (210) (fig 2e) (paragraph 27), so that the first semiconductor layer (202,200) and the second die (200) are electrically interconnected by using the first conductive pillar (218,204) (fig 2g) (paragraph 27), wherein the first conductive pillar (204,218) is electrically insulated from the thermally conductive layer (210) (paragraph 27), wherein an extension direction of the first conductive pillar (204,218) is the vertical direction, and wherein the coefficient of thermal conductivity of the thermally conductive layer (210) in the horizontal direction is greater than a coefficient of thermal conductivity of the first semiconductor layer (202) (paragraph 25) (fig 2e) .
PNG
media_image6.png
528
711
media_image6.png
Greyscale
Gao does not teach the adhesive layer is an insulating layer.
Nakano teaches providing an adhesive layer that is an insulating layer (106) (fig 16) (paragraph 54)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the adhesive layer to be an insulating layer because insulating resins, such as epoxy, have adhesive properties that are capable of bonding together substrates, and the insulating properties will prevent possible short circuits and leakage currents.
Regarding claim 15
Gao in view of Nakano teaches the structure of claim 14.
Gao teaches there are a plurality of vias (213) at the thermally conductive layer (210) (paragraph 26), and wherein the first conductive pillar (204,218) penetrates through one of the plurality of vias (213) (fig 2e) (paragraph 27).
Regarding claim 16.
Gao in view of Nakano teaches the structure of claim 14.
Gao teaches there is a bonding-based connection (206,220) between the thermally conductive layer (210) and the first semiconductor layer (200) (fig 2g) (paragraph 28,30).
Regarding claim 17.
Gao in view of Nakano teaches the structure of claim 14.
Gao teaches an insulating material (234) covering a surface of the thermally conductive layer (210), and the first conductive pillar (204,218) further penetrates through the insulating material (234) (fig 2g) (paragraph 30).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that Gao (US 2016/0260687) does not anticipate the claims, particularly a first insulation layer is on the lower surface and side surface of the thermally conductive layer.
However, as noted above Gao teaches this element, see annotated figure in the rejection of claim 1, when considered in combination with Nakano.
Allowable Subject Matter
Claims 5, 6 and 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art does not teach A semiconductor apparatus, comprising: a first die; a thermally conductive layer stacked with the first semiconductor layer, wherein a coefficient of thermal conductivity of the thermally conductive layer in a horizontal direction is greater than or equal to a coefficient of thermal conductivity in a vertical direction; a first insulation layer disposed on a lower surface and a side surface of the thermally conductive layer; a second insulation layer disposed on an upper surface of the thermally conductive layer; and a first conductive pillar penetrating through the thermally conductive layer, , wherein the first conductive pillar is electrically insulated from the thermally conductive layer, an insulation layer disposed to at least partially surround the first conductive pillar and extend along the first conductive pillar, the insulation layer being configured to isolate the first conductive pillar from the thermally conductive layer to implement electrical insulation.
Particularly note the precise configuration of the multiple insulating layers with respect to the thermally conductive layer, the conductive pillar and the semiconductor layer in combination with all other elements of the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 23, 2026