CTNF 18/063,950 CTNF 89298 DETAILED ACTION This Office Action is sent in response to Applicant’s Communication received 09 Dec 2022 for application number 18/063,950. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims. Claims 1-20 are presented for examination; elected claims 12-17 and 19-20 are examined below; non-elected claims 1-11 and 18 have been withdrawn. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 09 Dec 2022 and 17 Apr 2026 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of claims 12-20 in the reply filed on 25 Feb 2026 is acknowledged. Further, claim 18 has been withdrawn as it is directed to an invention that is independent or distinct from the invention originally claimed from claim 12, for the following reasons: claim 12 claims gate structures which extend vertically to a main extension direction, whereas claim 18 is directed towards a buried gate structure. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 18 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 13, 17, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 07-34-05 AIA Claim 13 recites the limitation " said third semiconductor material " in lines 3-4 . There is insufficient antecedent basis for this limitation in the claim. Claim 17 recites the limitation "the oxide" in line 2. There is insufficient antecedent basis for this limitation in the claim. Dependent claims 19-20 are rejected because they inherit the deficiency. 07-34-05 AIA Claim 20 recites the limitation " said isolator substrate " in lines 2 and 4 . There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 12, 16-17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kriekoucki et al. [hereinafter as Kriekouki] (WO 2024/023397 A1) . In reference to claim 12 , Kriekouki teaches A structured semiconductor device comprising: isolated coupled quantum dots defining a physical spin qubit [para 0003, 0034, 0111, 0113, 0129 disclose implementing a qubit via quantum dots] , wherein the structured semiconductor device comprises: a silicon structure [gate 114; Fig. 5, para 0045] on an isolator [insulating layer 102; Fig. 5, para 0050] building a source area [semiconductor region 110; Fig. 5, para 0045] ; a linear structure [grids 114/116; Fig. 5, para 0042] on an isolator [102] , wherein said linear structure [114/116] extends from said source area [110] , wherein said linear structure [114/116] has a width which is smaller [width of 114/116 smaller than width of 110] than a main area of said source area [110] , wherein said linear structure comprises: a first area [114 side of 114/116] of a first semiconductor material, and a separated second area of said first semiconductor material [116 side of 114/116] , an array of regularly spaced at least two thin, free-standing segments [grids 112A, 112B, 112C] having a same lateral cross section as said first area [114 side of 114/116] and said second area [116 side of 114/116] of said first semiconductor material, wherein said segments of said array [112A/112B/112C] are located on said isolator [102] , wherein said segments [112A/112B/112C] are isolated from each other by a dielectric material [spaces e1/e2/e4; Fig. 5, para 0106; the spaces act as dielectric material] , and gate structures [gates 122A/B, 126A/B; Fig. 5, para 0107] extending vertically to a main extension direction of said linear structure [114/116] , wherein said gate structures [122A/B, 126A/B] are isolated from said linear structure [114/116] , and wherein said gate structures [122A/B, 126A/B] define at least a first and a second gate area [for instance, 122A/B and 126A/B, 122A/126A and 122B/126B] , such that said array of said at least two thin, free-standing segments [112A/112B/112C] define at least two quantum dots as a basis for at least one physical spin qubit [para 0003, 0034, 0111, 0113, 0129 disclose implementing a qubit via quantum dots] . In reference to claim 16 , Kriekouki teaches The device according to claim 12, further comprising: gate structures [122A/B, 126A/B] separate and adjacent to alternating sides of said array of said quantum dots [122A/B, 126A/B are on either side of 112A/112B/112C] . In reference to claim 17, Kriekouki teaches The device according to claim 12, wherein said gate structures [122A/B, 126A/B] are fin-like structures [122A/B, 126A/B are fin-like] that extend vertically away from said main extension direction of said linear structure [114/116] on the oxide . In reference to claim 19, Kriekouki teaches The device according to claim 17, further comprising: a metal source contact [contact 115; Fig. 5, para 0044] on said first area of said first semiconductor material [114 side of 114/116] ; and a metal drain contact [contact 117; Fig. 5, para 0049] on said second area of said first semiconductor material [116 side of 114/116] . In reference to claim 20, Kriekouki teaches The device according to claim 17, further comprising: a first metallic gate contact [contact 124; Fig. 5, para 0059] over said isolator substrate [102] , wherein said first metallic gate contact [124] is in electrical contact with a first gate structure of said gate structures [122, for example] ; and a second metallic gate contact [contact 128; Fig. 5, para 0070] over said isolator substrate [102] , wherein said second metallic gate contact [128] is in electrical contact with a second gate structure of said gate structures [128, for example] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kriekouki in view of Holmes et al. [hereinafter as Holmes] (US 2021/0130944 A1) . In reference to claim 13 , Kriekouki teaches the invention of claim 12. However, Kriekouki does not explicitly teach The device according to claim 12, wherein said first semiconductor material is different to said second semiconductor material, said second semiconductor material is different to said third semiconductor material, and wherein said first, said second, and said third semiconductor material are different to silicon . Holmes teaches wherein said first semiconductor material is different to said second semiconductor material, said second semiconductor material is different to said third semiconductor material, and wherein said first, said second, and said third semiconductor material are different to silicon [paras 0036, 0071 disclose that the semiconductor layer may include a combination of InGaAs and InAs, or other materials, for example] . It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kriekouki and Holmes before the effective filing date of the claimed invention, to include the semiconductor materials as disclosed by Holmes into the semiconductor device of Kriekouki in order to obtain a semiconductor device that utilizes a combination of different semiconductor materials. One of ordinary skill in the art would be motivated to obtain a semiconductor device that utilizes a combination of different semiconductor materials to provide the predictable result of producing highly sensitive spin qubits by creating hybrid semiconductor-superconductor structures. In reference to claim 14 , Kriekouki teaches the invention of claim 12. However, Kriekouki does not explicitly teach The device according to claim 12, wherein said first semiconductor material is InGaAs . Holmes teaches wherein said first semiconductor material is InGaAs [paras 0036, 0071 disclose that the semiconductor layer may include a combination of InGaAs and InAs, or other materials, for example] . It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kriekouki and Holmes before the effective filing date of the claimed invention, to include the semiconductor materials as disclosed by Holmes into the semiconductor device of Kriekouki in order to obtain a semiconductor device that utilizes InGaAs as a semiconductor material. One of ordinary skill in the art would be motivated to obtain a semiconductor device that utilizes InGaAs as a semiconductor material to provide the predictable result of providing excellent electrical gating. In reference to claim 15, Kriekouki teaches the invention of claim 12. However, Kriekouki does not explicitly teach The device according to claim 12, wherein said second semiconductor material is InAs . Holmes teaches wherein said second semiconductor material is InAs [paras 0036, 0071 disclose that the semiconductor layer may include a combination of InGaAs and InAs, or other materials, for example] . It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kriekouki and Holmes before the effective filing date of the claimed invention, to include the semiconductor materials as disclosed by Holmes into the semiconductor device of Kriekouki in order to obtain a semiconductor device that utilizes InAs as a semiconductor material. One of ordinary skill in the art would be motivated to obtain a semiconductor device that utilizes InAs as a semiconductor material to provide the predictable result of providing a material with a strong spin-orbit coupling and a large g-factor. Examiner’s Note 07-96 AIA The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0) . Choi et al. (WO-2006083112-A1) discloses a spin-qubit based device with source and linear portions with lateral gates [Fig. 1]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW CHUNG/ Examiner, Art Unit 2898 Application/Control Number: 18/063,950 Page 2 Art Unit: 2898 Application/Control Number: 18/063,950 Page 3 Art Unit: 2898 Application/Control Number: 18/063,950 Page 4 Art Unit: 2898 Application/Control Number: 18/063,950 Page 5 Art Unit: 2898 Application/Control Number: 18/063,950 Page 6 Art Unit: 2898 Application/Control Number: 18/063,950 Page 7 Art Unit: 2898 Application/Control Number: 18/063,950 Page 8 Art Unit: 2898 Application/Control Number: 18/063,950 Page 9 Art Unit: 2898 Application/Control Number: 18/063,950 Page 10 Art Unit: 2898
Prosecution Insights