DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/23/2026 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 3/23/2026. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 2, 4 and 9-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ando et al. (US 10,879,308) in view of Lilak et al. (US 2020/0294998).
Re claim 1, Ando teaches, under BRI, Figs. 2, 15 & 17, abstract, cols. 11-12, a semiconductor structure comprising:
-a non-stacked transistor (FET4) having a frontside and a backside, wherein the non-stacked transistor (FET4) is devoid of having another transistor stacked above and below the non-stacked transistor (FET4);
-a stacked transistor (FET2, FET3) located laterally adjacent to the non-stacked transistor (FET4) and having a frontside and a backside, the stacked transistor (FET2, FET3) comprising two or more transistors stacked one atop the other; and
-a frontside interconnect (local interconnect) located on the frontside of both the non-stacked transistor (FET4) and the stacked transistor (FET2, FET3).
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Ando does not teach a backside interconnect located on the backside of both the non-stacked transistor and the stacked transistor.
Lillak teaches, Fig. 1A, a backside contact region (103) located on backside of transistors (in device regions).
As taught by Lilak, one of ordinary skill in the art would utilize & modify the above teaching into Ando to obtain a backside interconnect located on the backside of both the non-stacked transistor and the stacked transistor as claimed, because it aids in achieving desired backside contact structure & facilitating electrical connections of the formed integrated structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lilak in combination Ando due to above reason.
Re claim 2, Ando teaches, Fig. 17, cols. 11-12, wherein the frontside interconnect comprises a multilayered frontside interlayer dielectric (ILD) material structure (1502, 1602) having frontside contact structures (e.g., local interconnect, vias, Vss) embedded therein, and a frontside back-end-of-the-line (BEOL) structure (Vdd interconnect 1710) located on the multilayered frontside ILD material structure (1502, 1602) (see similar teaching in Lilak’s Fig. 1A).
Re claim 4, Ando teaches, in view of Fig. 17, wherein the frontside contact structures comprise a first frontside gate contact structure (V- gate contact) electrically connecting a gate structure of the non-stacked transistor (FET4) to the frontside BEOL structure (1710), a second gate contact structure (middle gate contact) electrically connecting a gate structure of each of the transistors of the stacked transistor (FET2, FET3) to the frontside BEOL structure (1710), a first frontside source/drain contact structure (right via) electrically connecting a first source/drain region (502) of the non-stacked transistor (FET4) to the frontside BEOL structure (1710), and a second frontside source/drain contact structure (center or left via) electrically connecting a first source/drain region and a second source/drain region of a first transistor of the two or more transistors of the stacked transistor (FET2, FET3) to the frontside BEOL structure (1710) (see similar teaching in Lilak’s Fig. 1A).
Re claim 9, Ando teaches, Fig. 2, wherein the non-stacked transistor (FET4) is a nanosheet transistor (nanosheet FET).
Re claim 10, Ando teaches, Fig. 15, the two or more transistors of the stacked transistors (FET2, FET3) are nanosheet transistors.
Re claim 11, Ando teaches, Fig. 15, a dielectric structure (isolation spacer 504) separating each nanosheet transistor.
Re claim 12, in combination cited above, Lilak teaches, Figs. 1A, 3A & 9D, [0018, 0019, 0045], the dielectric structure comprises a dielectric gate cut pillar (127B), a middle dielectric isolation layer (106), a stacked device gate spacer (123), and a bottom dielectric isolation layer (127A), wherein a first end (left) of the middle dielectric isolation layer (106) is connected to the dielectric gate cut pillar (127B), and a second end (right) of the middle dielectric isolation layer (106) is connected to the bottom dielectric isolation layer (127A) by the stacked device gate spacer (123), and the dielectric gate cut pillar (127B) contacts the frontside interconnect (105) and the bottom dielectric isolation layer (127A) contacts the backside interconnect (103).
Re claim 13, in combination cited above, Lilak teaches, under BRI, Fig. 1A, the middle dielectric isolation layer (106) and the bottom dielectric isolation layer (127A) are orientated parallel to (side & bottom) each semiconductor material nanosheet (116) of each nanosheet transistor of the two or more transistors of the stacked transistor (right two transistors), and the dielectric gate cut pillar (127B) and the stacked device gate spacer (123) are orientated perpendicular (upper or lower surface) to each semiconductor material nanosheet (116) of each nanosheet transistor of the two or more transistors of the stacked transistor.
Re claim 14, Ando teaches wherein each of the two or more transistors of the stacked transistor (FET2, FET3) is of a same conductivity type (e.g., an n-type or p-type transistor is desired, col. 9, 1st par.) (see similar teaching in Lilak’s [0015]).
Re claims 15 & 16, in combination cited above, Lilak teaches the two or more transistors of the stacked transistor comprise a top transistor having a first conductivity type (n-type) and a bottom transistor having a second conductivity type (p-type) that is different from the first conductivity type, wherein the first conductivity type is n-type, and the second conductivity type is p-type [0015].
Re claim 17, in combination cited above, Lilak teaches the first conductivity type is p-type, and the second conductivity type is n-type [0015].
Re claim 18, Ando teaches, Fig. 15, wherein the non-stacked transistor (FET4) and the stacked transistor (FET2, FET3) have a same device height, and the non-stacked transistor (FET4) has an upper surface and a lower surface, wherein the upper surface of the non-stacked transistor (FT4) is coplanar with an upper surface of the stacked transistor (FET2, FET3), and the lower surface of the non-stacked transistor (FET4) is coplanar with a lower surface of the stacked transistor (FET2, FET3).
Re claim 19, Ando teaches, Figs. 2, 12 & 15, wherein non-stacked transistor (FET4) includes a vertically stacked semiconductor nanosheets (nanosheet channels), and each of the transistors of the stacked transistor (FET2, FET3) includes a vertically stacked semiconductor nanosheets (lower and upper nanosheets), wherein a total number of vertically stacked semiconductor nanosheets of the non-stacked transistor (FET4) is equal to, or greater than, a total number of vertically stacked semiconductor nanosheets of the two or more transistors of the stacked transistor (FET2, FET3).
4. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ando as modified by Lilak as applied to claims 1-2 above, and in view of Cheng et al. (US 2020/0075661).
The teachings of Ando/Lilak have been discussed above.
Re claim 3, Ando/Lilak does not explicitly teach a carrier wafer located on the front side BEOL structure.
Cheng teaches, Fig. 2I, [0019], a carrier wafer (170) located on the front side BEOL structure (150).
As taught by Cheng, one of ordinary skill in the art would utilize the above teaching to obtain a carrier wafer located on the front side BEOL structure as claimed, because carrier wafer is known & widely used in the art to facilitate supporting devices/structures during manufacturing process.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination with Ando/Lilak due to above reason.
5. Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ando as modified by Lilak as applied to claims 1, 2 & 4 above, and further in view of Chen (US 2022/0320299).
The teachings of Ando/Lilak have been discussed above.
Re claim 5, in combination cited above, Lilak teaches, Fig. 1A, [0028], the backside interconnect (103) comprises a first backside metal level comprising a plurality of first backside electrically conductive structures (138, 128).
Ando/Lilak does not explicitly teach a second backside metal level located on the backside metal level and comprising a plurality of second backside electrically conductive structures.
Chen teaches, Fig. 7, [0045, 0047], a second backside metal level (one bottom layer of 150B) located on the first backside metal level (one of upper layer of 150B) and comprising a plurality of second backside electrically conductive structures (e.g., conductive structures in bottom layer of 150B).
As taught by Chen, one of ordinary skill in the art would utilize & modify the above teaching to obtain a second backside metal level as claimed, because it aids in achieving a desired backside metal structure that facilitates interconnections in the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Ando/Lilak due to above reason.
Re claim 6, in combination cited above, Chen teaches, claim 1, Figs. 1 & 7, [0021, 0031], one of the first backside electrically conductive structures of the plurality of first backside electrically conductive structures (e.g., layers with conductive structure below transistors) is electrically connected to a second source/drain region (of left transistor) of the non-stacked transistor (left transistor) by a first backside source/drain contact structure (metal contact 140B), and at least two other first backside electrically conductive structures of the plurality of first backside electrically conductive structures (e.g., layers with conductive structure below transistors) are electrically connected to a first source/drain region and a second source/drain region of a second transistor of the two or more transistors of the stacked transistor (middle transistors) by second backside source/drain contact structures (140B).
Re claim 7, in combination cited above, Chen teaches, Figs. 1 & 7, one of the second backside electrically conductive structures (one of 150B) is electrically connected to the first backside electrically conductive structure (upper layer of 150B) that is electrically connected to the second source/drain region of the non-stacked transistor (bottom left transistor) by a first backside metal via (140B).
Re claim 8, in combination cited above, Chen teaches, Figs. 1 & 7, another one of the second backside electrically conductive structures (one of 150B) is electrically connected to the first backside electrically conductive structure (upper layer of 150B) that is electrically connected to the second source/drain region of the stacked transistor (middle transistors) by a first backside metal via (140B).
6. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ando as modified by Lilak as applied to claim 1 above, and further in view of Hwang et al. (US 2012/0132996).
The teachings of Ando/Lilak have been discussed above.
Re claim 20, Ando/Lilak does not explicitly teach the non-stacked transistor is a logic device, and the two or more transistors of the stacked transistor are static access memory (SRAM) devices.
Hwang teaches, Fig. 11, [0042], “the first transistor 56 is a logic device, and the second transistor 58 is a SRAM”.
As taught by Hwang, one of ordinary skill in the art would utilize & modify the above teaching into Lilak to obtain the non-stacked transistor is a logic device, and the two or more transistors of the stacked transistor are static access memory (SRAM) devices, because transistors are known & essential elements in various applications, and it aids in achieving provide a strained silicon structure which can control the channel strain within the high density region and the low density region.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hwang in combination with Ando/Lilak due to above reason.
Response to Arguments
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liaw (US 2021/0305401, Fig. 11) discloses a multi-gate transistor structure including a gate structure and an isolation gate structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/25/26
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