DETAILED ACTION
Election/Restrictions - NO TRAVERSE
A restriction requirement was mailed on 7/17/25.
Applicant’s election without traverse of Species I in the reply filed on 11/14/25 is acknowledged. Claims 5-6 are withdrawn.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-11, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0202500 A1 (“Chanemougame”).
Chanemougame teaches, for example:
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Chanemougame teaches:
1. A static random-access memory (SRAM) device (see e.g. Figs. 2 and 4A-4D) comprising:
a storage cell for storing a bit, the storage cell comprising a first storage transistor, a second storage transistor, a third storage transistor, and a fourth storage transistor (see e.g. Fig. 2, 202, 204, 206, 208; see e.g. Figs. 4A-4D wherein pull-up and pull-down terminology is used PU1, PU2, PD1, PD2);
a first access transistor and a second access transistor configured to control access to the storage cell for storing or reading the bit (see e.g. Fig. 2; 218, 220; see e.g. Figs. 4A-4D wherein “pass-gate” PG terminology is used for PG1 and PG2); and
a stack of layer structures comprising three layer structures (see e.g. Figs. 4B-4D);
wherein the first storage transistor and the third storage transistor of the storage cell are formed in a first layer structure of the stack of layer structures (see e.g. Figs. 4B-4D wherein e.g. 406/PU1 and 434/PU2 are formed in lower layers),
wherein the second storage transistor and the fourth storage transistor of the storage cell are formed in a second layer structure of the stack of layer structures (see e.g. Figs. 4B-4D wherein e.g. 404/PD1 and 432/PD2 are formed in middle layers above the lower layers),
wherein the second layer structure is adjacent to the first layer structure (see e.g. Figs. 4B-4D),
wherein the first access transistor and the second access transistor are formed in a third layer structure of the stack adjacent to the second layer structure (see e.g. Figs. 4B-4D wherein e.g. 402/PG1 and 430/PG2 are formed in top layers above the lower and middle layers),
wherein each layer structure of the three layer structures comprises a semiconductor material and the transistors in the layer structure are based on the semiconductor material (see e.g. “silicon” or “Si”, para 37, 50, 63, 85), and
wherein the semiconductor materials of at least two of the three layer structures are of different types from each other (p-type vs. n-type, see e.g. para 41, 42, 50, 51, etc.).
2. The SRAM device of claim 1, wherein each of the different types of the semiconductor materials comprises: a silicon-based semiconductor material, a two-dimensional (2D) semiconductor material, or an oxide semiconductor material (see e.g. “silicon” or “Si”, para 37, 50, 63, 85).
3. The SRAM device of claim 1, wherein the first layer structure and the second layer structure each comprise a silicon-based semiconductor material, and wherein the third layer structure comprises one or both of a 2D semiconductor material and an oxide semiconductor (see e.g. “silicon” or “Si”, para 37, 50, 63, 85 may be used for all transistors; furthermore, each transistor may be a “nanosheet”, see para 36, 37, 50, etc.).
4. The SRAM device of claim 3, wherein relative to a main surface of a substrate:
the first layer structure is formed above the main surface,
the second layer structure is formed above the first layer structure, and
the third layer structure is formed above the first layer structure and the second layer structure (see discussion of claim 1; see Figs. 4B-4D).
7. The SRAM device of claim 1, wherein the first layer structure is a doped layer structure of a first-conductivity type and the second layer structure is a doped layer structure of a second conductivity-type (p-type vs. n-type, see e.g. para 41, 42, 50, 51, etc.).
8. The SRAM device of claim 1, wherein the first storage transistor and the second storage transistor are arranged as a first complementary field effect transistor (CFET) (see e.g. para 50, 53, etc.).
9. The SRAM device of claim 8, wherein the third storage transistor and the fourth storage transistor are arranged as a second CFET (see e.g. para 50, 53, etc.).
10. The SRAM device of claim 9, wherein: one or both of the first CFET and the second CFET comprise an integrated silicon-based nanosheet transistor (see e.g. para 36, 37, 50, 53, etc.).
11. The SRAM device of claim 1, further comprising: a first vertical element electrically connecting a gate of the first storage transistor to a gate of the second storage transistor (the gates of the first and second storage transistors are connected together as shown in Fig. 2; furthermore, Fig. 4B shows a single gate structure, colored the same as 422 though not directly labeled, around each of 406 and 404, with a vertical portion thereof connecting them; see also e.g. para 51).
17. The SRAM device of claim 1, further comprising:
a wordline (e.g. WL or 446, see e.g. para 52 and Figs. 2, 4C, and 4D); and
a bitline (e.g. BL or 444, see e.g. para 52 and Figs. 2, 4C, and 4D) arranged in the third layer structure and connected to a source/drain of the first access transistor, and a complementary bitline (e.g. !BL or 442, see e.g. para 52 and Figs. 2, 4C, and 4D) arranged in the third layer structure and connected to the source/drain of the second access transistor.
18. The SRAM device of claim 17, wherein the wordline is arranged above the stack and electrically connected to a gate of the first access transistor and a gate of the second access transistor (see e.g. para 52 and Figs. 2, 4C, and 4D).
19. The SRAM device of claim 17, wherein the wordline is arranged between the second layer structure and the third layer structure and electrically connection to a gate of the first access transistor and a gate of the second access transistor (see e.g. para 52 and Figs. 2, 4C, and 4D).
20. A method for fabricating a static random-access memory, SRAM, device (see e.g. Figs. 2 and 4A-4D) comprising a stack of layer structures comprising three layer structures (see e.g. Figs. 4B-4D), the method comprising:
forming a first layer structure of the stack, wherein two storage transistors of a storage cell of the SRAM device are formed in the first layer structure (see e.g. Figs. 4B-4D wherein e.g. 406/PU1 and 434/PU2 are formed in lower layers);
forming a second layer structure of the stack adjacent to the first layer structure, wherein two other storage transistors of the storage cell are formed in the second layer structure (see e.g. Figs. 4B-4D wherein e.g. 404/PD1 and 432/PD2 are formed in middle layers above the lower layers);
forming a third layer structure of the stack adjacent to the second layer structure, wherein two access transistors are formed in the third layer structure (see e.g. Figs. 4B-4D wherein e.g. 402/PG1 and 430/PG2 are formed in top layers above the lower and middle layers), the two access transistors being configured to control access to the storage cell for storing or reading a bit to or from the storage cell (see e.g. Fig. 2 wherein if PG1/218 and PG2/220 are off, then no signals will reach 206, 210, 208, or 212 from 230 or 232); and
wherein each layer structure of the three layer structures comprises a semiconductor material and the transistors in the layer structure are based on the semiconductor material (see e.g. “silicon” or “Si”, para 37, 50, 63, 85), and wherein at least two of the three layer structures comprise a different type of semiconductor material (p-type vs. n-type, see e.g. para 41, 42, 50, 51, etc.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame.
Chanemougame teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
12. The SRAM device of claim 11, further comprising: a second vertical element electrically connecting a gate of the third storage transistor to a gate of the fourth storage transistor (the gates of the third and fourth storage transistors are connected together as shown in Fig. 2; furthermore, the first and second storage transistor gates can be seen in Fig. 4B, which shows a single gate structure, colored the same as 422 though not directly labeled, around each of 406 and 404, with a vertical portion thereof connecting them; see also e.g. para 51; while there is no cross-section similar to Fig. 4B to show the gate of the third and fourth transistors, by analogy, it is obvious to one of ordinary skill in the art to do so for the third and fourth gates, since the cross sections of Fig. 4C for the first and second transistors and Fig. 4D for the third and fourth transistors are similar).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
13. The SRAM device of claim 12, further comprising: a third vertical element electrically connecting a source/drain of the first storage transistor, a source/drain of the second storage transistor, and a source/drain of the first access transistor (they are connected at point 224, see Fig. 2 and para 41; see the local interconnects e.g. LI_B, 426, LI_T, 428, which are said to interconnect the source/drain regions, see e.g. para 51 and Figs. 4B-4D).
14. The SRAM device of claim 13, further comprising: a fourth vertical element electrically connecting a source/drain of the third storage transistor, a source/drain of the fourth storage transistor, and a source/drain of the second access transistor (they are connected at point 222, see Fig. 2; also see para 41; see the local interconnects e.g. LI_B, 426, LI_T, 428, which are said to interconnect the source/drain regions, see e.g. para 51 and Figs. 4B-4D).
15. The SRAM device of claim 12, further comprising:
a third vertical element electrically connecting a source/drain of the first storage transistor, a source/drain of the second storage transistor, and a source/drain of the first access transistor (they are connected at point 224, see Fig. 2 and para 41; see the local interconnects e.g. LI_B, 426, LI_T, 428, which are said to interconnect the source/drain regions, see e.g. para 51 and Figs. 4B-4D); and
a fourth vertical element electrically connecting a source/drain of the third storage transistor, a source/drain of the fourth storage transistor, and a source/drain of the second access transistor (they are connected at point 222, see Fig. 2; also see para 41; see the local interconnects e.g. LI_B, 426, LI_T, 428, which are said to interconnect the source/drain regions, see e.g. para 51 and Figs. 4B-4D),
wherein the first vertical element is electrically connected to the fourth vertical element (see e.g. Fig. 2), and
wherein the second vertical element is electrically connected to the third vertical element (see e.g. Fig. 2).
16. The SRAM device of claim 15, wherein:
a source/drain of the first storage transistor and a source/drain of the third storage transistor are connected to a ground line (see e.g. ground symbol at the bottom of Fig. 2; see also e.g. para 44); and
a source/drain of the second storage transistor and a source/drain of the fourth storage transistor are connected to a supply voltage line (see e.g. 228 in Fig. 2; see also e.g. para 44, 52, etc.).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896