DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6, 7, 8, 9, 10, 13, and 14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yamagishi (US 2020/0185445)
Regarding claim 6.
Yamagishi teaches a stacked semiconductor device (100) comprising: a first semiconductor chip (300) including a first bonded surface (299) (fig 5) and a second semiconductor chip (200) including a second bonded surface (200) (fig 9) facing the first bonded surface (fig 3) (paragraph 70), the first and second bonded surfaces being bonded to each other (fig 3) (paragraph 70), wherein the first semiconductor chip (300) includes: a first substrate (350) (paragraph 37); at least one first power interconnect (370) disposed between the first substrate (350) and the first bonded surface of the first semiconductor chip (300) (paragraph 71), and configured to carry a power-supply voltage (paragraph 77)at least one first power hybrid bonding structure (369) disposed to be in contact with the first power interconnect (370) (paragraph 73) (fig 5), and configured to extend along the same path as a routing path (269) of the first power interconnect (fig 6), wherein the second semiconductor chip (200) includes: a second substrate (250) (paragraph 64) (fig 11); at least one second power interconnect (270) disposed between the second bonded surface and the second substrate (250) (paragraph 65), and configured to carry a power-supply voltage therethrough (paragraph 146); and at least one second power hybrid bonding structure (269) (paragraph 70) disposed to be in contact with the second power interconnect (270) (paragraph 76) and the first power hybrid bonding structure (369) (fig 3) (paragraph 70), and configured to extend along the same path (12) (fig 6) as a routing path of the second power interconnect (269) (paragraph 80), wherein the second semiconductor chip (200) includes a pixel array (212) configured to generate a pixel signal by converting incident light into the pixel signal (paragraph 64), and the at least one second power hybrid bonding structure (269) is disposed in the pixel array (212) (fig 3).
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Regarding claim 7.
Yamagishi teaches the structure of claim 6.
Yamagishi further teaches the at least one first power hybrid bonding structure (369) includes: a plurality of power hybrid bonding structures (fig 3), each power hybrid bonding structure extending in a line shape in a first direction (fig 6), disposed to be spaced apart from each other in a second direction perpendicular to the first direction (fig 6) (paragraph 77-79).
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Regarding claim 8.
Yamagishi teaches the structure of claim 7.
Yamagishi teaches the at least one first power hybrid bonding structure (369) extends across the pixel array (212) in the first direction (fig 3,6) (paragraph 89-81).
Regarding claim 9.
Yamagishi teaches the structure of claim 7.
Yamagishi teaches the at least one second power hybrid bonding structure (269) includes: a plurality of power hybrid bonding structures (fig 3,6), each power hybrid bonding structure extending in a line shape (fig 6) in the first direction and being disposed to be spaced apart from each other in the second direction (fig 6), wherein the at least one second power hybrid bonding structure (269) and the at least one first power hybrid bonding structure (269) partially overlap with each other in the second direction (fig 3,6).
Regarding claim 10.
Yamagishi teaches the structure of claim 9.
Yamagishi teaches the at least one first power hybrid bonding structure (369) and the at least one second power hybrid bonding structure (269) adjacent to each other are disposed such that a predetermined region (299) of the first power hybrid bonding structure is in contact with a predetermined region of the second power hybrid bonding structure (fig 3,6) (paragraph 76).
Regarding claim 13.
Yamagishi teaches the structure of claim 7.
Yamagishi teaches the at least one second power hybrid bonding structure (269) includes: a plurality of power hybrid bonding structures (fig 3,6), each power hybrid bonding structure extending in a line shape in the first direction and being disposed to be spaced apart from each other in the second direction (fig 6), wherein the at least one second power hybrid bonding structure (269) and the at least one first power hybrid bonding structure (369) adjacent to the at least one second power hybrid bonding structure (269) overlap with each other at their edges (fig 6) (paragraph 77-79).
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Regarding claim 14.
Yamagishi teaches the structure of claim 13.
Yamagishi teaches an edge of the at least one first power hybrid bonding structure (369) is in contact with an edge of the at least one second power hybrid bonding structure (269) adjacent to each other (fig 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2022/0052100) in view of Kim (US 2020/0243466)
Regarding claim 1
Wei teaches a stacked semiconductor device comprising: a first semiconductor chip (311) including a first bonded surface (330) and a second semiconductor chip (301) including a second bonded surface (330) facing the first bonded surface, the first and second bonded surfaces being bonded to each other (fig 3) (paragraph 42), wherein the first semiconductor chip (311) includes: a first substrate (312); at least one first power interconnect (313) disposed between the first substrate (311) and the first bonded surface (330) of the first semiconductor chip (311) (fig 3) (paragraph 42-43), and configured to carry a power-supply voltage therethrough (paragraph 17); and at least one first power hybrid bonding structure (313) disposed to be in contact with the first power interconnect (313) (paragraph 51), and configured to extend along the same path, wherein the second semiconductor chip (301) includes: a second substrate (302); at least one second power interconnect (303) disposed between the second bonded surface and the second substrate (330), and configured to carry a power-supply voltage therethrough (paragraph 17); and at least one second power hybrid bonding structure (303) disposed to be in contact with the second power interconnect and the first power hybrid bonding structure (313), and configured to extend along the same path (note that interconnect is attached to the bottom surface of the bonding structure and is therefore configured to extend where together), the first and second power hybrid bonding structures (303,313) are structured to be symmetrical to each other with respect to the bonded surface (330) (fig 3).
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Wei does not teach does not teach the power hybrid bonding structure extends along a routing path.
Kim teaches a hybrid bonding structure (fig 7) wherein the first hybrid bonding structure (150h) is configured to extend along a routing path (fig 13), and a second hybrid bonding structure (250h) are configured to extend along a routing path (150h) (fig 13) (paragraph (58)
It would have been obvious to one of ordinary skill in the art for the hybrid bonding structures to extend along routing paths in order to enable connection to different die components.
Regarding claim 3.
Wei in view of Kim teaches the structure of claim 1.
Kim teaches each of the first (150h) and second (250h) hybrid bonding structures is formed to extend in a straight line shape in a first direction (fig 13).
Regarding claim 4.
Wei in view of Kim teaches the structure of claim 1.
Kim teaches the hybrid bonding structure is formed to extend a bent line shape (150g) (fig 12) (paragraph 57)
It would have been obvious to one of ordinary skill in the art for the hybrid routing structures to comprise a bent line in order to enable routing through proximate structures (Kim paragraph 57).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2022/0052100) in view of Kim (US 2020/0243466) as applied to claim 1 and further in view of Chen (US 2021/0391376)
Regarding claim 5.
Wei in view of Kim teaches elements of claim 1 above.
Wei in in view of Kim does not teach signal interconnect.
Chen teaches at least one first signal interconnect (1242) disposed between the first bonded surface (1204) and the first substrate (1206) (paragraph 48), and configured to carry a signal therethrough (paragraph 54); at least one first signal hybrid bonding structure (1202,1240) disposed on the first signal interconnect (1242) and having a via shape (1240) in contact with the first signal interconnect (1242); at least one second signal interconnect (1140) disposed between the second bonded surface (1104) and the second substrate (1106) (paragraph 48), and configured to carry a signal therethrough (paragraph 54); and at least one second signal hybrid bonding structure (1102,1130) having a via shape (1130) in contact with the second signal interconnect (1140) and the first signal hybrid bonding structure (1202) (fig 6) (paragraph 48,54).
It would have been obvious to one of ordinary skill in the art to provide a signal transmission path extending across the hybrid bond interface so that signal from the first die device can reach devices on the second die (Chen paragraph 31)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamagishi (US 2020/0185445) as applied to claim 9 and further in view of Jang (US 2022/0059596)
Regarding claim 11.
Yamagishi teaches the elements of claim 9 above.
Yamagishi does not teach that at the at least one first power hybrid bonding structure and the at least one second power hybrid bonding structure together entirely cover the pixel array.
Jang teaches the at least one first power hybrid bonding structure (114) and the at least one second power hybrid bonding structure (21,31) (paragraph 29) together (paragraph 61) entirely cover (paragraph 51) the pixel array (APS) (paragraph 21) (fig 2).
It would have been obvious to one of ordinary skill in the for the bonded structure to completely cover the pixel region in order shield noise caused by an electromagnetic field induced by the operation of the circuits (Jang paragraph 51)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamagishi (US 2020/0185445) as applied to claim 6 and further in view of Lattard (US 2019/0252353)
Regarding claim 12.
Yamagishi teaches elements of claim 6 above.
Yamagishi does not teach that the first or second hybrid bonding structures are configured for a ground voltage.
Lattard teaches the at least one first power hybrid bonding structure (31) and the at least one second power hybrid bonding structure (32) (fig 1) (paragraph 16) are configured to receive a ground voltage (GND) (fig 2) (paragraph 35).
It would have been obvious to one of ordinary skill in the for the hybrid bonding structures to be configured to receive a ground voltage in order to enable a voltage difference in enabling current to flow through the system.
Response to Arguments
Applicant's arguments filed 7/28/2025 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach that the hybrid bonding structures are structured to be symmetrical to each other, because there is no textual support for the limitation and the depicted figures cannot be relied upon (page 8,9)
The applicant is incorrect, any portion of the prior art including elements depicted in the figures may be relied upon. MPEP 2125.I. The applicant will note that the examiner did not rely upon the proportions or relative dimensions of the applied prior art, the examiner relied upon the figure clearly and graphically depicting the structures to be symmetrical about the bonded surface.
The applicant argues that the prior art does not anticipate amended claim 6.
The applicant will note the prior art newly applied above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 November 3, 2025