Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 7, and 11 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US20220216349A1, hereinafter Lee).
Regarding claim 1, Lee discloses a semiconductor device comprising:
a first nanosheet field effect transistor (FET) having a first gate stack, arranged on a substrate (Fig. 6 multi-bridge channel structure MBCSa); and
a second nanosheet FET having a second gate stack, arranged on the substrate adjacent to the first nanosheet FET (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa),
wherein a top of the first gate stack and a top of the second gate stack are at different heights (Fig. 6 topmost bridge within MBCSa 120 is at a different height to topmost bridge within MBCSb 124).
Regarding claim 4, Lee discloses the semiconductor device of claim 1,
wherein the first FET comprises a pull-up (PU) PFET, and the second FET comprises a pull-down (PD) NFET (Par. 35 “[t]he first and second load transistors PU1 and PU2 may be referred to as pull-up transistors” and “[t]he first and second drive transistors PD1 and PD2 may be referred to as pull-down transistors.” Par. 36 additionally teaches that “[t]he first and second load transistors PU1 and PU2 may include p-type metal oxide semiconductor (PMOS) transistors, and the first and second transfer transistors PG1 and PG2 and the first and second drive transistors PD1 and PD2 may include n-type MOS (NMOS) transistors.” Therefore, Lee discloses a first pull-up PFET and a second pull-down NFET).
Regarding claim 7, Lee discloses the semiconductor device of claim 4, further comprising
a shallow trench isolation (STI) SiO2 recess connected to the PU PFET and the PD NFET of different depths on an upper surface of the substrate (Par. 107 “[a] device isolation region may be formed by using an ordinary process, such as a shallow trench isolation (STI) process”).
Regarding claim 11, Lee discloses a method of preventing a source/drain (S/D) epi merge, comprising:
providing a first nanosheet fin including a first field effect transistor (FET) having a first gate stack, on a substrate (Fig. 6 multi-bridge channel structure MBCSa); and
providing a second nanosheet fin including a second FET having a second gate stack on the substrate adjacent to the first nanosheet fin (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa),
wherein a first top of the first gate stack is a different height than a second top of the second gate stack (Fig. 6 topmost bridge within MBCSa 120 is at a different height to topmost bridge within MBCSb 124).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20220216349A1) in view of Lim et al. (US20200194440A1, hereinafter Lim).
Regarding claim 2, Lee teaches the semiconductor device of claim 1, further comprising:
a first channel of the first gate stack extending from a bottom of the first gate stack and having a first height (Fig. 6 lowermost nano-bridge 112 in MBCSa has a first height); and
a second channel of the second gate stack extending from a bottom of the second gate stack and having a second height (Fig. 6 lowermost nano-bridge 122 in MBCSb has a second height).
Lee does not appear to teach
wherein the first height of the first channel is different than the second height of the second channel based on a difference in channel heights of the substrate.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). As Lim teaches adjusting the distance between adjacent sources by the different heights of fins 212/222, the combination of Lee and Lim teaches adjusting first and second channel heights based on a difference in channel heights relative to the substrate in order to optimize the distance between adjacent sources.
Regarding claim 3, the combination of Lee and Lim teaches the semiconductor device of claim 2,
wherein the first height of the first channel is different than the second height of the second channel additionally based on a metal gate height having a distance between two adjacent channels on the top of the first gate stack and the top of the second gate stack (Lee teaches different gate stack heights as shown in fig. 6 based on different gate electrode 128 heights in GSa and GSb. Combined with the above teachings of Lim, a person of ordinary skill in the art would also adjust the relative gate stack heights by altering their respective gate electrode heights in order to optimize the distances between adjacent sources).
Regarding claim 5, Lee teaches the semiconductor device of claim 4.
Lee does not appear to teach
wherein a source/drain (S/D) epitaxial growth on the PU PFET and on the PD NFET are offset by a difference in channel height of the first height of the first channel and the second height of the second channel.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). As Lim teaches adjusting the distance between adjacent sources by the different heights of fins 212/222, the combination of Lee and Lim teaches adjusting first and second channel heights based on a difference in channel heights relative to the substrate in order to optimize the distance between adjacent sources.
Regarding claim 16, Lee teaches the method according to claim 11, further comprising:
providing a first channel that extends from a bottom of the first gate stack and has a first height (Fig. 6 lowermost nano-bridge 112 in MBCSa has a first height); and
providing a second channel that extends from a bottom of the second gate stack and has a second height (Fig. 6 lowermost nano-bridge 122 in MBCSb has a second height).
Lee does not appear to teach
wherein the first height of the first channel is different than the second height of the second channel by at least a difference in channel heights of the substrate.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). As Lim teaches adjusting the distance between adjacent sources by the different heights of fins 212/222, the combination of Lee and Lim teaches adjusting first and second channel heights based on a difference in channel heights relative to the substrate in order to optimize the distance between adjacent sources.
Regarding claim 17, the combination of Lee and Lim teaches the method according to claim 16, further comprising
providing a first metal gate on the first nanosheet FET and a second metal gate on the second nanosheet FET (Lee fig. 6 gate electrodes 128 in MBCSa/MBCSb), wherein the first height of the first channel is different than the second height of the second channel by the difference in channel heights and by a metal gate height distance between the first channel and the second channel on the first top of the first gate stack and the second top of the second gate stack (Lee teaches different gate stack heights as shown in fig. 6 based on different gate electrode 128 heights in GSa and GSb. Combined with the above teachings of Lim, a person of ordinary skill in the art would also adjust the relative gate stack heights by altering their respective gate electrode heights in order to optimize the distances between adjacent sources).
Claims 6, 8-10, 12-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20220216349A1) in view of Lim (US20200194440A1) and Cheng et al. (US20160336428A1, hereinafter Cheng).
Regarding claim 6, Lee teaches the semiconductor device of claim 4.
Lee does not appear to teach wherein:
the substrate comprises a stepped upper surface;
the PU PFET is arranged on the stepped upper surface of the substrate; and
the PD NFET is arranged a non-stepped upper surface of the substrate.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)).
Cheng teaches
the substrate comprises a stepped upper surface (Fig. 16 silicon portion 14P has stepped upper surface).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Lim with the teachings of Cheng because as both Lim and Cheng teach a suitable method for adjusting the heights of adjacent transistors on a silicon substrate, it would have been obvious to substitute Lim’s variable fin height on a level substrate with Cheng’s variable fin height through use of a stepped substrate structure to achieve the predictable result of adjusting the height of adjacent transistors by use of a stepped silicon substrate in order to optimize the distance between adjacent source/drains as taught by Lim.
Regarding claim 8, Lee teaches the semiconductor device of claim 1.Lee does not appear to teach wherein:
the substrate comprises a silicon (Si) pattern with different recess depths; and
the substrate is arranged below a Bottom Dielectric Isolation (BDI) layer.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)).
Cheng teaches
the substrate comprises a silicon (Si) pattern with different recess depths (Fig. 16 silicon portion 14P has stepped upper surface which is a result of different recess depths); and
the substrate is arranged below a Bottom Dielectric Isolation (BDI) layer (Fig. 16 silicon portion 14P disposed beneath first and second oxide structures 30A/30B).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Lim with the teachings of Cheng because as both Lim and Cheng teach a suitable method for adjusting the heights of adjacent transistors on a silicon substrate, it would have been obvious to substitute Lim’s variable fin height on a level substrate with Cheng’s variable fin height through use of a stepped substrate structure with different recess depths to achieve the predictable result of adjusting the height of adjacent transistors by use of a stepped silicon substrate with different recess depths in order to optimize the distance between adjacent source/drains as taught by Lim.
Regarding claim 9, the combination of Lee, Lim, and Cheng teaches the semiconductor device of claim 8,
wherein there are a same number of nanosheets for each nanosheet FET on the Si pattern (While Lee does not explicitly disclose a same number of nanosheets for each nanosheet FET on the Si pattern, as the only difference between the combination of Lee, Lim, and Cheng and the claimed invention is a relative recitation of dimensions and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than the combination of Lee, Lim, and Cheng, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Regarding claim 10, the combination of Lee, Lim, and Cheng teaches the semiconductor device of claim 8, wherein:
there are a same number of nanosheets having a same total nanosheet height (While Lee does not explicitly disclose a same number of nanosheets having the same height for each nanosheet FET on the Si pattern, as the only difference between the combination of Lee, Lim, and Cheng and the claimed invention is a relative recitation of dimensions and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than the combination of Lee, Lim, and Cheng, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)); and
the total nanosheet height comprises a channel height, a dummy SiGe layer, and the BDI layer (Lee fig. 11A see preliminary layers which comprise alternating channel layers and sacrificial layers which par. 112 teaches “may be formed by using an epitaxial silicon germanium layer.” See above rejection of claim 8 for the BDI as taught by Cheng. The combination of Lee, Lim, and Cheng would have a total height comprising those 3 elements).
Regarding claim 12, Lee teaches the method according to claim 11.
Lee does not appear to teach further comprising
forming a step on a surface of the substrate such that the first gate stack is offset in height from the second gate stack.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)).
Cheng teaches
forming a step on a surface of the substrate such that the first gate stack is offset in height from the second gate stack (Fig. 16 silicon portion 14P has stepped upper surface).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Lim with the teachings of Cheng because as both Lim and Cheng teach a suitable method for adjusting the heights of adjacent transistors on a silicon substrate, it would have been obvious to substitute Lim’s variable fin height on a level substrate with Cheng’s variable fin height through use of a stepped substrate structure to achieve the predictable result of adjusting the height of adjacent transistors by use of a stepped silicon substrate in order to optimize the distance between adjacent source/drains as taught by Lim.
Regarding claim 13, the combination of Lee, Lim, and Cheng teaches the method according to claim 12,
wherein the first nanosheet fin and the second nanosheet fin formed on the substrate have equal lengths (Lee fig. 4 first and second transistors 200A/200B have the same length).
Regarding claim 14, the combination of Lee, Lim, and Cheng teaches the method according to claim 12, wherein:
the first nanosheet fin is provided on a higher portion of the stepped substrate surface (Cheng fig. 16 shows a first set of fins under first gate 40A on a higher portion of a stepped substrate); and
the second nanosheet fin is provided on a lower portion of the stepped substrate surface (Cheng fig. 16 shows a second set of fins under second gate 40B on a lower portion of a stepped substrate. See above rejection of claim 12 for the teachings of Lim for putting the separate transistors at different heights).
Regarding claim 15, the combination of Lee, Lim, and Cheng teaches the method according to claim 14, wherein
the first FET provided on the first nanosheet fin comprises a pull-up (PU) PFET, and
the second FET provided on the second nanosheet fin comprises a pull-down (PD) NFET (Par. 35 “[t]he first and second load transistors PU1 and PU2 may be referred to as pull-up transistors” and “[t]he first and second drive transistors PD1 and PD2 may be referred to as pull-down transistors.” Par. 36 additionally teaches that “[t]he first and second load transistors PU1 and PU2 may include p-type metal oxide semiconductor (PMOS) transistors, and the first and second transfer transistors PG1 and PG2 and the first and second drive transistors PD1 and PD2 may include n-type MOS (NMOS) transistors.” Therefore, Lee discloses a first pull-up PFET and a second pull-down NFET).
Regarding claim 18, Lee teaches a method of forming a semiconductor device, the method comprising:
forming a first gate nanosheet stack with alternating layers of different semiconductor materials (Fig. 6 multi-bridge channel structure MBCSa comprises alternating semiconductor layers as can be seen in fig. 11A with alternating sacrificial/channel layers 111a-120a);
forming a second nanosheet gate stack with alternating layers of different semiconductor materials adjacent to the first nanosheet gate stack (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa comprises alternating semiconductor layers as can be seen in fig. 11A with alternating sacrificial/channel layers 111a-120a);
patterning the first nanosheet gate stack and the second nanosheet gate stack to create respective nanosheet fins (Figs. 11A-12A alternating sacrificial/channel layers 111a-120a patterned into nanosheet fins); and
growing an epitaxial source/drain (S/D) on each of the first nanosheet fin and the second nanosheet fin (Fig. 16A source/drain patterns 346 formed over both fins).
Lee does not appear to teach
forming a stepped portion on a substrate surface;
wherein an upper surface of a first nanosheet fin is higher than an upper surface of a second nanosheet fin.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)).
Cheng teaches
the substrate comprises a stepped upper surface (Fig. 16 silicon portion 14P has stepped upper surface).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Lim with the teachings of Cheng because as both Lim and Cheng teach a suitable method for adjusting the heights of adjacent transistors on a silicon substrate, it would have been obvious to substitute Lim’s variable fin height on a level substrate with Cheng’s variable fin height through use of a stepped substrate structure to achieve the predictable result of adjusting the height of adjacent transistors by use of a stepped silicon substrate in order to optimize the distance between adjacent source/drains as taught by Lim.
Regarding claim 19, the combination of Lee, Lim, and Cheng teaches the method according to claim 18,
wherein the epitaxial S/D is grown on a side of each nanosheet fin (Lee fig. 16A source/drain 346 on side of each nanosheet fin) and has different respective height on the stepped portion of the substrate surface and the non-stepped portion of the substrate surface (Lim teaches adjusting the distance between adjacent source/drains is a results effective variable that may be optimized by changing relative source/drain heights, see above rejection of claim 18).
Regarding claim 20, the combination of Lee, Lim, and Cheng teaches the method according to claim 18, wherein:
the alternating layers of different semiconductor materials include Si and SiGe (Par. 112 “when the channel layers 112 a…124 a are formed by using an epitaxial silicon layer, the sacrificial layers 111 a…125 a may be formed by using an epitaxial silicon germanium layer”); and
the method further comprises providing an STI of SiO2 on surface of the substrate (Par. 107 “A device isolation region may be formed by using an ordinary process, such as a shallow trench isolation (STI) process” and examiner notes that SiO2 is a common material for shallow trench isolations).
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812