Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see sections titled “Obviousness Rejections of Claims 1-17” and “Obviousness Rejection of Claims 18-20,” filed 05/19/2026, with respect to the rejection(s) of claim under USC 102 and USC 103, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al. (US20220216349A1, hereinafter Lee) and Chiu et al. (US20220130822A1, hereinafter Chiu).
Regarding amended claim 1, Lee teaches a semiconductor device comprising:
a first nanosheet field effect transistor (FET) having a first gate stack, arranged on a substrate (Fig. 6 multi-bridge channel structure MBCSa); and
a second nanosheet FET having a second gate stack, arranged on the substrate adjacent to the first nanosheet FET (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa),
wherein a top of the first gate stack and a top of the second gate stack are at different heights (Fig. 6 topmost bridge within MBCSa 120 is at a different height to topmost bridge within MBCSb 124).
Lee does not appear to teach
a bottommost nanosheet of the first gate stack is at a different horizontal plane than a bottommost nanosheet of the second gate stack.
Chiu teaches
a bottommost nanosheet of the first gate stack is at a different horizontal plane than a bottommost nanosheet of the second gate stack (Fig. 4K plurality of nanosheet stacks 150a/150b/150c are disposed with their bottommost nanosheets at different horizontal planes).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Chiu because by using “the stepped substrate to compensate for the height of the nanosheet stacks…[one can] produce a generally planar structure while still customizing the performance for different functional blocks” (Chiu par. 25).
See below for full claims mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-7, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20220216349A1) in view of Chiu (US20220130822A1).
Regarding claim 1, Lee teaches a semiconductor device comprising:
a first nanosheet field effect transistor (FET) having a first gate stack, arranged on a substrate (Fig. 6 multi-bridge channel structure MBCSa); and
a second nanosheet FET having a second gate stack, arranged on the substrate adjacent to the first nanosheet FET (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa),
wherein a top of the first gate stack and a top of the second gate stack are at different heights (Fig. 6 topmost bridge within MBCSa 120 is at a different height to topmost bridge within MBCSb 124).
Lee does not appear to teach
a bottommost nanosheet of the first gate stack is at a different horizontal plane than a bottommost nanosheet of the second gate stack.
Chiu teaches
a bottommost nanosheet of the first gate stack is at a different horizontal plane than a bottommost nanosheet of the second gate stack (Fig. 4K plurality of nanosheet stacks 150a/150b/150c are disposed with their bottommost nanosheets at different horizontal planes).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Chiu because by using “the stepped substrate to compensate for the height of the nanosheet stacks…[one can] produce a generally planar structure while still customizing the performance for different functional blocks” (Chiu par. 25).
Regarding claim 4, the combination of Lee and Chiu teaches the semiconductor device of claim 1,
wherein the first FET comprises a pull-up (PU) PFET, and the second FET comprises a pull-down (PD) NFET (Lee par. 35 “[t]he first and second load transistors PU1 and PU2 may be referred to as pull-up transistors” and “[t]he first and second drive transistors PD1 and PD2 may be referred to as pull-down transistors.” Par. 36 additionally teaches that “[t]he first and second load transistors PU1 and PU2 may include p-type metal oxide semiconductor (PMOS) transistors, and the first and second transfer transistors PG1 and PG2 and the first and second drive transistors PD1 and PD2 may include n-type MOS (NMOS) transistors.” Therefore, Lee discloses a first pull-up PFET and a second pull-down NFET).
Regarding claim 6, the combination of Lee and Chiu teaches the semiconductor device of claim 4, wherein:
the substrate comprises a stepped upper surface (Chiu par. 29 teaches that by using “the stepped substrate to compensate for the height of the nanosheet stacks…[one can] produce a generally planar structure while still customizing the performance for different functional blocks”);
the PU PFET is arranged on the stepped upper surface of the substrate; and
the PD NFET is arranged a non-stepped upper surface of the substrate (As Chiu teaches the use of a stepped semiconductor surface to compensate for semiconductor stacks of different heights and optimize arrangements, see Chiu par. 25, this means a person of ordinary would be motivated to try an arrangement where the PU PFET is disposed on the upper surface of a stepped substrate and the PD NFET is disposed on the lower surface of the stepped substrate as taught by Chiu).
Regarding claim 7, the combination of Lee and Chiu teaches the semiconductor device of claim 4, further comprising
a shallow trench isolation (STI) SiO2 recess connected to the PU PFET and the PD NFET of different depths on an upper surface of the substrate (Lee par. 107 “[a] device isolation region may be formed by using an ordinary process, such as a shallow trench isolation (STI) process”).
Regarding claim 11, Lee teaches a method of preventing a source/drain (S/D) epi merge, comprising:
providing a first nanosheet fin including a first field effect transistor (FET) having a first gate stack, on a substrate (Fig. 6 multi-bridge channel structure MBCSa); and
providing a second nanosheet fin including a second FET having a second gate stack on the substrate adjacent to the first nanosheet fin (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa),
wherein a first top of the first gate stack is a different height than a second top of the second gate stack (Fig. 6 topmost bridge within MBCSa 120 is at a different height to topmost bridge within MBCSb 124).
Lee does not appear to teach
a bottommost nanosheet of the first gate stack is at a different horizontal plane than a bottommost nanosheet of the second gate stack.
Chiu teaches
a bottommost nanosheet of the first gate stack is at a different horizontal plane than a bottommost nanosheet of the second gate stack (Fig. 4K plurality of nanosheet stacks 150a/150b/150c are disposed with their bottommost nanosheets at different horizontal planes).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Chiu because by using “the stepped substrate to compensate for the height of the nanosheet stacks…[one can] produce a generally planar structure while still customizing the performance for different functional blocks” (Chiu par. 25).
Regarding claim 12, the combination of Lee and Chiu teaches the method according to claim 11,
further comprising forming a step on a surface of the substrate such that the first gate stack is offset in height from the second gate stack (Chiu teaches the technique of using a stepped substrate, see above rejection of claim 11. Chiu figs. 4A-4F illustrate the step of forming a stepped substrate which would result in the first gate stack of the combination of Lee and Chiu being offset in height from the second gate stack).
Regarding claim 13, the combination of Lee and Chiu teaches the method according to claim 12,
wherein the first nanosheet fin and the second nanosheet fin formed on the substrate have equal lengths (Lee fig. 4 first and second transistors 200A/200B have the same length).
Regarding claim 14, the combination of Lee and Chiu teaches the method according to claim 12,
wherein: the first nanosheet fin is provided on a higher portion of the stepped substrate surface; and
the second nanosheet fin is provided on a lower portion of the stepped substrate surface (Chiu fig. 4K teaches a plurality of nanosheet stacks disposed on a stacked substrate and so the combination of Lee and Chiu, see claim 11, would have a first nanosheet stack provided on a higher portion of the stepped substrate and a second nanosheet stack provided on a lower portion of the stepped substrate).
Regarding claim 15, the combination of Lee and Chiu teaches the method according to claim 14,
wherein the first FET provided on the first nanosheet fin comprises a pull-up (PU) PFET, and
the second FET provided on the second nanosheet fin comprises a pull-down (PD) NFET (Lee par. 35 teaches that “[t]he first and second load transistors PU1 and PU2 may be referred to as pull-up transistors” and “[t]he first and second drive transistors PD1 and PD2 may be referred to as pull-down transistors.” Par. 36 of Lee additionally teaches that “[t]he first and second load transistors PU1 and PU2 may include p-type metal oxide semiconductor (PMOS) transistors, and the first and second transfer transistors PG1 and PG2 and the first and second drive transistors PD1 and PD2 may include n-type MOS (NMOS) transistors.” Therefore, Lee discloses a first pull-up PFET and a second pull-down NFET).
Claims 2-3, 5, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee (US20220216349A1) and Chiu (US20220130822A1), as applied to claims 1, 4, and 11 above, and further in view of Lim et al. (US20200194440A1, hereinafter Lim).
Regarding claim 2, the combination of Lee and Chiu teaches the semiconductor device of claim 1, further comprising:
a first channel of the first gate stack extending from a bottom of the first gate stack and having a first height (Fig. 6 lowermost nano-bridge 112 in MBCSa has a first height); and
a second channel of the second gate stack extending from a bottom of the second gate stack and having a second height (Fig. 6 lowermost nano-bridge 122 in MBCSb has a second height).
The combination of Lee and Chiu does not appear to teach
wherein the first height of the first channel is different than the second height of the second channel based on a difference in channel heights of the substrate.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). As Lim teaches adjusting the distance between adjacent sources by the different heights of fins 212/222, the combination of Lee, Chiu, and Lim teaches adjusting first and second channel heights based on a difference in channel heights relative to the substrate in order to optimize the distance between adjacent sources.
Regarding claim 3, the combination of Lee, Chiu, and Lim teaches the semiconductor device of claim 2,
wherein the first height of the first channel is different than the second height of the second channel additionally based on a metal gate height having a distance between two adjacent channels on the top of the first gate stack and the top of the second gate stack (Lee teaches different gate stack heights as shown in fig. 6 based on different gate electrode 128 heights in GSa and GSb. Combined with the above teachings of Lim, a person of ordinary skill in the art would also adjust the relative gate stack heights by altering their respective gate electrode heights in order to optimize the distances between adjacent sources).
Regarding claim 5, the combination of Lee and Chiu teaches the semiconductor device of claim 4.
The combination of Lee and Chiu does not appear to teach
wherein a source/drain (S/D) epitaxial growth on the PU PFET and on the PD NFET are offset by a difference in channel height of the first height of the first channel and the second height of the second channel.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). As Lim teaches adjusting the distance between adjacent sources by the different heights of fins 212/222, the combination of Lee, Chiu, and Lim teaches adjusting first and second channel heights based on a difference in channel heights relative to the substrate in order to optimize the distance between adjacent sources.
Regarding claim 16, the combination of Lee and Chiu teaches the method according to claim 11, further comprising:
providing a first channel that extends from a bottom of the first gate stack and has a first height (Fig. 6 lowermost nano-bridge 112 in MBCSa has a first height); and
providing a second channel that extends from a bottom of the second gate stack and has a second height (Fig. 6 lowermost nano-bridge 122 in MBCSb has a second height).
The combination of Lee and Chiu does not appear to teach
wherein the first height of the first channel is different than the second height of the second channel by at least a difference in channel heights of the substrate.
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.”
Therefore, as distance between adjacent sources affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). As Lim teaches adjusting the distance between adjacent sources by the different heights of fins 212/222, the combination of Lee, Chiu, and Lim teaches adjusting first and second channel heights based on a difference in channel heights relative to the substrate in order to optimize the distance between adjacent sources.
Regarding claim 17, the combination of Lee, Chiu, and Lim teaches the method according to claim 16, further comprising
providing a first metal gate on the first nanosheet FET and a second metal gate on the second nanosheet FET (Lee fig. 6 gate electrodes 128 in MBCSa/MBCSb), wherein the first height of the first channel is different than the second height of the second channel by the difference in channel heights and by a metal gate height distance between the first channel and the second channel on the first top of the first gate stack and the second top of the second gate stack (Lee teaches different gate stack heights as shown in fig. 6 based on different gate electrode 128 heights in GSa and GSb. Combined with the above teachings of Lim, a person of ordinary skill in the art would also adjust the relative gate stack heights by altering their respective gate electrode heights in order to optimize the distances between adjacent sources).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Chiu as applied to claim 1 above, and further in view of Cheng et al. (US20160336428A1, hereinafter Cheng).
Regarding claim 8, the combination of Lee and Chiu teaches the semiconductor device of claim 1, wherein:
the substrate comprises a silicon (Si) pattern with different recess depths.
The combination of Lee and Chiu does not appear to teach
the substrate is arranged below a Bottom Dielectric Isolation (BDI) layer.
Cheng teaches
the substrate is arranged below a Bottom Dielectric Isolation (BDI) layer (Fig. 16 silicon portion 14P disposed beneath first and second oxide structures 30A/30B).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Chiu with the teachings of Cheng because the introduction of oxide structures below the fins increases isolation between adjacent fins which reduces parasitic effects.
Regarding claim 9, the combination of Lee, Chiu, and Cheng teaches the semiconductor device of claim 8,
wherein there are a same number of nanosheets for each nanosheet FET on the Si pattern (While the combination of Lee, Chiu, and Cheng does not explicitly disclose a same number of nanosheets for each nanosheet FET on the Si pattern, as the only difference between the combination of Lee, Chiu, and Cheng and the claimed invention is a relative recitation of dimensions and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than the combination of Lee, Chiu, and Cheng, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Regarding claim 10, the combination of Lee, Chiu, and Cheng teaches the semiconductor device of claim 8, wherein:
there are a same number of nanosheets having a same total nanosheet height (Chiu par. 25 teaches that one can use “the stepped substrate to compensate for the height of the nanosheet stacks…[to] produce a generally planar structure while still customizing the performance for different functional blocks,” see above rejection of claim 1. Therefore, the combination of Lee, Chiu, and Cheng teaches utilizing a stepped substrate in order to have a same nanosheet height); and
the total nanosheet height comprises a channel height, a dummy SiGe layer, and the BDI layer (Lee fig. 11A see preliminary layers which comprise alternating channel layers and sacrificial layers which par. 112 teaches “may be formed by using an epitaxial silicon germanium layer.” See above rejection of claim 8 for the BDI as taught by Cheng. The combination of Lee, Chiu, and Cheng would have a total height comprising those 3 elements).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20220216349A1) in view of Chiu (US20220130822A1) and Lim (US20200194440A1).
Regarding claim 18, Lee teaches a method of forming a semiconductor device, the method comprising:
forming a first gate nanosheet stack with alternating layers of different semiconductor materials on the stepped portion of the substrate surface (Fig. 6 multi-bridge channel structure MBCSa comprises alternating semiconductor layers as can be seen in fig. 11A with alternating sacrificial/channel layers 111a-120a);
forming a second nanosheet gate stack with alternating layers of different semiconductor materials on a non-stepped portion of the substrate surface (Fig. 6 multi-bridge channel structure MBCSb arranged on substrate 100 adjacent to MBCSa comprises alternating semiconductor layers as can be seen in fig. 11A with alternating sacrificial/channel layers 111a-120a);
patterning the first nanosheet gate stack and the second nanosheet gate stack to create respective nanosheet fins (Figs. 11A-12A alternating sacrificial/channel layers 111a-120a patterned into nanosheet fins); and
growing an epitaxial source/drain (S/D) on each of the first nanosheet fin and the second nanosheet fin (Fig. 16A source/drain patterns 346 formed over both fins).
Lee does not appear to teach
forming a stepped portion on a substrate surface,
wherein an upper surface of a first nanosheet fin is higher than an upper surface of a second nanosheet fin,
wherein a bottom of the first gate nanosheet stack is at a different horizontal plane than a bottom of the second gate nanosheet stack.
Chiu teaches
forming a stepped portion on a substrate surface,
wherein a bottom of the first gate nanosheet stack is at a different horizontal plane than a bottom of the second gate nanosheet stack (Fig. 4K plurality of nanosheet stacks 150a/150b/150c are disposed with their bottommost nanosheets at different horizontal planes).
Lim teaches in par. 66 that “[t]he greater height of the source 210 relative to the source 208 [in fig. 6] may increase the distance 220 between the adjacent tips of the source 208 and source 210, which may lead to an increased breakdown voltage.” As distance between the sources of adjacent fins affects the breakdown voltage, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Chiu because by using “the stepped substrate to compensate for the height of the nanosheet stacks…[one can] produce a generally planar structure while still customizing the performance for different functional blocks” (Chiu par. 25).
Therefore, the combination of Lee, Chiu, and Lim also teach the limitation
wherein an upper surface of a first nanosheet fin is higher than an upper surface of a second nanosheet fin (While Chiu teaches the technique of utilizing a stepped substrate structure to produce a generally planar device, a person of ordinary skill in the art with the teachings of Lim would also take into account the relative heights to optimize their source distances and so the combination of Lee, Chiu, and Lim teaches embodiments in which the upper surface of a first fin is higher than an upper surface of a second fin).
Regarding claim 19, the combination of Lee, Chiu, and Lim teaches the method according to claim 18,
wherein the epitaxial S/D is grown on a side of each nanosheet fin (Lee fig. 16A source/drain 346 on side of each nanosheet fin) and has different respective height on the stepped portion of the substrate surface and the non-stepped portion of the substrate surface (The combination of Lee, Chiu, and Lim teaches the technique of adjusting adjacent sources to optimize performance, see claim 18, and so their combination also teach embodiments in which the adjacent S/D regions have different heights).
Regarding claim 20, the combination of Lee, Chiu, and Lim teaches the method according to claim 18, wherein:
the alternating layers of different semiconductor materials include Si and SiGe (Lee par. 112 teaches that “when the channel layers 112 a…124 a are formed by using an epitaxial silicon layer, the sacrificial layers 111 a…125 a may be formed by using an epitaxial silicon germanium layer”); and
the method further comprises providing an STI of SiO2 on surface of the substrate (Lee par. 107 teaches that “[a] device isolation region may be formed by using an ordinary process, such as a shallow trench isolation (STI) process” and examiner notes that SiO2 is a common material for shallow trench isolations).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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