DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/27/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0301459 A1 (Akiba) further in view of US 2015/0364410 A1 (Hando).
Re claims 1 and 19, Akiba teaches an electronic component comprising:
an electronic component body (semiconductor element layer 12a);
at least one electrode (conductive structure including surface wiring 14 and redistribution wiring 17) on a surface of the electronic component body; and
a cover layer (insulating film 3) having insulating properties on at least a part of a periphery of the electrode and extending across a boundary between the periphery of the electrode and the surface of the electronic component body (Figs. 1 and 2),
wherein the surface of the electronic component body includes an insulating layer (insulating film 16),
the electrode includes, on the at least part of the periphery, a lower electrode (surface wiring 14) closer to the surface of the electronic component body and an upper electrode (redistribution wiring 17) on the lower electrode,
the lower electrode is in direct contact with an entire surface of the upper electrode (lower electrode 14 is in direct contact with the entirety of the bottommost surface of upper electrode 17 Fig. 2),
the cover layer is not disposed between the lower electrode and the upper electrode (layer 3 of the cover layer is not between the lower or upper electrode and in the highlighted portion where the lower and upper electrodes are connected there is not intervening layer see Fig. 2 below),
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the lower electrode extends more outward than the upper electrode to create a step at the at least part of the periphery of the electrode, and at the step at the periphery of the electrode, the cover layer extends from a surface of the upper electrode to a portion with no electrodes on the surface of the electronic component body (Figs. 1 and 2).
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Akiba does not explicitly teach wherein the insulating layer is a ceramic layer containing a first low temperature co-fired ceramic material, and the cover layer contains a second low temperature co-fired ceramic material (claim 1), nor wherein both the first low temperature co-fired ceramic material and the second low temperature co-fired ceramic material include a same low temperature co-fired ceramic material (claim 19). However, Akiba does teach that the insulation films 16 should be an inorganic low-k material such as SiO or SiN [0070], and insulation layer 3 is a resin material and provides protection and is used to surround the solder bumps 18 [0075] Fig. 2.
Hando teaches making printed circuit boards and package substrates for semiconductor devices wherein the solder blocking layers can be made of either resins, silicon nitride or LTCC ceramics ([0017]).
It would have been obvious to one of ordinary skill in the art at the time of filing to form the insulating layers 3 and 16 of Akiba using LTCC materials as taught in Hando. Hando teaches the equivalency of resins, silicon nitride and LTCC materials for the same uses in semiconductor packages.
Applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Re claim 2, Akiba teaches wherein the at least one electrode includes multiple electrodes on the surface of the electronic component body (Fig. 1), the multiple electrodes include an outermost peripheral electrode most peripherally disposed on the surface of the electronic component body and an inner electrode inward of the outermost peripheral electrodes, the outermost peripheral electrode includes the step, and the cover layer is on the step (the upper and lower electrode layers comprising a step due to the difference in area is present in all electrodes Fig. 1).
Re claim 3, Akiba teaches wherein the outermost peripheral electrode includes the step at its edge most peripherally disposed on the surface of the electronic component body, and the cover layer is on the step (lower electrode layer 14 extends further to the rightmost and leftmost edge of the substrate than the upper electrode layer 17 Fig. 1 and 2).
Re claim 4, Akiba teaches wherein the at least one electrode includes multiple electrodes on the surface of the electronic component body, at least one of the multiple electrodes includes the step at its edge facing adjacent electrode of the multiple electrodes, and the cover layer is on the step (lower electrode layer 14 extends further outward the upper electrode 17 around all sides of the electrode Fig. 1 and 2).
Re claim 19, Akiba teaches wherein both the first low temperature co-fired ceramic material and the second low temperature co-fired ceramic material include a same low temperature co-fired ceramic material (insulating layer 16 of the cover layer extends across the terminating surface of the device and can be a ceramic like SiO or SiN [0070]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on the references as they are being applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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