DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Applicant’s Amendment filed on 12/12/2025. Claims 2-6 and 8-15 are pending in the office action.
Claims 2-6 and 8-9 have been amended.
Claims 1 and 7 have been canceled.
Claims 13-15 are newly added.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 4-6 and 8-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of data processing without significantly more.
As per claim 4:
Claim interpretation: describes “a system” includes “the synthesis dataset of claim 1” related to a circuit routing.
Claim analysis:
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. The claim recites “a system”, therefore, it falls into “a machine”. See MPEP 2106.03. (Step 1: Yes).
Step 2A, Prong One: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04, subsection II, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
The limitation “a system using a neural network comprising the synthetic dataset for pathfinding application of claim 2” that falls directed to mental process as an abstract idea (Step A: Prong One: Yes).
Step 2A, Prong Two: This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception or whether the claim is “directed to” the judicial exception. This evaluation is performed by (1) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (2) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d). The claim recites the additional elements of “a system” and “components”.
The limitation “using a neural network comprising the synthetic dataset for pathfinding application of claim 2” is mere a mental process data gathering, and thus are insignificant extra-solution activity. See MPEP 2106.05(g) (“whether the limitation is significant”). In addition, all uses of the recited judicial exceptions require such data gathering and, as such, these limitations do not impose any meaningful limits on the claim. These limitations amount to necessary data gathering and outputting. See MPEP 2106.05.
Further, the claim recited “a system” and “components” are broadest interpretation to be one of components of a generic computer. The computer is used as a tool to perform the generic computer function to process data. See MPEP 2106.05(f). The computer is used to perform an abstract idea “generate joinable and detached bitmap image for the synthesis dataset”, as discussed above in Step 2A, Prong One, such that it amounts to no more than mere data process to apply the exception using a generic computer. See MPEP 2106.05(f).
Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application (Step 2A, Prong Two: NO), and the claim is directed to the judicial exception. (Step 2A: YES).
Step 2B: This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. See MPEP 2106.05.
As explained with respect to Step 2A, Prong Two, there may be “components” of generic computer as additional elements. The additional elements are at best mere instructions to “apply” the abstract ideas, which cannot provide an inventive concept. See MPEP 2106.05(f). Additional elements were both found to be insignificant extra-solution activity in Step 2A, Prong Two, because they were determined to be insignificant limitations as necessary data gathering. However, a conclusion that an additional element is insignificant extra-solution activity in Step 2A, Prong Two should be re-evaluated in Step 2B. See MPEP 2106.05, subsection I.A.
At Step 2B, the evaluation of the insignificant extra-solution activity consideration takes into account whether or not the extra-solution activity is well understood, routine, and conventional in the field. See MPEP 2106.05(g). As discussed in Step 2A, Prong Two above, the recitations of “using a neural network comprising the synthetic dataset for pathfinding application” is an abstract idea. These elements amount to process data over a are well-understood, routine, conventional activity. See MPEP 2106.05(d), subsection II.
As discussed in Step 2A, Prong Two above, the recitation of “components configured to generate joinable and detached bitmap image for the synthesis dataset” amounts to no more than mere instructions to apply the exception using a generic computer component.
Even when considered in combination, these additional elements represent mere instructions to implement an abstract idea or other exception on a computer and insignificant extra-solution activity, which do not provide an inventive concept. (Step 2B: NO).
Thus, claim 4 is ineligibility subject matter under 35 U.S.C 101.
As per claims 5 and 13-15 are also rejected because are depended directly from claim 4.
As per claim 6:
Claim interpretation: describes “a synthesis dataset” related to circuit pin and routing, wherein the synthetic dataset is generated by an algorithm that joins together a plurality of small, existing routed circuit to produce a high resolution, complex obstacle-avoiding multi-pin routed circuit.
Claim analysis:
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. The claim recites “a synthesis dataset” that related to circuit pins and routing and it does not fall into four categories i.e., process, machine, manufacture, or composition of matter, therefore, it is ineligibility subject matter under 35 U.S.C 101. See MPEP 2106.03. (Step 1: No).
Thus, claim 6 is ineligible subject matter under 35 U.S.C 101.
As per claim 8 are also rejected because are depended directed or indirectly from claim 6.
As per claim 9:
Claim interpretation: describes “a method for generating small bitmaps, each small bitmap comprises at least one terminal or a net segment placed on the small bitmap perimeter; and joining the small bitmaps via edge terminals and/or net segments into a longer, more complex net within a larger bitmap to generate a complex global pathfinding dataset of placed bitmaps”.
Claim analysis:
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. The claim recites “a method”, therefore, it falls into “a process”. See MPEP 2106.03. (Step 1: Yes).
Step 2A, Prong One: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04, subsection II, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
The limitation “generating small bitmaps, each small bitmap comprises at least one terminal or a net segment placed on the small bitmap perimeter; and joining the small bitmaps via edge terminals and/or net segments into a longer, more complex net within a larger bitmap to generate a complex global pathfinding dataset of placed bitmaps” as broadest interpretation that combines data information (dataset) into a bigger/larger dataset that falls into mental process and mathematical concept as an abstract idea (Step A: Prong One: Yes).
Step 2A, Prong Two: This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception or whether the claim is “directed to” the judicial exception. This evaluation is performed by (1) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (2) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d). The claim recites the additional elements of “training dataset according to an algorithm” in the preamble.
The limitation “generating small bitmaps, each small bitmap comprises at least one terminal or a net segment placed on the small bitmap perimeter; and joining the small bitmaps via edge terminals and/or net segments into a longer, more complex net within a larger bitmap to generate a complex global pathfinding dataset of placed bitmaps” is mere a mental process for gathering a larger dataset, and thus are insignificant extra-solution activity. See MPEP 2106.05(g) (“whether the limitation is significant”). In addition, all uses of the recited judicial exceptions require such data gathering and, as such, these limitations do not impose any meaningful limits on the claim. These limitations amount to necessary data gathering and outputting. See MPEP 2106.05.
Further, the claim recited “training dataset” are broadest interpretation as mental process or process using pen/pencil or paper as a tool to perform a mental process. See MPEP 2106.05(f). The human mentally perform an abstract idea “generating small bitmaps, each small bitmap comprises at least one terminal or a net segment placed on the small bitmap perimeter; and joining the small bitmaps via edge terminals and/or net segments into a longer, more complex net within a larger bitmap to generate a complex global pathfinding dataset of placed bitmaps”, as discussed above in Step 2A, Prong One, such that it amounts to no more than mere data process. See MPEP 2106.05(f).
Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application (Step 2A, Prong Two: NO), and the claim is directed to the judicial exception. (Step 2A: YES).
Step 2B: This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. See MPEP 2106.05.
As explained with respect to Step 2A, Prong Two, there may be pen/pencil and paper as additional elements. The additional elements are at best mere process the abstract ideas, which cannot provide an inventive concept. See MPEP 2106.05(f). Additional elements were both found to be insignificant extra-solution activity in Step 2A, Prong Two, because they were determined to be insignificant limitations as necessary data gathering. However, a conclusion that an additional element is insignificant extra-solution activity in Step 2A, Prong Two should be re-evaluated in Step 2B. See MPEP 2106.05, subsection I.A.
At Step 2B, the evaluation of the insignificant extra-solution activity consideration takes into account whether or not the extra-solution activity is well understood, routine, and conventional in the field. See MPEP 2106.05(g). As discussed in Step 2A, Prong Two above, the recitations of “generating small bitmaps, each small bitmap comprises at least one terminal or a net segment placed on the small bitmap perimeter; and joining the small bitmaps via edge terminals and/or net segments into a longer, more complex net within a larger bitmap to generate a complex global pathfinding dataset of placed bitmaps” is an abstract idea. These elements amount to process data over a are well-understood, routine, conventional activity. See MPEP 2106.05(d), subsection II.
As discussed in Step 2A, Prong Two above, the recitation of “generating small bitmaps, each small bitmap comprises at least one terminal or a net segment placed on the small bitmap perimeter; and joining the small bitmaps via edge terminals and/or net segments into a longer, more complex net within a larger bitmap to generate a complex global pathfinding dataset of placed bitmaps” can be process by mental or pen and paper.
Even when considered in combination, these additional elements represent mere instructions to implement an abstract idea and insignificant extra-solution activity, which do not provide an inventive concept. (Step 2B: NO).
Thus, claim 9 is ineligibility subject matter under 35 U.S.C 101.
As per claim 10-12 are also rejected because are depended directly from claim 9.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5 and 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 4: a system includes the synthesis dataset of claim 2, but not clear what is the system to be discloses in this claim.
Moreover, claims 14-15 and the Application specification, paragraph [0012] described “the system can be implemented using a suitable parallel processing system such as a graphic processing unit (GPU), tensor processing unit (TPU), or other suitable system”. Hence, the system does not describe a completed system, not even as a generic computer. Thus, how is the system work?
Furthermore, claim 13 recited “a component” but the specification or the claim does not describe or define what is/are components in the system? Hence, there is unclear subject matter what kind/type of “a component” in the claim language.
As per claim 5 is also rejected because it is depended directly or indirectly from claim 4.
Thus, claims 4-5 and 13-15 are recited indefinite subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6 and 8-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., (U.S. Pub. 2007/0256045) in view of Chouba et al., (U.S Pat. 11,842,136).
As per claims 2-4, 6, 8-10, and 12: Lin teaches a method implemented by a computer-aided router for routing nets for interconnecting terminals of cell instances within an integrated circuit (IC) layout. The invention is suitably implemented in the form of software (i.e., algorithm) residing on computer-readable media which when read and executed by a conventional computer causes the computer to act as a router, selecting routes for nets interconnecting terminals within an IC described by a netlist given positions of those terminals (‘045, par. [0033] [0034], routing algorithm and also see fig. 1 and fig. 4), comprise:
(claims 2, 8-9, and 12) generating within a rectangular bitmap a large set of net routing (fig. 2A-2F, fig. 3, 40A, fig.5, rectangle 78, par. [0037] also see fig. 2A-2F), wherein each tile of the rectangular bitmap comprises at least one terminal or a net segment place on a perimeter of the rectangular bitmap (fig. 1, establish tiles 10, and fig. 2A-2F, tile 30, par. [0006] and fig. 5, tiles 80, par. [0037], tile [0080] congestion map (bit map) see par. [0014], fig. 7A-7B, terminals 84 and net segment 85, also see fig. 8A-8B, terminal 87 in grid J and net second 86 in grid K for example);
(claims 2, 9, and 12) joining (merging) two or more rectangular bitmaps via two edge net segments to obtain a larger bitmap, wherein the larger bitmap comprises a valid grouping of routed nets (claim 10: global pathfinding dataset of placed bitmap) (see fig. 4, global routing 54 and global maze routing 64) with smaller bitmaps being rotated and flipped as needed (the abstract, iteratively merges the tiles into processivity larger tiles, fig. 3, 40A-40C, par. [0008], the larger tile 46 from 4 of tiles 44, while each of tile 44 is merged from tiles 42);
(claims 2 and 12) determining whether the joined bitmaps are a valid grouping if it does not exceed a maximum layout resolution (fig. 3, tile 46 reaches to the coarsest stage into single tile 46, par. [0016] [0017]); and
(claim 2) using the valid grouping of joined bitmaps to produce the routed circuit (fig. 3, from 40C-40E, par. [0009], routed all nets, par. [0016] [0017]);
(claims 2 and 5-6) a high resolution, complex obstacle-avoiding multi-pin routed circuit, comprising the routed circuits (fig. 3, from 40C-40E, fig. 4, finest level 60, fig. 9 and par. [0035] [0036] avoid conflict and par. [0056], tile resolution).
Lin does not teach a target training resolution.
Chouba teaches identifying a plurality of candidate routes for connecting the first circuit element to the second circuit element based on the representation, each of the plurality of candidate routes comprising a respective set of candidate sub-routes; and selecting a candidate route from the plurality of candidate routes by (claims 3-4, and 10) iteratively selecting candidate sub-routes using a neural network for determining target action selection data associated with the configuration by evaluating the simulations and updating the representation of the electrical circuit by providing an action selection signal representing a selection of a candidate sub-route based on the determined target action selection data (i.e., a target training resolution) (‘136, col. 2, ll. 48-60).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Chouba and Lin using Chouba the neural network is trained as candidate sub-routes are selected and so the neural network becomes more efficient at guiding the search to promising solutions thereby reducing the computational expense required to select candidate sub-routes in each iteration (‘136, col. 3, ll. 1-7).
As per claim 11: Lin and Chouba teach the method of claim 10, further comprising the step of: resolving any unprocessed space adjacent the placed bitmap (Lin, par. [0008] [0011] [0014] [0035]).
As per claims 5 and 13: Lin and Chouba teach the system according to claim 4, further comprising components configured to generate joinable (Lin, fig. 3, 40A-40C and fig.11, 97-100) and detached bitmap images for the synthetic dataset (Lin, fig. 3, 40C-40F and fig. 11, 89-97) to form a high resolution, complex global synthetic dataset (Lin, par. [0056], tile resolution and also see fig. 4, global routing 54 and global maze routing 64).
As per claim 14: Lin and Chouba teach the system according to claim 4, comprising a parallel processing (‘136, col. 13, ll. 31-38).
As per claim 15: Lin and Chouba teach the system according to claim 14, wherein the parallel processing system is one selected from a graphics processing unit (GPU) or a tensor processing unit (TPU) (‘136, col. 13, ll. 31-38 and col. 15, ll. 10-29, GPU).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGHIA M DOAN whose telephone number is (571)272-5973. The examiner can normally be reached Mon - Fri 7:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/ Primary Examiner, Art Unit 2851